2 * arch/ppc/kernel/head_44x.S
4 * Kernel execution entry point code.
6 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
7 * Initial PowerPC version.
8 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
10 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
11 * Low-level exception handers, MMU support, and rewrite.
12 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
13 * PowerPC 8xx modifications.
14 * Copyright (c) 1998-1999 TiVo, Inc.
15 * PowerPC 403GCX modifications.
16 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
17 * PowerPC 403GCX/405GP modifications.
18 * Copyright 2000 MontaVista Software Inc.
19 * PPC405 modifications
20 * PowerPC 403GCX/405GP modifications.
21 * Author: MontaVista Software, Inc.
22 * frank_rowand@mvista.com or source@mvista.com
23 * debbie_chu@mvista.com
24 * Copyright 2002-2004 MontaVista Software, Inc.
25 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
27 * This program is free software; you can redistribute it and/or modify it
28 * under the terms of the GNU General Public License as published by the
29 * Free Software Foundation; either version 2 of the License, or (at your
30 * option) any later version.
33 #include <linux/config.h>
34 #include <asm/processor.h>
37 #include <asm/pgtable.h>
38 #include <asm/ibm4xx.h>
39 #include <asm/ibm44x.h>
40 #include <asm/cputable.h>
41 #include <asm/thread_info.h>
42 #include <asm/ppc_asm.h>
43 #include <asm/offsets.h>
49 #define SET_IVOR(vector_number, vector_label) \
50 li r26,vector_label@l; \
51 mtspr SPRN_IVOR##vector_number,r26; \
54 /* As with the other PowerPC ports, it is expected that when code
55 * execution begins here, the following registers contain valid, yet
56 * optional, information:
58 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
59 * r4 - Starting address of the init RAM disk
60 * r5 - Ending address of the init RAM disk
61 * r6 - Start of kernel command line string (e.g. "mem=128")
62 * r7 - End of kernel command line string
69 * Reserve a word at a fixed location to store the address
74 * Save parameters we are passed
81 li r24,0 /* CPU number */
84 * Set up the initial MMU state
86 * We are still executing code at the virtual address
87 * mappings set by the firmware for the base of RAM.
89 * We first invalidate all TLB entries but the one
90 * we are running from. We then load the KERNELBASE
91 * mappings so we can begin to use kernel addresses
92 * natively and so the interrupt vector locations are
93 * permanently pinned (necessary since Book E
94 * implementations always have translation enabled).
96 * TODO: Use the known TLB entry we are running from to
97 * determine which physical region we are located
98 * in. This can be used to determine where in RAM
99 * (on a shared CPU system) or PCI memory space
100 * (on a DRAMless system) we are located.
101 * For now, we assume a perfect world which means
102 * we are located at the base of DRAM (physical 0).
106 * Search TLB for entry that we are currently using.
107 * Invalidate all entries but the one we are using.
109 /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */
110 mfspr r3,SPRN_PID /* Get PID */
111 mfmsr r4 /* Get MSR */
112 andi. r4,r4,MSR_IS@l /* TS=1? */
113 beq wmmucr /* If not, leave STS=0 */
114 oris r3,r3,PPC44x_MMUCR_STS@h /* Set STS=1 */
115 wmmucr: mtspr SPRN_MMUCR,r3 /* Put MMUCR */
118 bl invstr /* Find our address */
119 invstr: mflr r5 /* Make it accessible */
120 tlbsx r23,0,r5 /* Find entry we are in */
121 li r4,0 /* Start at TLB entry 0 */
122 li r3,0 /* Set PAGEID inval value */
123 1: cmpw r23,r4 /* Is this our entry? */
124 beq skpinv /* If so, skip the inval */
125 tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
126 skpinv: addi r4,r4,1 /* Increment */
127 cmpwi r4,64 /* Are we done? */
128 bne 1b /* If not, repeat */
129 isync /* If so, context change */
132 * Configure and load pinned entry into TLB slot 63.
135 lis r3,KERNELBASE@h /* Load the kernel virtual address */
136 ori r3,r3,KERNELBASE@l
138 /* Kernel is at the base of RAM */
139 li r4, 0 /* Load the kernel physical address */
141 /* Load the kernel PID = 0 */
146 /* Initialize MMUCR */
152 clrrwi r3,r3,10 /* Mask off the effective page number */
153 ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M
156 clrrwi r4,r4,10 /* Mask off the real page number */
157 /* ERPN is 0 for first 4GB page */
160 /* Added guarded bit to protect against speculative loads/stores */
162 ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
164 li r0,63 /* TLB slot 63 */
166 tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */
167 tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */
168 tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */
170 /* Force context change */
179 /* If necessary, invalidate original entry we used */
183 tlbwe r6,r23,PPC44x_TLB_PAGEID
187 #ifdef CONFIG_SERIAL_TEXT_DEBUG
189 * Add temporary UART mapping for early debug. This
190 * mapping must be identical to that used by the early
191 * bootloader code since the same asm/serial.h parameters
192 * are used for polled operation.
196 ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M
199 lis r4,0x4000 /* RPN is 0x40000000 */
200 ori r4,r4,0x0001 /* ERPN is 1 for second 4GB page */
204 ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_I | PPC44x_TLB_G)
206 li r0,1 /* TLB slot 1 */
208 tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */
209 tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */
210 tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */
212 ori r3,r3,PPC44x_TLB_TS /* Translation state 1 */
214 li r0,1 /* TLB slot 1 */
216 tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */
217 tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */
218 tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */
220 /* Force context change */
222 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
224 /* Establish the interrupt vector offsets */
225 SET_IVOR(0, CriticalInput);
226 SET_IVOR(1, MachineCheck);
227 SET_IVOR(2, DataStorage);
228 SET_IVOR(3, InstructionStorage);
229 SET_IVOR(4, ExternalInput);
230 SET_IVOR(5, Alignment);
231 SET_IVOR(6, Program);
232 SET_IVOR(7, FloatingPointUnavailable);
233 SET_IVOR(8, SystemCall);
234 SET_IVOR(9, AuxillaryProcessorUnavailable);
235 SET_IVOR(10, Decrementer);
236 SET_IVOR(11, FixedIntervalTimer);
237 SET_IVOR(12, WatchdogTimer);
238 SET_IVOR(13, DataTLBError);
239 SET_IVOR(14, InstructionTLBError);
242 /* Establish the interrupt vector base */
243 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
247 * This is where the main kernel code starts.
252 ori r2,r2,init_task@l
254 /* ptr to current thread */
255 addi r4,r2,THREAD /* init task's THREAD */
259 lis r1,init_thread_union@h
260 ori r1,r1,init_thread_union@l
262 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
267 * Decide what sort of machine this is and initialize the MMU.
277 /* Setup PTE pointers for the Abatron bdiGDB */
278 lis r6, swapper_pg_dir@h
279 ori r6, r6, swapper_pg_dir@l
280 lis r5, abatron_pteptrs@h
281 ori r5, r5, abatron_pteptrs@l
283 ori r4, r4, KERNELBASE@l
284 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
288 lis r4,start_kernel@h
289 ori r4,r4,start_kernel@l
291 ori r3,r3,MSR_KERNEL@l
294 rfi /* change context and jump to start_kernel */
297 * Interrupt vector entry code
299 * The Book E MMUs are always on so we don't need to handle
300 * interrupts in real mode as with previous PPC processors. In
301 * this case we handle interrupts in the kernel virtual address
304 * Interrupt vectors are dynamically placed relative to the
305 * interrupt prefix as determined by the address of interrupt_base.
306 * The interrupt vectors offsets are programmed using the labels
307 * for each interrupt vector entry.
309 * Interrupt vectors must be aligned on a 16 byte boundary.
310 * We align on a 32 byte cache line boundary for good measure.
313 #define NORMAL_EXCEPTION_PROLOG \
314 mtspr SPRN_SPRG0,r10; /* save two registers to work with */\
315 mtspr SPRN_SPRG1,r11; \
316 mtspr SPRN_SPRG2,r1; \
317 mfcr r10; /* save CR in r10 for now */\
318 mfspr r11,SPRN_SRR1; /* check whether user or kernel */\
319 andi. r11,r11,MSR_PR; \
321 mfspr r1,SPRG3; /* if from user, start at top of */\
322 lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\
323 addi r1,r1,THREAD_SIZE; \
324 1: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\
326 stw r10,_CCR(r11); /* save various registers */\
327 stw r12,GPR12(r11); \
330 stw r10,GPR10(r11); \
332 stw r12,GPR11(r11); \
334 stw r10,_LINK(r11); \
340 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
342 SAVE_4GPRS(3, r11); \
346 * Exception prolog for critical exceptions. This is a little different
347 * from the normal exception prolog above since a critical exception
348 * can potentially occur at any point during normal exception processing.
349 * Thus we cannot use the same SPRG registers as the normal prolog above.
350 * Instead we use a couple of words of memory at low physical addresses.
351 * This is OK since we don't support SMP on these processors.
353 /* XXX but we don't have RAM mapped at 0 in space 0 -- paulus. */
354 #define CRITICAL_EXCEPTION_PROLOG \
355 stw r10,crit_r10@l(0); /* save two registers to work with */\
356 stw r11,crit_r11@l(0); \
358 stw r10,crit_sprg0@l(0); \
360 stw r10,crit_sprg1@l(0); \
362 stw r10,crit_sprg4@l(0); \
364 stw r10,crit_sprg5@l(0); \
366 stw r10,crit_sprg6@l(0); \
368 stw r10,crit_sprg7@l(0); \
369 mfspr r10,SPRN_PID; \
370 stw r10,crit_pid@l(0); \
372 stw r10,crit_srr0@l(0); \
374 stw r10,crit_srr1@l(0); \
375 mfcr r10; /* save CR in r10 for now */\
376 mfspr r11,SPRN_CSRR1; /* check whether user or kernel */\
377 andi. r11,r11,MSR_PR; \
378 lis r11,critical_stack_top@h; \
379 ori r11,r11,critical_stack_top@l; \
381 /* COMING FROM USER MODE */ \
382 mfspr r11,SPRG3; /* if from user, start at top of */\
383 lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
384 addi r11,r11,THREAD_SIZE; \
385 1: subi r11,r11,INT_FRAME_SIZE; /* Allocate an exception frame */\
387 stw r10,_CCR(r11); /* save various registers */\
388 stw r12,GPR12(r11); \
391 stw r10,_LINK(r11); \
392 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
393 stw r12,_DEAR(r11); /* since they may have had stuff */\
394 mfspr r9,SPRN_ESR; /* in them at the point where the */\
395 stw r9,_ESR(r11); /* exception was taken */\
401 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
403 SAVE_4GPRS(3, r11); \
409 #define START_EXCEPTION(label) \
413 #define FINISH_EXCEPTION(func) \
414 bl transfer_to_handler_full; \
416 .long ret_from_except_full
418 #define EXCEPTION(n, label, hdlr, xfer) \
419 START_EXCEPTION(label); \
420 NORMAL_EXCEPTION_PROLOG; \
421 addi r3,r1,STACK_FRAME_OVERHEAD; \
424 #define CRITICAL_EXCEPTION(n, label, hdlr) \
425 START_EXCEPTION(label); \
426 CRITICAL_EXCEPTION_PROLOG; \
427 addi r3,r1,STACK_FRAME_OVERHEAD; \
428 EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
429 NOCOPY, transfer_to_handler_full, \
430 ret_from_except_full)
432 #define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \
442 #define COPY_EE(d, s) rlwimi d,s,0,16,16
445 #define EXC_XFER_STD(n, hdlr) \
446 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
447 ret_from_except_full)
449 #define EXC_XFER_LITE(n, hdlr) \
450 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
453 #define EXC_XFER_EE(n, hdlr) \
454 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
455 ret_from_except_full)
457 #define EXC_XFER_EE_LITE(n, hdlr) \
458 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
462 /* Critical Input Interrupt */
463 CRITICAL_EXCEPTION(0x0100, CriticalInput, UnknownException)
465 /* Machine Check Interrupt */
466 CRITICAL_EXCEPTION(0x0200, MachineCheck, MachineCheckException)
468 /* Data Storage Interrupt */
469 START_EXCEPTION(DataStorage)
470 mtspr SPRG0, r10 /* Save some working registers */
479 * Check if it was a store fault, if not then bail
480 * because a user tried to access a kernel or
481 * read-protected page. Otherwise, get the
482 * offending address and handle it.
485 andis. r10, r10, ESR_ST@h
488 mfspr r10, SPRN_DEAR /* Get faulting address */
490 /* If we are faulting a kernel address, we have to use the
491 * kernel page tables.
493 andis. r11, r10, 0x8000
495 lis r11, swapper_pg_dir@h
496 ori r11, r11, swapper_pg_dir@l
499 rlwinm r12,r12,0,0,23 /* Clear TID */
503 /* Get the PGD for the current thread */
508 /* Load PID into MMUCR TID */
509 mfspr r12,SPRN_MMUCR /* Get MMUCR */
510 mfspr r13,SPRN_PID /* Get PID */
511 rlwimi r12,r13,0,24,31 /* Set TID */
516 rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */
517 lwzx r11, r12, r11 /* Get pgd/pmd entry */
518 rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
519 beq 2f /* Bail if no table */
521 rlwimi r12, r10, 23, 20, 28 /* Compute pte address */
522 lwz r11, 4(r12) /* Get pte entry */
524 andi. r13, r11, _PAGE_RW /* Is it writeable? */
525 beq 2f /* Bail if not */
529 ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
530 stw r11, 4(r12) /* Update Linux page table */
532 li r13, PPC44x_TLB_SR@l /* Set SR */
533 rlwimi r13, r11, 29, 29, 29 /* SX = _PAGE_HWEXEC */
534 rlwimi r13, r11, 0, 30, 30 /* SW = _PAGE_RW */
535 rlwimi r13, r11, 29, 28, 28 /* UR = _PAGE_USER */
536 rlwimi r12, r11, 31, 26, 26 /* (_PAGE_USER>>1)->r12 */
537 rlwimi r12, r11, 29, 30, 30 /* (_PAGE_USER>>3)->r12 */
538 and r12, r12, r11 /* HWEXEC/RW & USER */
539 rlwimi r13, r12, 0, 26, 26 /* UX = HWEXEC & USER */
540 rlwimi r13, r12, 3, 27, 27 /* UW = RW & USER */
542 rlwimi r11,r13,0,26,31 /* Insert static perms */
544 rlwinm r11,r11,0,20,15 /* Clear U0-U3 */
546 /* find the TLB index that caused the fault. It has to be here. */
549 tlbwe r11, r14, PPC44x_TLB_ATTRIB /* Write ATTRIB */
551 /* Done...restore registers and get out of here.
561 rfi /* Force context change */
565 * The bailout. Restore registers to pre-exception conditions
566 * and call the heavyweights to help us out.
578 /* Instruction Storage Interrupt */
579 START_EXCEPTION(InstructionStorage)
580 NORMAL_EXCEPTION_PROLOG
581 mr r4,r12 /* Pass SRR0 as arg2 */
582 li r5,0 /* Pass zero as arg3 */
583 addi r3,r1,STACK_FRAME_OVERHEAD
584 EXC_XFER_EE_LITE(0x0400, do_page_fault)
586 /* External Input Interrupt */
587 EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
589 /* Alignment Interrupt */
590 START_EXCEPTION(Alignment)
591 NORMAL_EXCEPTION_PROLOG
592 mfspr r4,SPRN_DEAR /* Grab the DEAR and save it */
594 addi r3,r1,STACK_FRAME_OVERHEAD
595 EXC_XFER_EE(0x0600, AlignmentException)
597 /* Program Interrupt */
598 START_EXCEPTION(Program)
599 NORMAL_EXCEPTION_PROLOG
600 mfspr r4,SPRN_ESR /* Grab the ESR and save it */
602 addi r3,r1,STACK_FRAME_OVERHEAD
603 EXC_XFER_EE(0x700, ProgramCheckException)
605 /* Floating Point Unavailable Interrupt */
606 EXCEPTION(0x2010, FloatingPointUnavailable, UnknownException, EXC_XFER_EE)
608 /* System Call Interrupt */
609 START_EXCEPTION(SystemCall)
610 NORMAL_EXCEPTION_PROLOG
611 EXC_XFER_EE_LITE(0x0c00, DoSyscall)
613 /* Auxillary Processor Unavailable Interrupt */
614 EXCEPTION(0x2020, AuxillaryProcessorUnavailable, UnknownException, EXC_XFER_EE)
616 /* Decrementer Interrupt */
617 START_EXCEPTION(Decrementer)
618 NORMAL_EXCEPTION_PROLOG
619 lis r0,TSR_DIS@h /* Setup the DEC interrupt mask */
620 mtspr SPRN_TSR,r0 /* Clear the DEC interrupt */
621 addi r3,r1,STACK_FRAME_OVERHEAD
622 EXC_XFER_LITE(0x1000, timer_interrupt)
624 /* Fixed Internal Timer Interrupt */
625 /* TODO: Add FIT support */
626 EXCEPTION(0x1010, FixedIntervalTimer, UnknownException, EXC_XFER_EE)
628 /* Watchdog Timer Interrupt */
629 /* TODO: Add watchdog support */
630 CRITICAL_EXCEPTION(0x1020, WatchdogTimer, UnknownException)
632 /* Data TLB Error Interrupt */
633 START_EXCEPTION(DataTLBError)
634 mtspr SPRG0, r10 /* Save some working registers */
641 mfspr r10, SPRN_DEAR /* Get faulting address */
643 /* If we are faulting a kernel address, we have to use the
644 * kernel page tables.
646 andis. r11, r10, 0x8000
648 lis r11, swapper_pg_dir@h
649 ori r11, r11, swapper_pg_dir@l
652 rlwinm r12,r12,0,0,23 /* Clear TID */
656 /* Get the PGD for the current thread */
661 /* Load PID into MMUCR TID */
663 mfspr r13,SPRN_PID /* Get PID */
664 rlwimi r12,r13,0,24,31 /* Set TID */
669 rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */
670 lwzx r11, r12, r11 /* Get pgd/pmd entry */
671 rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
672 beq 2f /* Bail if no table */
674 rlwimi r12, r10, 23, 20, 28 /* Compute pte address */
675 lwz r11, 4(r12) /* Get pte entry */
676 andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
677 beq 2f /* Bail if not present */
679 ori r11, r11, _PAGE_ACCESSED
682 /* Jump to common tlb load */
686 /* The bailout. Restore registers to pre-exception conditions
687 * and call the heavyweights to help us out.
698 /* Instruction TLB Error Interrupt */
700 * Nearly the same as above, except we get our
701 * information from different registers and bailout
702 * to a different point.
704 START_EXCEPTION(InstructionTLBError)
705 mtspr SPRG0, r10 /* Save some working registers */
712 mfspr r10, SRR0 /* Get faulting address */
714 /* If we are faulting a kernel address, we have to use the
715 * kernel page tables.
717 andis. r11, r10, 0x8000
719 lis r11, swapper_pg_dir@h
720 ori r11, r11, swapper_pg_dir@l
723 rlwinm r12,r12,0,0,23 /* Clear TID */
727 /* Get the PGD for the current thread */
732 /* Load PID into MMUCR TID */
734 mfspr r13,SPRN_PID /* Get PID */
735 rlwimi r12,r13,0,24,31 /* Set TID */
740 rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */
741 lwzx r11, r12, r11 /* Get pgd/pmd entry */
742 rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
743 beq 2f /* Bail if no table */
745 rlwimi r12, r10, 23, 20, 28 /* Compute pte address */
746 lwz r11, 4(r12) /* Get pte entry */
747 andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
748 beq 2f /* Bail if not present */
750 ori r11, r11, _PAGE_ACCESSED
753 /* Jump to common TLB load point */
757 /* The bailout. Restore registers to pre-exception conditions
758 * and call the heavyweights to help us out.
769 /* Check for a single step debug exception while in an exception
770 * handler before state has been saved. This is to catch the case
771 * where an instruction that we are trying to single step causes
772 * an exception (eg ITLB/DTLB miss) and thus the first instruction of
773 * the exception handler generates a single step debug exception.
775 * If we get a debug trap on the first instruction of an exception handler,
776 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
777 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
778 * The exception handler was handling a non-critical interrupt, so it will
779 * save (and later restore) the MSR via SPRN_SRR1, which will still have
780 * the MSR_DE bit set.
782 /* Debug Interrupt */
783 CRITICAL_EXCEPTION(0x2000, Debug, DebugException)
785 START_EXCEPTION(Debug)
786 /* This first instruction was already executed by the exception
787 * handler and must be the first instruction of every exception
790 mtspr SPRN_SPRG0,r10 /* Save some working registers... */
792 mtspr SPRN_SPRG4W,r12
793 mfcr r10 /* ..and the cr because we change it */
795 mfspr r11,SPRN_CSRR1 /* MSR at the time of fault */
797 bne+ 2f /* trapped from problem state */
799 mfspr r11,SPRN_CSRR0 /* Faulting instruction address */
800 lis r12, KERNELBASE@h
801 ori r12, r12, KERNELBASE@l
803 blt+ 2f /* addr below exception vectors */
806 ori r12, r12, Debug@l
808 bgt+ 2f /* addr above TLB exception vectors */
810 lis r11,DBSR_IC@h /* Remove the trap status */
814 rlwinm r11,r11,0,23,21 /* clear MSR_DE */
815 mtspr SPRN_CSRR1, r11 /* restore MSR at rcfi without DE */
817 mtcrf 0xff,r10 /* restore registers */
818 mfspr r12,SPRN_SPRG4R
823 rfci /* return to the exception handler */
824 b . /* prevent prefetch past rfci */
827 mtcrf 0xff,r10 /* restore registers */
828 mfspr r12,SPRN_SPRG4R
832 CRIT_EXCEPTION_PROLOG
833 addi r3,r1,STACK_FRAME_OVERHEAD
836 FINISH_EXCEPTION(DebugException)
843 * Data TLB exceptions will bail out to this point
844 * if they can't resolve the lightweight TLB fault.
847 NORMAL_EXCEPTION_PROLOG
848 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
850 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
852 addi r3,r1,STACK_FRAME_OVERHEAD
853 EXC_XFER_EE_LITE(0x0300, do_page_fault)
857 * Both the instruction and data TLB miss get to this
858 * point to load the TLB.
860 * r11 - available to use
861 * r12 - Pointer to the 64-bit PTE
862 * r13 - available to use
863 * r14 - available to use
864 * MMUCR - loaded with proper value when we get here
865 * Upon exit, we reload everything and RFI.
869 * We set execute, because we don't have the granularity to
870 * properly set this at the page level (Linux problem).
871 * If shared is set, we cause a zero PID->TID load.
872 * Many of these bits are software only. Bits we don't set
873 * here we (properly should) assume have the appropriate value.
876 /* Load the next available TLB index */
877 lis r13, tlb_44x_index@ha
878 lwz r14, tlb_44x_index@l(r13)
879 /* Load the TLB high watermark */
880 lis r13, tlb_44x_hwater@ha
881 lwz r11, tlb_44x_hwater@l(r13)
883 /* Increment, rollover, and store TLB index */
885 cmpw 0, r14, r11 /* reserve entries */
889 /* Store the next available TLB index */
890 lis r13, tlb_44x_index@ha
891 stw r14, tlb_44x_index@l(r13)
893 lwz r13, 0(r12) /* Get MS word of PTE */
894 lwz r11, 4(r12) /* Get LS word of PTE */
895 rlwimi r13, r11, 0, 0 , 19 /* Insert RPN */
896 tlbwe r13, r14, PPC44x_TLB_XLAT /* Write XLAT */
899 * Create PAGEID. This is the faulting address,
900 * page size, and valid flag.
902 li r12, PPC44x_TLB_VALID | PPC44x_TLB_4K
903 rlwimi r10, r12, 0, 20, 31 /* Insert valid and page size */
904 tlbwe r10, r14, PPC44x_TLB_PAGEID /* Write PAGEID */
906 li r13, PPC44x_TLB_SR@l /* Set SR */
907 rlwimi r13, r11, 0, 30, 30 /* Set SW = _PAGE_RW */
908 rlwimi r13, r11, 29, 29, 29 /* SX = _PAGE_HWEXEC */
909 rlwimi r13, r11, 29, 28, 28 /* UR = _PAGE_USER */
910 rlwimi r12, r11, 31, 26, 26 /* (_PAGE_USER>>1)->r12 */
911 and r12, r12, r11 /* HWEXEC & USER */
912 rlwimi r13, r12, 0, 26, 26 /* UX = HWEXEC & USER */
914 rlwimi r11, r13, 0, 26, 31 /* Insert static perms */
915 rlwinm r11, r11, 0, 20, 15 /* Clear U0-U3 */
916 tlbwe r11, r14, PPC44x_TLB_ATTRIB /* Write ATTRIB */
918 /* Done...restore registers and get out of here.
927 rfi /* Force context change */
934 * extern void giveup_altivec(struct task_struct *prev)
936 * The 44x core does not have an AltiVec unit.
938 _GLOBAL(giveup_altivec)
942 * extern void giveup_fpu(struct task_struct *prev)
944 * The 44x core does not have an FPU.
950 * extern void abort(void)
952 * At present, this routine just applies a system reset.
956 oris r13,r13,DBCR0_RST_SYSTEM@h
961 #ifdef CONFIG_BDI_SWITCH
962 /* Context switch the PTE pointer for the Abatron BDI2000.
963 * The PGDIR is the second parameter.
965 lis r5, abatron_pteptrs@h
966 ori r5, r5, abatron_pteptrs@l
970 isync /* Force context change */
974 * We put a few things here that have to be page-aligned. This stuff
975 * goes at the beginning of the data segment, which is page-aligned.
979 _GLOBAL(empty_zero_page)
983 * To support >32-bit physical addresses, we use an 8KB pgdir.
985 _GLOBAL(swapper_pg_dir)
988 /* Stack for handling critical exceptions from kernel mode */
990 critical_stack_bottom:
996 * This space gets a copy of optional info passed to us by the bootstrap
997 * which is used to pass parameters into the kernel like root=/dev/sda1, etc.
1003 * Room for two PTE pointers, usually the kernel and current user pointers
1004 * to their respective root page table.
1010 * This area is used for temporarily saving registers during the
1011 * critical exception prolog.