2 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
3 * Initial PowerPC version.
4 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
7 * Low-level exception handers, MMU support, and rewrite.
8 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
9 * PowerPC 8xx modifications.
10 * Copyright (c) 1998-1999 TiVo, Inc.
11 * PowerPC 403GCX modifications.
12 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
13 * PowerPC 403GCX/405GP modifications.
14 * Copyright 2000 MontaVista Software Inc.
15 * PPC405 modifications
16 * PowerPC 403GCX/405GP modifications.
17 * Author: MontaVista Software, Inc.
18 * frank_rowand@mvista.com or source@mvista.com
19 * debbie_chu@mvista.com
22 * Module name: head_4xx.S
25 * Kernel execution entry point code.
27 * This program is free software; you can redistribute it and/or
28 * modify it under the terms of the GNU General Public License
29 * as published by the Free Software Foundation; either version
30 * 2 of the License, or (at your option) any later version.
34 #include <linux/config.h>
35 #include <asm/processor.h>
38 #include <asm/pgtable.h>
39 #include <asm/ibm4xx.h>
40 #include <asm/cputable.h>
41 #include <asm/thread_info.h>
42 #include <asm/ppc_asm.h>
43 #include <asm/offsets.h>
45 /* As with the other PowerPC ports, it is expected that when code
46 * execution begins here, the following registers contain valid, yet
47 * optional, information:
49 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
50 * r4 - Starting address of the init RAM disk
51 * r5 - Ending address of the init RAM disk
52 * r6 - Start of kernel command line string (e.g. "mem=96m")
53 * r7 - End of kernel command line string
55 * This is all going to change RSN when we add bi_recs....... -- Dan
61 /* Save parameters we are passed.
69 /* We have to turn on the MMU right away so we get cache modes
74 /* We now have the lower 16 Meg mapped into TLB entries, and the caches
79 ori r0,r0,MSR_KERNEL@l
82 ori r0,r0,start_here@l
86 b . /* prevent prefetch past rfi */
89 * This area is used for temporarily saving registers during the
90 * critical exception prolog.
118 * Exception vector entry code. This code runs with address translation
119 * turned off (i.e. using physical addresses). We assume SPRG3 has the
120 * physical address of the current task thread_struct.
121 * Note that we have to have decremented r1 before we write to any fields
122 * of the exception frame, since a critical interrupt could occur at any
123 * time, and it will write to the area immediately below the current r1.
125 #define NORMAL_EXCEPTION_PROLOG \
126 mtspr SPRN_SPRG0,r10; /* save two registers to work with */\
127 mtspr SPRN_SPRG1,r11; \
128 mtspr SPRN_SPRG2,r1; \
129 mfcr r10; /* save CR in r10 for now */\
130 mfspr r11,SPRN_SRR1; /* check whether user or kernel */\
131 andi. r11,r11,MSR_PR; \
133 mfspr r1,SPRG3; /* if from user, start at top of */\
134 lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\
135 addi r1,r1,THREAD_SIZE; \
136 1: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\
138 stw r10,_CCR(r11); /* save various registers */\
139 stw r12,GPR12(r11); \
142 stw r10,GPR10(r11); \
144 stw r12,GPR11(r11); \
146 stw r10,_LINK(r11); \
152 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
154 SAVE_4GPRS(3, r11); \
158 * Exception prolog for critical exceptions. This is a little different
159 * from the normal exception prolog above since a critical exception
160 * can potentially occur at any point during normal exception processing.
161 * Thus we cannot use the same SPRG registers as the normal prolog above.
162 * Instead we use a couple of words of memory at low physical addresses.
163 * This is OK since we don't support SMP on these processors.
165 #define CRITICAL_EXCEPTION_PROLOG \
166 stw r10,crit_r10@l(0); /* save two registers to work with */\
167 stw r11,crit_r11@l(0); \
169 stw r10,crit_sprg0@l(0); \
171 stw r10,crit_sprg1@l(0); \
173 stw r10,crit_sprg4@l(0); \
175 stw r10,crit_sprg5@l(0); \
177 stw r10,crit_sprg6@l(0); \
179 stw r10,crit_sprg7@l(0); \
180 mfspr r10,SPRN_PID; \
181 stw r10,crit_pid@l(0); \
183 stw r10,crit_srr0@l(0); \
185 stw r10,crit_srr1@l(0); \
186 mfcr r10; /* save CR in r10 for now */\
187 mfspr r11,SPRN_SRR3; /* check whether user or kernel */\
188 andi. r11,r11,MSR_PR; \
189 lis r11,critical_stack_top@h; \
190 ori r11,r11,critical_stack_top@l; \
192 /* COMING FROM USER MODE */ \
193 mfspr r11,SPRG3; /* if from user, start at top of */\
194 lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
195 addi r11,r11,THREAD_SIZE; \
196 1: subi r11,r11,INT_FRAME_SIZE; /* Allocate an exception frame */\
198 stw r10,_CCR(r11); /* save various registers */\
199 stw r12,GPR12(r11); \
202 stw r10,_LINK(r11); \
203 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
204 stw r12,_DEAR(r11); /* since they may have had stuff */\
205 mfspr r9,SPRN_ESR; /* in them at the point where the */\
206 stw r9,_ESR(r11); /* exception was taken */\
212 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
214 SAVE_4GPRS(3, r11); \
218 * State at this point:
219 * r9 saved in stack frame, now saved SRR3 & ~MSR_WE
220 * r10 saved in crit_r10 and in stack frame, trashed
221 * r11 saved in crit_r11 and in stack frame,
222 * now phys stack/exception frame pointer
223 * r12 saved in stack frame, now saved SRR2
224 * SPRG0,1,4,5,6,7 saved in crit_sprg0,1,4,5,6,7
225 * PID saved in crit_pid
226 * SRR0,1 saved in crit_srr0,1
227 * CR saved in stack frame, CR0.EQ = !SRR3.PR
228 * LR, DEAR, ESR in stack frame
229 * r1 saved in stack frame, now virt stack/excframe pointer
230 * r0, r3-r8 saved in stack frame
236 #define START_EXCEPTION(n, label) \
240 #define EXCEPTION(n, label, hdlr, xfer) \
241 START_EXCEPTION(n, label); \
242 NORMAL_EXCEPTION_PROLOG; \
243 addi r3,r1,STACK_FRAME_OVERHEAD; \
246 #define CRITICAL_EXCEPTION(n, label, hdlr) \
247 START_EXCEPTION(n, label); \
248 CRITICAL_EXCEPTION_PROLOG; \
249 addi r3,r1,STACK_FRAME_OVERHEAD; \
250 EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
251 NOCOPY, crit_transfer_to_handler, \
254 #define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \
264 #define COPY_EE(d, s) rlwimi d,s,0,16,16
267 #define EXC_XFER_STD(n, hdlr) \
268 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
269 ret_from_except_full)
271 #define EXC_XFER_LITE(n, hdlr) \
272 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
275 #define EXC_XFER_EE(n, hdlr) \
276 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
277 ret_from_except_full)
279 #define EXC_XFER_EE_LITE(n, hdlr) \
280 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
285 * 0x0100 - Critical Interrupt Exception
287 CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, UnknownException)
290 * 0x0200 - Machine Check Exception
292 CRITICAL_EXCEPTION(0x0200, MachineCheck, MachineCheckException)
295 * 0x0300 - Data Storage Exception
296 * This happens for just a few reasons. U0 set (but we don't do that),
297 * or zone protection fault (user violation, write to protected page).
298 * If this is just an update of modified status, we do that quickly
299 * and exit. Otherwise, we call heavywight functions to do the work.
301 START_EXCEPTION(0x0300, DataStorage)
302 mtspr SPRG0, r10 /* Save some working registers */
320 /* First, check if it was a zone fault (which means a user
321 * tried to access a kernel or read-protected page - always
322 * a SEGV). All other faults here must be stores, so no
323 * need to check ESR_DST as well. */
325 andis. r10, r10, ESR_DIZ@h
328 mfspr r10, SPRN_DEAR /* Get faulting address */
330 /* If we are faulting a kernel address, we have to use the
331 * kernel page tables.
333 andis. r11, r10, 0x8000
335 lis r11, swapper_pg_dir@h
336 ori r11, r11, swapper_pg_dir@l
338 mtspr SPRN_PID, r9 /* TLB will have 0 TID */
341 /* Get the PGD for the current thread.
348 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
349 lwz r11, 0(r11) /* Get L1 entry */
350 rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */
351 beq 2f /* Bail if no table */
353 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
354 lwz r11, 0(r12) /* Get Linux PTE */
356 andi. r9, r11, _PAGE_RW /* Is it writeable? */
357 beq 2f /* Bail if not */
361 ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
362 stw r11, 0(r12) /* Update Linux page table */
364 /* Most of the Linux PTE is ready to load into the TLB LO.
365 * We set ZSEL, where only the LS-bit determines user access.
366 * We set execute, because we don't have the granularity to
367 * properly set this at the page level (Linux problem).
368 * If shared is set, we cause a zero PID->TID load.
369 * Many of these bits are software only. Bits we don't set
370 * here we (properly should) assume have the appropriate value.
373 andc r11, r11, r12 /* Make sure 20, 21 are zero */
375 /* find the TLB index that caused the fault. It has to be here.
379 tlbwe r11, r9, TLB_DATA /* Load TLB LO */
381 /* Done...restore registers and get out of here.
401 rfi /* Should sync shadow TLBs */
402 b . /* prevent prefetch past rfi */
405 /* The bailout. Restore registers to pre-exception conditions
406 * and call the heavyweights to help us out.
428 * 0x0400 - Instruction Storage Exception
429 * This is caused by a fetch from non-execute or guarded pages.
431 START_EXCEPTION(0x0400, InstructionAccess)
432 NORMAL_EXCEPTION_PROLOG
433 mr r4,r12 /* Pass SRR0 as arg2 */
434 li r5,0 /* Pass zero as arg3 */
435 EXC_XFER_EE_LITE(0x400, handle_page_fault)
437 /* 0x0500 - External Interrupt Exception */
438 EXCEPTION(0x0500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
440 /* 0x0600 - Alignment Exception */
441 START_EXCEPTION(0x0600, Alignment)
442 NORMAL_EXCEPTION_PROLOG
443 mfspr r4,SPRN_DEAR /* Grab the DEAR and save it */
445 addi r3,r1,STACK_FRAME_OVERHEAD
446 EXC_XFER_EE(0x600, AlignmentException)
448 /* 0x0700 - Program Exception */
449 START_EXCEPTION(0x0700, ProgramCheck)
450 NORMAL_EXCEPTION_PROLOG
451 mfspr r4,SPRN_ESR /* Grab the ESR and save it */
453 addi r3,r1,STACK_FRAME_OVERHEAD
454 EXC_XFER_STD(0x700, ProgramCheckException)
456 EXCEPTION(0x0800, Trap_08, UnknownException, EXC_XFER_EE)
457 EXCEPTION(0x0900, Trap_09, UnknownException, EXC_XFER_EE)
458 EXCEPTION(0x0A00, Trap_0A, UnknownException, EXC_XFER_EE)
459 EXCEPTION(0x0B00, Trap_0B, UnknownException, EXC_XFER_EE)
461 /* 0x0C00 - System Call Exception */
462 START_EXCEPTION(0x0C00, SystemCall)
463 NORMAL_EXCEPTION_PROLOG
464 EXC_XFER_EE_LITE(0xc00, DoSyscall)
466 EXCEPTION(0x0D00, Trap_0D, UnknownException, EXC_XFER_EE)
467 EXCEPTION(0x0E00, Trap_0E, UnknownException, EXC_XFER_EE)
468 EXCEPTION(0x0F00, Trap_0F, UnknownException, EXC_XFER_EE)
470 /* 0x1000 - Programmable Interval Timer (PIT) Exception */
471 START_EXCEPTION(0x1000, Decrementer)
472 NORMAL_EXCEPTION_PROLOG
474 mtspr SPRN_TSR,r0 /* Clear the PIT exception */
475 addi r3,r1,STACK_FRAME_OVERHEAD
476 EXC_XFER_LITE(0x1000, timer_interrupt)
480 * FIT and WDT handlers are not implemented yet.
483 /* 0x1010 - Fixed Interval Timer (FIT) Exception
485 STND_EXCEPTION(0x1010, FITException, UnknownException)
487 /* 0x1020 - Watchdog Timer (WDT) Exception
490 CRITICAL_EXCEPTION(0x1020, WDTException, UnknownException)
493 /* 0x1100 - Data TLB Miss Exception
494 * As the name implies, translation is not in the MMU, so search the
495 * page tables and fix it. The only purpose of this function is to
496 * load TLB entries from the page table if they exist.
498 START_EXCEPTION(0x1100, DTLBMiss)
499 mtspr SPRG0, r10 /* Save some working registers */
516 mfspr r10, SPRN_DEAR /* Get faulting address */
518 /* If we are faulting a kernel address, we have to use the
519 * kernel page tables.
521 andis. r11, r10, 0x8000
523 lis r11, swapper_pg_dir@h
524 ori r11, r11, swapper_pg_dir@l
526 mtspr SPRN_PID, r9 /* TLB will have 0 TID */
529 /* Get the PGD for the current thread.
536 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
537 lwz r12, 0(r11) /* Get L1 entry */
538 andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */
539 beq 2f /* Bail if no table */
541 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
542 lwz r11, 0(r12) /* Get Linux PTE */
543 andi. r9, r11, _PAGE_PRESENT
546 ori r11, r11, _PAGE_ACCESSED
549 /* Create TLB tag. This is the faulting address plus a static
550 * set of bits. These are size, valid, E, U0.
553 rlwimi r10, r12, 0, 20, 31
557 2: /* Check for possible large-page pmd entry */
558 rlwinm. r9, r12, 2, 22, 24
561 /* Create TLB tag. This is the faulting address, plus a static
562 * set of bits (valid, E, U0) plus the size from the PMD.
565 rlwimi r10, r9, 0, 20, 31
571 /* The bailout. Restore registers to pre-exception conditions
572 * and call the heavyweights to help us out.
593 /* 0x1200 - Instruction TLB Miss Exception
594 * Nearly the same as above, except we get our information from different
595 * registers and bailout to a different point.
597 START_EXCEPTION(0x1200, ITLBMiss)
598 mtspr SPRG0, r10 /* Save some working registers */
615 mfspr r10, SRR0 /* Get faulting address */
617 /* If we are faulting a kernel address, we have to use the
618 * kernel page tables.
620 andis. r11, r10, 0x8000
622 lis r11, swapper_pg_dir@h
623 ori r11, r11, swapper_pg_dir@l
625 mtspr SPRN_PID, r9 /* TLB will have 0 TID */
628 /* Get the PGD for the current thread.
635 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
636 lwz r12, 0(r11) /* Get L1 entry */
637 andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */
638 beq 2f /* Bail if no table */
640 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
641 lwz r11, 0(r12) /* Get Linux PTE */
642 andi. r9, r11, _PAGE_PRESENT
645 ori r11, r11, _PAGE_ACCESSED
648 /* Create TLB tag. This is the faulting address plus a static
649 * set of bits. These are size, valid, E, U0.
652 rlwimi r10, r12, 0, 20, 31
656 2: /* Check for possible large-page pmd entry */
657 rlwinm. r9, r12, 2, 22, 24
660 /* Create TLB tag. This is the faulting address, plus a static
661 * set of bits (valid, E, U0) plus the size from the PMD.
664 rlwimi r10, r9, 0, 20, 31
670 /* The bailout. Restore registers to pre-exception conditions
671 * and call the heavyweights to help us out.
692 EXCEPTION(0x1300, Trap_13, UnknownException, EXC_XFER_EE)
693 EXCEPTION(0x1400, Trap_14, UnknownException, EXC_XFER_EE)
694 EXCEPTION(0x1500, Trap_15, UnknownException, EXC_XFER_EE)
695 EXCEPTION(0x1600, Trap_16, UnknownException, EXC_XFER_EE)
696 #ifdef CONFIG_IBM405_ERR51
697 /* 405GP errata 51 */
698 START_EXCEPTION(0x1700, Trap_17)
701 EXCEPTION(0x1700, Trap_17, UnknownException, EXC_XFER_EE)
703 EXCEPTION(0x1800, Trap_18, UnknownException, EXC_XFER_EE)
704 EXCEPTION(0x1900, Trap_19, UnknownException, EXC_XFER_EE)
705 EXCEPTION(0x1A00, Trap_1A, UnknownException, EXC_XFER_EE)
706 EXCEPTION(0x1B00, Trap_1B, UnknownException, EXC_XFER_EE)
707 EXCEPTION(0x1C00, Trap_1C, UnknownException, EXC_XFER_EE)
708 EXCEPTION(0x1D00, Trap_1D, UnknownException, EXC_XFER_EE)
709 EXCEPTION(0x1E00, Trap_1E, UnknownException, EXC_XFER_EE)
710 EXCEPTION(0x1F00, Trap_1F, UnknownException, EXC_XFER_EE)
712 /* 0x2000 - Debug Exception
714 START_EXCEPTION(0x2000, DebugTrap)
715 CRITICAL_EXCEPTION_PROLOG
718 * If this is a single step or branch-taken exception in an
719 * exception entry sequence, it was probably meant to apply to
720 * the code where the exception occurred (since exception entry
721 * doesn't turn off DE automatically). We simulate the effect
722 * of turning off DE on entry to an exception handler by turning
723 * off DE in the SRR3 value and clearing the debug status.
725 mfspr r10,SPRN_DBSR /* check single-step/branch taken */
726 andis. r10,r10,(DBSR_IC|DBSR_BT)@h
728 andi. r0,r9,MSR_IR|MSR_PR /* check supervisor + MMU off */
729 beq 2f /* branch if we need to fix it up... */
731 /* continue normal handling for a critical exception... */
732 1: mfspr r4,SPRN_DBSR
733 addi r3,r1,STACK_FRAME_OVERHEAD
734 EXC_XFER_TEMPLATE(DebugException, 0x2002, \
735 (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
736 NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
738 /* here it looks like we got an inappropriate debug exception. */
739 2: rlwinm r9,r9,0,~MSR_DE /* clear DE in the SRR3 value */
740 mtspr SPRN_DBSR,r10 /* clear the IC/BT debug intr status */
741 /* restore state and get out */
750 lwz r10,crit_r10@l(0)
751 lwz r11,crit_r11@l(0)
757 * The other Data TLB exceptions bail out to this point
758 * if they can't resolve the lightweight TLB fault.
761 NORMAL_EXCEPTION_PROLOG
762 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
764 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
765 EXC_XFER_EE_LITE(0x300, handle_page_fault)
767 /* Other PowerPC processors, namely those derived from the 6xx-series
768 * have vectors from 0x2100 through 0x2F00 defined, but marked as reserved.
769 * However, for the 4xx-series processors these are neither defined nor
773 /* Damn, I came up one instruction too many to fit into the
774 * exception space :-). Both the instruction and data TLB
775 * miss get to this point to load the TLB.
776 * r10 - TLB_TAG value
778 * r12, r9 - avilable to use
779 * PID - loaded with proper value when we get here
780 * Upon exit, we reload everything and RFI.
781 * Actually, it will fit now, but oh well.....a common place
787 /* load the next available TLB index.
789 lwz r9, tlb_4xx_index@l(0)
791 andi. r9, r9, (PPC4XX_TLB_SIZE-1)
792 stw r9, tlb_4xx_index@l(0)
796 * Clear out the software-only bits in the PTE to generate the
797 * TLB_DATA value. These are the bottom 2 bits of the RPM, the
798 * top 3 bits of the zone field, and M.
803 tlbwe r11, r9, TLB_DATA /* Load TLB LO */
804 tlbwe r10, r9, TLB_TAG /* Load TLB HI */
806 /* Done...restore registers and get out of here.
826 rfi /* Should sync shadow TLBs */
827 b . /* prevent prefetch past rfi */
829 /* extern void giveup_fpu(struct task_struct *prev)
831 * The PowerPC 4xx family of processors do not have an FPU, so this just
837 /* This is where the main kernel code starts.
843 ori r2,r2,init_task@l
845 /* ptr to phys current thread */
847 addi r4,r4,THREAD /* init task's THREAD */
851 lis r1,init_thread_union@ha
852 addi r1,r1,init_thread_union@l
854 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
856 bl early_init /* We have to do this with MMU on */
859 * Decide what sort of machine this is and initialize the MMU.
869 /* Go back to running unmapped so we can load up new values
870 * and change to using our exception vectors.
871 * On the 4xx, all we have to do is invalidate the TLB to clear
872 * the old 16M byte TLB mappings.
877 lis r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@h
878 ori r3,r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@l
882 b . /* prevent prefetch past rfi */
884 /* Load up the kernel context */
886 sync /* Flush to memory before changing TLB */
888 isync /* Flush shadow TLBs */
890 /* set up the PTE pointers for the Abatron bdiGDB.
892 lis r6, swapper_pg_dir@h
893 ori r6, r6, swapper_pg_dir@l
894 lis r5, abatron_pteptrs@h
895 ori r5, r5, abatron_pteptrs@l
896 stw r5, 0xf0(r0) /* Must match your Abatron config file */
900 /* Now turn on the MMU for real! */
902 ori r4,r4,MSR_KERNEL@l
903 lis r3,start_kernel@h
904 ori r3,r3,start_kernel@l
907 rfi /* enable MMU and jump to start_kernel */
908 b . /* prevent prefetch past rfi */
910 /* Set up the initial MMU state so we can do the first level of
911 * kernel initialization. This maps the first 16 MBytes of memory 1:1
912 * virtual to physical and more importantly sets the cache mode.
915 tlbia /* Invalidate all TLB entries */
918 /* We should still be executing code at physical address 0x0000xxxx
919 * at this point. However, start_here is at virtual address
920 * 0xC000xxxx. So, set up a TLB mapping to cover this once
921 * translation is enabled.
924 lis r3,KERNELBASE@h /* Load the kernel virtual address */
925 ori r3,r3,KERNELBASE@l
926 tophys(r4,r3) /* Load the kernel physical address */
928 iccci r0,r3 /* Invalidate the i-cache before use */
930 /* Load the kernel PID.
936 /* Configure and load two entries into TLB slots 62 and 63.
937 * In case we are pinning TLBs, these are reserved in by the
938 * other TLB functions. If not reserving, then it doesn't
939 * matter where they are loaded.
941 clrrwi r4,r4,10 /* Mask off the real page number */
942 ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */
944 clrrwi r3,r3,10 /* Mask off the effective page number */
945 ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M))
947 li r0,63 /* TLB slot 63 */
949 tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry */
950 tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */
952 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(SERIAL_DEBUG_IO_BASE)
954 /* Load a TLB entry for the UART, so that ppc4xx_progress() can use
955 * the UARTs nice and early. We use a 4k real==virtual mapping. */
957 lis r3,SERIAL_DEBUG_IO_BASE@h
958 ori r3,r3,SERIAL_DEBUG_IO_BASE@l
961 ori r4,r4,(TLB_WR|TLB_I|TLB_M|TLB_G)
964 ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K))
966 li r0,0 /* TLB slot 0 */
969 #endif /* CONFIG_SERIAL_DEBUG_TEXT && SERIAL_DEBUG_IO_BASE */
973 /* Establish the exception vector base
975 lis r4,KERNELBASE@h /* EVPR only uses the high 16-bits */
976 tophys(r0,r4) /* Use the physical address */
983 oris r13,r13,DBCR0_RST_SYSTEM@h
988 #ifdef CONFIG_BDI_SWITCH
989 /* Context switch the PTE pointer for the Abatron BDI2000.
990 * The PGDIR is the second parameter.
998 isync /* Need an isync to flush shadow */
999 /* TLBs after changing PID */
1002 /* We put a few things here that have to be page-aligned. This stuff
1003 * goes at the beginning of the data segment, which is page-aligned.
1007 _GLOBAL(empty_zero_page)
1009 _GLOBAL(swapper_pg_dir)
1013 /* Stack for handling critical exceptions from kernel mode */
1015 critical_stack_bottom:
1020 /* This space gets a copy of optional info passed to us by the bootstrap
1021 * which is used to pass parameters into the kernel like root=/dev/sda1, etc.
1026 /* Room for two PTE pointers, usually the kernel and current user pointers
1027 * to their respective root page table.