2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
15 #include <linux/config.h>
16 #include <linux/sys.h>
17 #include <asm/unistd.h>
18 #include <asm/errno.h>
19 #include <asm/processor.h>
21 #include <asm/cache.h>
22 #include <asm/cputable.h>
24 #include <asm/ppc_asm.h>
25 #include <asm/thread_info.h>
26 #include <asm/offsets.h>
39 * Returns (address we're running at) - (address we were linked at)
40 * for use before the text and data are mapped to KERNELBASE.
53 * add_reloc_offset(x) returns x + reloc_offset().
55 _GLOBAL(add_reloc_offset)
67 * sub_reloc_offset(x) returns x - reloc_offset().
69 _GLOBAL(sub_reloc_offset)
81 * reloc_got2 runs through the .got2 section adding an offset
86 lis r7,__got2_start@ha
87 addi r7,r7,__got2_start@l
89 addi r8,r8,__got2_end@l
110 * called with r3 = data offset and r4 = CPU number
113 _GLOBAL(identify_cpu)
114 addis r8,r3,cpu_specs@ha
115 addi r8,r8,cpu_specs@l
118 lwz r5,CPU_SPEC_PVR_MASK(r8)
120 lwz r6,CPU_SPEC_PVR_VALUE(r8)
123 addi r8,r8,CPU_SPEC_ENTRY_SIZE
126 addis r6,r3,cur_cpu_spec@ha
127 addi r6,r6,cur_cpu_spec@l
134 * do_cpu_ftr_fixups - goes through the list of CPU feature fixups
135 * and writes nop's over sections of code that don't apply for this cpu.
136 * r3 = data offset (not changed)
138 _GLOBAL(do_cpu_ftr_fixups)
139 /* Get CPU 0 features */
140 addis r6,r3,cur_cpu_spec@ha
141 addi r6,r6,cur_cpu_spec@l
144 lwz r4,CPU_SPEC_FEATURES(r4)
146 /* Get the fixup table */
147 addis r6,r3,__start___ftr_fixup@ha
148 addi r6,r6,__start___ftr_fixup@l
149 addis r7,r3,__stop___ftr_fixup@ha
150 addi r7,r7,__stop___ftr_fixup@l
156 lwz r8,-16(r6) /* mask */
158 lwz r9,-12(r6) /* value */
161 lwz r8,-8(r6) /* section begin */
162 lwz r9,-4(r6) /* section end */
165 /* write nops over the section of code */
166 /* todo: if large section, add a branch at the start of it */
170 lis r0,0x60000000@h /* nop */
172 andi. r10,r4,CPU_FTR_SPLIT_ID_CACHE@l
174 dcbst 0,r8 /* suboptimal, but simpler */
179 sync /* additional sync needed on g4 */
184 * call_setup_cpu - call the setup_cpu function for this cpu
185 * r3 = data offset, r24 = cpu number
187 * Setup function is called with:
190 * r5 = ptr to CPU spec (relocated)
192 _GLOBAL(call_setup_cpu)
193 addis r5,r3,cur_cpu_spec@ha
194 addi r5,r5,cur_cpu_spec@l
198 lwz r6,CPU_SPEC_SETUP(r5)
204 #if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
206 /* This gets called by via-pmu.c to switch the PLL selection
207 * on 750fx CPU. This function should really be moved to some
208 * other place (as most of the cpufreq code in via-pmu
210 _GLOBAL(low_choose_750fx_pll)
216 /* If switching to PLL1, disable HID0:BTIC */
227 /* Calc new HID1 value */
228 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
229 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
230 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
234 /* Store new HID1 image */
238 addis r6,r6,nap_save_hid1@ha
239 stw r4,nap_save_hid1@l(r6)
241 /* If switching to PLL0, enable HID0:BTIC */
256 #endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
258 /* void local_save_flags_ptr(unsigned long *flags) */
259 _GLOBAL(local_save_flags_ptr)
264 * Need these nops here for taking over save/restore to
285 _GLOBAL(local_save_flags_ptr_end)
287 /* void local_irq_restore(unsigned long flags) */
288 _GLOBAL(local_irq_restore)
290 * Just set/clear the MSR_EE bit through restore/flags but do not
291 * change anything else. This is needed by the RT system and makes
296 /* Copy all except the MSR_EE bit from r4 (current MSR value)
297 to r3. This is the sort of thing the rlwimi instruction is
298 designed for. -- paulus. */
300 /* Check if things are setup the way we want _already_. */
326 _GLOBAL(local_irq_restore_end)
328 _GLOBAL(local_irq_disable)
329 mfmsr r0 /* Get current interrupt state */
330 rlwinm r3,r0,16+1,32-1,31 /* Extract old value of 'EE' */
331 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
332 SYNC /* Some chip revs have problems here... */
333 mtmsr r0 /* Update machine state */
336 * Need these nops here for taking over save/restore to
355 _GLOBAL(local_irq_disable_end)
357 _GLOBAL(local_irq_enable)
358 mfmsr r3 /* Get current state */
359 ori r3,r3,MSR_EE /* Turn on 'EE' bit */
360 SYNC /* Some chip revs have problems here... */
361 mtmsr r3 /* Update machine state */
364 * Need these nops here for taking over save/restore to
384 _GLOBAL(local_irq_enable_end)
387 * complement mask on the msr then "or" some values on.
388 * _nmask_and_or_msr(nmask, value_to_or)
390 _GLOBAL(_nmask_and_or_msr)
391 mfmsr r0 /* Get current msr */
392 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
393 or r0,r0,r4 /* Or on the bits in r4 (second parm) */
394 SYNC /* Some chip revs have problems here... */
395 mtmsr r0 /* Update machine state */
404 #if defined(CONFIG_40x)
405 sync /* Flush to memory before changing mapping */
407 isync /* Flush shadow TLB */
408 #elif defined(CONFIG_44x)
412 /* Load high watermark */
413 lis r4,tlb_44x_hwater@ha
414 lwz r5,tlb_44x_hwater@l(r4)
416 1: tlbwe r3,r3,PPC44x_TLB_PAGEID
422 #else /* !(CONFIG_40x || CONFIG_44x) */
423 #if defined(CONFIG_SMP)
429 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
430 rlwinm r0,r0,0,28,26 /* clear DR */
434 lis r9,mmu_hash_lock@h
435 ori r9,r9,mmu_hash_lock@l
447 stw r0,0(r9) /* clear mmu_hash_lock */
451 #else /* CONFIG_SMP */
455 #endif /* CONFIG_SMP */
456 #endif /* ! defined(CONFIG_40x) */
460 * Flush MMU TLB for a particular address
463 #if defined(CONFIG_40x)
467 /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear.
468 * Since 25 is the V bit in the TLB_TAG, loading this value will invalidate
470 tlbwe r3, r3, TLB_TAG
473 #elif defined(CONFIG_44x)
475 mfspr r5,SPRN_PID /* Get PID */
476 rlwimi r4,r5,0,24,31 /* Set TID */
482 /* There are only 64 TLB entries, so r3 < 64,
483 * which means bit 22, is clear. Since 22 is
484 * the V bit in the TLB_PAGEID, loading this
485 * value will invalidate the TLB entry.
487 tlbwe r3, r3, PPC44x_TLB_PAGEID
490 #else /* !(CONFIG_40x || CONFIG_44x) */
491 #if defined(CONFIG_SMP)
497 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
498 rlwinm r0,r0,0,28,26 /* clear DR */
502 lis r9,mmu_hash_lock@h
503 ori r9,r9,mmu_hash_lock@l
515 stw r0,0(r9) /* clear mmu_hash_lock */
519 #else /* CONFIG_SMP */
522 #endif /* CONFIG_SMP */
523 #endif /* ! CONFIG_40x */
527 * Flush instruction cache.
528 * This is a no-op on the 601.
530 _GLOBAL(flush_instruction_cache)
531 #if defined(CONFIG_8xx)
535 #elif defined(CONFIG_4xx)
549 rlwinm r3,r3,16,16,31
551 beqlr /* for 601, do nothing */
552 /* 603/604 processor - use invalidate-all bit in HID0 */
556 #endif /* CONFIG_8xx/4xx */
561 * Write any modified data cache blocks out to memory
562 * and invalidate the corresponding instruction cache blocks.
563 * This is a no-op on the 601.
565 * flush_icache_range(unsigned long start, unsigned long stop)
567 _GLOBAL(flush_icache_range)
569 rlwinm r5,r5,16,16,31
571 beqlr /* for 601, do nothing */
572 li r5,L1_CACHE_LINE_SIZE-1
576 srwi. r4,r4,LG_L1_CACHE_LINE_SIZE
581 addi r3,r3,L1_CACHE_LINE_SIZE
583 sync /* wait for dcbst's to get to ram */
586 addi r6,r6,L1_CACHE_LINE_SIZE
588 sync /* additional sync needed on g4 */
592 * Write any modified data cache blocks out to memory.
593 * Does not invalidate the corresponding cache lines (especially for
594 * any corresponding instruction cache).
596 * clean_dcache_range(unsigned long start, unsigned long stop)
598 _GLOBAL(clean_dcache_range)
599 li r5,L1_CACHE_LINE_SIZE-1
603 srwi. r4,r4,LG_L1_CACHE_LINE_SIZE
608 addi r3,r3,L1_CACHE_LINE_SIZE
610 sync /* wait for dcbst's to get to ram */
614 * Write any modified data cache blocks out to memory and invalidate them.
615 * Does not invalidate the corresponding instruction cache blocks.
617 * flush_dcache_range(unsigned long start, unsigned long stop)
619 _GLOBAL(flush_dcache_range)
620 li r5,L1_CACHE_LINE_SIZE-1
624 srwi. r4,r4,LG_L1_CACHE_LINE_SIZE
629 addi r3,r3,L1_CACHE_LINE_SIZE
631 sync /* wait for dcbst's to get to ram */
635 * Like above, but invalidate the D-cache. This is used by the 8xx
636 * to invalidate the cache so the PPC core doesn't get stale data
637 * from the CPM (no cache snooping here :-).
639 * invalidate_dcache_range(unsigned long start, unsigned long stop)
641 _GLOBAL(invalidate_dcache_range)
642 li r5,L1_CACHE_LINE_SIZE-1
646 srwi. r4,r4,LG_L1_CACHE_LINE_SIZE
651 addi r3,r3,L1_CACHE_LINE_SIZE
653 sync /* wait for dcbi's to get to ram */
656 #ifdef CONFIG_NOT_COHERENT_CACHE
658 * 40x cores have 8K or 16K dcache and 32 byte line size.
659 * 44x has a 32K dcache and 32 byte line size.
660 * 8xx has 1, 2, 4, 8K variants.
661 * For now, cover the worst case of the 44x.
662 * Must be called with external interrupts disabled.
664 #define CACHE_NWAYS 64
665 #define CACHE_NLINES 16
667 _GLOBAL(flush_dcache_all)
668 li r4, (2 * CACHE_NWAYS * CACHE_NLINES)
671 1: lwz r3, 0(r5) /* Load one word from every line */
672 addi r5, r5, L1_CACHE_LINE_SIZE
675 #endif /* CONFIG_NOT_COHERENT_CACHE */
678 * Flush a particular page from the data cache to RAM.
679 * Note: this is necessary because the instruction cache does *not*
680 * snoop from the data cache.
681 * This is a no-op on the 601 which has a unified cache.
683 * void __flush_dcache_icache(void *page)
685 _GLOBAL(__flush_dcache_icache)
687 rlwinm r5,r5,16,16,31
689 beqlr /* for 601, do nothing */
690 rlwinm r3,r3,0,0,19 /* Get page base address */
691 li r4,4096/L1_CACHE_LINE_SIZE /* Number of lines in a page */
694 0: dcbst 0,r3 /* Write line to ram */
695 addi r3,r3,L1_CACHE_LINE_SIZE
700 addi r6,r6,L1_CACHE_LINE_SIZE
707 * Flush a particular page from the data cache to RAM, identified
708 * by its physical address. We turn off the MMU so we can just use
709 * the physical address (this may be a highmem page without a kernel
712 * void __flush_dcache_icache_phys(unsigned long physaddr)
714 _GLOBAL(__flush_dcache_icache_phys)
716 rlwinm r5,r5,16,16,31
718 beqlr /* for 601, do nothing */
720 rlwinm r0,r10,0,28,26 /* clear DR */
723 rlwinm r3,r3,0,0,19 /* Get page base address */
724 li r4,4096/L1_CACHE_LINE_SIZE /* Number of lines in a page */
727 0: dcbst 0,r3 /* Write line to ram */
728 addi r3,r3,L1_CACHE_LINE_SIZE
733 addi r6,r6,L1_CACHE_LINE_SIZE
736 mtmsr r10 /* restore DR */
741 * Clear pages using the dcbz instruction, which doesn't cause any
742 * memory traffic (except to write out any cache lines which get
743 * displaced). This only works on cacheable memory.
745 * void clear_pages(void *page, int order) ;
748 li r0,4096/L1_CACHE_LINE_SIZE
760 addi r3,r3,L1_CACHE_LINE_SIZE
765 * Copy a whole page. We use the dcbz instruction on the destination
766 * to reduce memory traffic (it eliminates the unnecessary reads of
767 * the destination into cache). This requires that the destination
770 #define COPY_16_BYTES \
785 /* don't use prefetch on 8xx */
786 li r0,4096/L1_CACHE_LINE_SIZE
792 #else /* not 8xx, we can prefetch */
795 #if MAX_COPY_PREFETCH > 1
796 li r0,MAX_COPY_PREFETCH
800 addi r11,r11,L1_CACHE_LINE_SIZE
802 #else /* MAX_COPY_PREFETCH == 1 */
804 li r11,L1_CACHE_LINE_SIZE+4
805 #endif /* MAX_COPY_PREFETCH */
806 li r0,4096/L1_CACHE_LINE_SIZE - MAX_COPY_PREFETCH
814 #if L1_CACHE_LINE_SIZE >= 32
816 #if L1_CACHE_LINE_SIZE >= 64
819 #if L1_CACHE_LINE_SIZE >= 128
829 crnot 4*cr0+eq,4*cr0+eq
830 li r0,MAX_COPY_PREFETCH
833 #endif /* CONFIG_8xx */
836 * void atomic_clear_mask(atomic_t mask, atomic_t *addr)
837 * void atomic_set_mask(atomic_t mask, atomic_t *addr);
839 _GLOBAL(atomic_clear_mask)
846 _GLOBAL(atomic_set_mask)
855 * I/O string operations
857 * insb(port, buf, len)
858 * outsb(port, buf, len)
859 * insw(port, buf, len)
860 * outsw(port, buf, len)
861 * insl(port, buf, len)
862 * outsl(port, buf, len)
863 * insw_ns(port, buf, len)
864 * outsw_ns(port, buf, len)
865 * insl_ns(port, buf, len)
866 * outsl_ns(port, buf, len)
868 * The *_ns versions don't do byte-swapping.
936 _GLOBAL(__ide_mm_insw)
948 _GLOBAL(__ide_mm_outsw)
960 _GLOBAL(__ide_mm_insl)
972 _GLOBAL(__ide_mm_outsl)
985 * Extended precision shifts.
987 * Updated to be valid for shift counts from 0 to 63 inclusive.
990 * R3/R4 has 64 bit value
994 * ashrdi3: arithmetic right shift (sign propagation)
995 * lshrdi3: logical right shift
996 * ashldi3: left shift
1000 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
1001 addi r7,r5,32 # could be xori, or addi with -32
1002 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
1003 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
1004 sraw r7,r3,r7 # t2 = MSW >> (count-32)
1005 or r4,r4,r6 # LSW |= t1
1006 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
1007 sraw r3,r3,r5 # MSW = MSW >> count
1008 or r4,r4,r7 # LSW |= t2
1013 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
1014 addi r7,r5,32 # could be xori, or addi with -32
1015 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
1016 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
1017 or r3,r3,r6 # MSW |= t1
1018 slw r4,r4,r5 # LSW = LSW << count
1019 or r3,r3,r7 # MSW |= t2
1024 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
1025 addi r7,r5,32 # could be xori, or addi with -32
1026 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
1027 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
1028 or r4,r4,r6 # LSW |= t1
1029 srw r3,r3,r5 # MSW = MSW >> count
1030 or r4,r4,r7 # LSW |= t2
1040 mr r3,r1 /* Close enough */
1044 * These are used in the alignment trap handler when emulating
1045 * single-precision loads and stores.
1046 * We restore and save the fpscr so the task gets the same result
1047 * and exceptions as if the cpu had performed the load or store.
1050 #if defined(CONFIG_4xx)
1062 lfd 0,-4(r5) /* load up fpscr value */
1066 mffs 0 /* save new fpscr value */
1071 lfd 0,-4(r5) /* load up fpscr value */
1075 mffs 0 /* save new fpscr value */
1081 * Create a kernel thread
1082 * kernel_thread(fn, arg, flags)
1084 _GLOBAL(kernel_thread)
1088 mr r30,r3 /* function */
1089 mr r31,r4 /* argument */
1090 ori r3,r5,CLONE_VM /* flags */
1091 oris r3,r3,CLONE_UNTRACED>>16
1092 li r4,0 /* new sp (unused) */
1095 cmpi 0,r3,0 /* parent or child? */
1096 bne 1f /* return if parent */
1097 li r0,0 /* make top-level stack frame */
1099 mtlr r30 /* fn addr in lr */
1100 mr r3,r31 /* load arg and call fn */
1102 li r0,__NR_exit /* exit if function returns */
1111 * This routine is just here to keep GCC happy - sigh...
1116 #define SYSCALL(name) \
1118 li r0,__NR_##name; \
1122 stw r3,errno@l(r4); \
1128 /* Why isn't this a) automatic, b) written in 'C'? */
1131 _GLOBAL(sys_call_table)
1132 .long sys_restart_syscall /* 0 */
1137 .long sys_open /* 5 */
1142 .long sys_unlink /* 10 */
1147 .long sys_chmod /* 15 */
1149 .long sys_ni_syscall /* old break syscall holder */
1152 .long sys_getpid /* 20 */
1157 .long sys_stime /* 25 */
1162 .long sys_utime /* 30 */
1163 .long sys_ni_syscall /* old stty syscall holder */
1164 .long sys_ni_syscall /* old gtty syscall holder */
1167 .long sys_ni_syscall /* 35 */ /* old ftime syscall holder */
1172 .long sys_rmdir /* 40 */
1176 .long sys_ni_syscall /* old prof syscall holder */
1177 .long sys_brk /* 45 */
1182 .long sys_getegid /* 50 */
1184 .long sys_umount /* recycled never used phys() */
1185 .long sys_ni_syscall /* old lock syscall holder */
1187 .long sys_fcntl /* 55 */
1188 .long sys_ni_syscall /* old mpx syscall holder */
1190 .long sys_ni_syscall /* old ulimit syscall holder */
1192 .long sys_umask /* 60 */
1197 .long sys_getpgrp /* 65 */
1202 .long sys_setreuid /* 70 */
1204 .long ppc_sigsuspend
1205 .long sys_sigpending
1206 .long sys_sethostname
1207 .long sys_setrlimit /* 75 */
1208 .long sys_old_getrlimit
1210 .long sys_gettimeofday
1211 .long sys_settimeofday
1212 .long sys_getgroups /* 80 */
1217 .long sys_readlink /* 85 */
1222 .long sys_mmap /* 90 */
1227 .long sys_fchown /* 95 */
1228 .long sys_getpriority
1229 .long sys_setpriority
1230 .long sys_ni_syscall /* old profil syscall holder */
1232 .long sys_fstatfs /* 100 */
1233 .long sys_ni_syscall
1234 .long sys_socketcall
1237 .long sys_getitimer /* 105 */
1242 .long sys_ni_syscall /* 110 */
1244 .long sys_ni_syscall /* old 'idle' syscall */
1245 .long sys_ni_syscall
1247 .long sys_swapoff /* 115 */
1252 .long ppc_clone /* 120 */
1253 .long sys_setdomainname
1255 .long sys_ni_syscall
1257 .long sys_mprotect /* 125 */
1258 .long sys_sigprocmask
1259 .long sys_ni_syscall /* old sys_create_module */
1260 .long sys_init_module
1261 .long sys_delete_module
1262 .long sys_ni_syscall /* old sys_get_kernel_syms */ /* 130 */
1267 .long sys_sysfs /* 135 */
1268 .long sys_personality
1269 .long sys_ni_syscall /* for afs_syscall */
1272 .long sys_llseek /* 140 */
1277 .long sys_readv /* 145 */
1282 .long sys_mlock /* 150 */
1285 .long sys_munlockall
1286 .long sys_sched_setparam
1287 .long sys_sched_getparam /* 155 */
1288 .long sys_sched_setscheduler
1289 .long sys_sched_getscheduler
1290 .long sys_sched_yield
1291 .long sys_sched_get_priority_max
1292 .long sys_sched_get_priority_min /* 160 */
1293 .long sys_sched_rr_get_interval
1297 .long sys_getresuid /* 165 */
1298 .long sys_ni_syscall /* old sys_query_module */
1300 .long sys_nfsservctl
1302 .long sys_getresgid /* 170 */
1304 .long sys_rt_sigreturn
1305 .long sys_rt_sigaction
1306 .long sys_rt_sigprocmask
1307 .long sys_rt_sigpending /* 175 */
1308 .long sys_rt_sigtimedwait
1309 .long sys_rt_sigqueueinfo
1310 .long ppc_rt_sigsuspend
1312 .long sys_pwrite64 /* 180 */
1317 .long sys_sigaltstack /* 185 */
1319 .long sys_ni_syscall /* streams1 */
1320 .long sys_ni_syscall /* streams2 */
1322 .long sys_getrlimit /* 190 */
1325 .long sys_truncate64
1326 .long sys_ftruncate64
1327 .long sys_stat64 /* 195 */
1330 .long sys_pciconfig_read
1331 .long sys_pciconfig_write
1332 .long sys_pciconfig_iobase /* 200 */
1333 .long sys_ni_syscall /* 201 - reserved - MacOnLinux - new */
1334 .long sys_getdents64
1335 .long sys_pivot_root
1337 .long sys_madvise /* 205 */
1342 .long sys_lsetxattr /* 210 */
1347 .long sys_listxattr /* 215 */
1348 .long sys_llistxattr
1349 .long sys_flistxattr
1350 .long sys_removexattr
1351 .long sys_lremovexattr
1352 .long sys_fremovexattr /* 220 */
1354 .long sys_sched_setaffinity
1355 .long sys_sched_getaffinity
1356 .long sys_ni_syscall
1357 .long sys_ni_syscall /* 225 - reserved for Tux */
1358 .long sys_sendfile64
1360 .long sys_io_destroy
1361 .long sys_io_getevents
1362 .long sys_io_submit /* 230 */
1364 .long sys_set_tid_address
1366 .long sys_exit_group
1367 .long sys_lookup_dcookie /* 235 */
1368 .long sys_epoll_create
1370 .long sys_epoll_wait
1371 .long sys_remap_file_pages
1372 .long sys_timer_create /* 240 */
1373 .long sys_timer_settime
1374 .long sys_timer_gettime
1375 .long sys_timer_getoverrun
1376 .long sys_timer_delete
1377 .long sys_clock_settime /* 245 */
1378 .long sys_clock_gettime
1379 .long sys_clock_getres
1380 .long sys_clock_nanosleep
1381 .long ppc_swapcontext
1382 .long sys_tgkill /* 250 */
1386 .long ppc_fadvise64_64
1387 .long sys_ni_syscall /* 255 - rtas (used on ppc64) */
1388 .long sys_ni_syscall /* 256 reserved for sys_debug_setcontext */
1390 .long sys_ni_syscall /* 258 reserved for new sys_remap_file_pages */
1391 .long sys_ni_syscall /* 259 reserved for new sys_mbind */
1392 .long sys_ni_syscall /* 260 reserved for new sys_get_mempolicy */
1393 .long sys_ni_syscall /* 261 reserved for new sys_set_mempolicy */
1396 .long sys_mq_timedsend
1397 .long sys_mq_timedreceive /* 265 */
1399 .long sys_mq_getsetattr
1400 .long sys_ni_syscall /* 268 reserved for sys_kexec_load */