2 * Common pmac/prep/chrp pci routines. -- Cort
5 #include <linux/config.h>
6 #include <linux/kernel.h>
8 #include <linux/delay.h>
9 #include <linux/string.h>
10 #include <linux/init.h>
11 #include <linux/capability.h>
12 #include <linux/sched.h>
13 #include <linux/errno.h>
14 #include <linux/bootmem.h>
16 #include <asm/processor.h>
19 #include <asm/sections.h>
20 #include <asm/pci-bridge.h>
21 #include <asm/byteorder.h>
23 #include <asm/uaccess.h>
28 #define DBG(x...) printk(x)
33 unsigned long isa_io_base = 0;
34 unsigned long isa_mem_base = 0;
35 unsigned long pci_dram_offset = 0;
37 void pcibios_make_OF_bus_map(void);
39 static int pci_relocate_bridge_resource(struct pci_bus *bus, int i);
40 static int probe_resource(struct pci_bus *parent, struct resource *pr,
41 struct resource *res, struct resource **conflict);
42 static void update_bridge_base(struct pci_bus *bus, int i);
43 static void pcibios_fixup_resources(struct pci_dev* dev);
44 static void fixup_broken_pcnet32(struct pci_dev* dev);
45 static int reparent_resources(struct resource *parent, struct resource *res);
46 static void fixup_rev1_53c810(struct pci_dev* dev);
47 static void fixup_cpc710_pci64(struct pci_dev* dev);
48 #ifdef CONFIG_PPC_PMAC
49 extern void pmac_pci_fixup_cardbus(struct pci_dev* dev);
50 extern void pmac_pci_fixup_pciata(struct pci_dev* dev);
51 extern void pmac_pci_fixup_k2_sata(struct pci_dev* dev);
54 static u8* pci_to_OF_bus_map;
57 /* By default, we don't re-assign bus numbers. We do this only on
60 int pci_assign_all_busses;
62 struct pci_controller* hose_head;
63 struct pci_controller** hose_tail = &hose_head;
65 static int pci_bus_count;
67 struct pci_fixup pcibios_fixups[] = {
68 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32 },
69 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810 },
70 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64},
71 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources },
72 #ifdef CONFIG_PPC_PMAC
73 /* We should add per-machine fixup support in xxx_setup.c or xxx_pci.c */
74 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus },
75 { PCI_FIXUP_FINAL, PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata },
76 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SERVERWORKS, 0x0240, pmac_pci_fixup_k2_sata },
77 #endif /* CONFIG_PPC_PMAC */
82 fixup_rev1_53c810(struct pci_dev* dev)
84 /* rev 1 ncr53c810 chips don't set the class at all which means
85 * they don't get their resources remapped. Fix that here.
88 if ((dev->class == PCI_CLASS_NOT_DEFINED)) {
89 printk("NCR 53c810 rev 1 detected, setting PCI class.\n");
90 dev->class = PCI_CLASS_STORAGE_SCSI;
95 fixup_broken_pcnet32(struct pci_dev* dev)
97 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
98 dev->vendor = PCI_VENDOR_ID_AMD;
99 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
100 pci_name_device(dev);
105 fixup_cpc710_pci64(struct pci_dev* dev)
107 /* Hide the PCI64 BARs from the kernel as their content doesn't
108 * fit well in the resource management
110 dev->resource[0].start = dev->resource[0].end = 0;
111 dev->resource[0].flags = 0;
112 dev->resource[1].start = dev->resource[1].end = 0;
113 dev->resource[1].flags = 0;
117 pcibios_fixup_resources(struct pci_dev *dev)
119 struct pci_controller* hose = (struct pci_controller *)dev->sysdata;
121 unsigned long offset;
124 printk(KERN_ERR "No hose for PCI dev %s!\n", pci_name(dev));
127 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
128 struct resource *res = dev->resource + i;
131 if (res->end == 0xffffffff) {
132 DBG("PCI:%s Resource %d [%08lx-%08lx] is unassigned\n",
133 pci_name(dev), i, res->start, res->end);
134 res->end -= res->start;
136 res->flags |= IORESOURCE_UNSET;
140 if (res->flags & IORESOURCE_MEM) {
141 offset = hose->pci_mem_offset;
142 } else if (res->flags & IORESOURCE_IO) {
143 offset = (unsigned long) hose->io_base_virt
147 res->start += offset;
150 printk("Fixup res %d (%lx) of dev %s: %lx -> %lx\n",
151 i, res->flags, pci_name(dev),
152 res->start - offset, res->start);
157 /* Call machine specific resource fixup */
158 if (ppc_md.pcibios_fixup_resources)
159 ppc_md.pcibios_fixup_resources(dev);
163 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
164 struct resource *res)
166 unsigned long offset = 0;
167 struct pci_controller *hose = dev->sysdata;
169 if (hose && res->flags & IORESOURCE_IO)
170 offset = (unsigned long)hose->io_base_virt - isa_io_base;
171 else if (hose && res->flags & IORESOURCE_MEM)
172 offset = hose->pci_mem_offset;
173 region->start = res->start - offset;
174 region->end = res->end - offset;
178 * We need to avoid collisions with `mirrored' VGA ports
179 * and other strange ISA hardware, so we always want the
180 * addresses to be allocated in the 0x000-0x0ff region
183 * Why? Because some silly external IO cards only decode
184 * the low 10 bits of the IO address. The 0x00-0xff region
185 * is reserved for motherboard devices that decode all 16
186 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
187 * but we want to try to avoid allocating at 0x2900-0x2bff
188 * which might have be mirrored at 0x0100-0x03ff..
191 pcibios_align_resource(void *data, struct resource *res, unsigned long size,
194 struct pci_dev *dev = data;
196 if (res->flags & IORESOURCE_IO) {
197 unsigned long start = res->start;
200 printk(KERN_ERR "PCI: I/O Region %s/%d too large"
201 " (%ld bytes)\n", pci_name(dev),
202 dev->resource - res, size);
206 start = (start + 0x3ff) & ~0x3ff;
214 * Handle resources of PCI devices. If the world were perfect, we could
215 * just allocate all the resource regions and do nothing more. It isn't.
216 * On the other hand, we cannot just re-allocate all devices, as it would
217 * require us to know lots of host bridge internals. So we attempt to
218 * keep as much of the original configuration as possible, but tweak it
219 * when it's found to be wrong.
221 * Known BIOS problems we have to work around:
222 * - I/O or memory regions not configured
223 * - regions configured, but not enabled in the command register
224 * - bogus I/O addresses above 64K used
225 * - expansion ROMs left enabled (this may sound harmless, but given
226 * the fact the PCI specs explicitly allow address decoders to be
227 * shared between expansion ROMs and other resource regions, it's
228 * at least dangerous)
231 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
232 * This gives us fixed barriers on where we can allocate.
233 * (2) Allocate resources for all enabled devices. If there is
234 * a collision, just mark the resource as unallocated. Also
235 * disable expansion ROMs during this step.
236 * (3) Try to allocate resources for disabled devices. If the
237 * resources were assigned correctly, everything goes well,
238 * if they weren't, they won't disturb allocation of other
240 * (4) Assign new addresses to resources which were either
241 * not configured at all or misconfigured. If explicitly
242 * requested by the user, configure expansion ROM address
247 pcibios_allocate_bus_resources(struct list_head *bus_list)
249 struct list_head *ln;
252 struct resource *res, *pr;
254 /* Depth-First Search on bus tree */
255 for (ln = bus_list->next; ln != bus_list; ln=ln->next) {
257 for (i = 0; i < 4; ++i) {
258 if ((res = bus->resource[i]) == NULL || !res->flags
259 || res->start > res->end)
261 if (bus->parent == NULL)
262 pr = (res->flags & IORESOURCE_IO)?
263 &ioport_resource: &iomem_resource;
265 pr = pci_find_parent_resource(bus->self, res);
267 /* this happens when the generic PCI
268 * code (wrongly) decides that this
269 * bridge is transparent -- paulus
275 DBG("PCI: bridge rsrc %lx..%lx (%lx), parent %p\n",
276 res->start, res->end, res->flags, pr);
278 if (request_resource(pr, res) == 0)
281 * Must be a conflict with an existing entry.
282 * Move that entry (or entries) under the
283 * bridge resource and try again.
285 if (reparent_resources(pr, res) == 0)
288 printk(KERN_ERR "PCI: Cannot allocate resource region "
289 "%d of PCI bridge %d\n", i, bus->number);
290 if (pci_relocate_bridge_resource(bus, i))
291 bus->resource[i] = NULL;
293 pcibios_allocate_bus_resources(&bus->children);
298 * Reparent resource children of pr that conflict with res
299 * under res, and make res replace those children.
302 reparent_resources(struct resource *parent, struct resource *res)
304 struct resource *p, **pp;
305 struct resource **firstpp = NULL;
307 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
308 if (p->end < res->start)
310 if (res->end < p->start)
312 if (p->start < res->start || p->end > res->end)
313 return -1; /* not completely contained */
318 return -1; /* didn't find any conflicting entries? */
319 res->parent = parent;
320 res->child = *firstpp;
324 for (p = res->child; p != NULL; p = p->sibling) {
326 DBG(KERN_INFO "PCI: reparented %s [%lx..%lx] under %s\n",
327 p->name, p->start, p->end, res->name);
333 * A bridge has been allocated a range which is outside the range
334 * of its parent bridge, so it needs to be moved.
337 pci_relocate_bridge_resource(struct pci_bus *bus, int i)
339 struct resource *res, *pr, *conflict;
340 unsigned long try, size;
342 struct pci_bus *parent = bus->parent;
344 if (parent == NULL) {
345 /* shouldn't ever happen */
346 printk(KERN_ERR "PCI: can't move host bridge resource\n");
349 res = bus->resource[i];
353 for (j = 0; j < 4; j++) {
354 struct resource *r = parent->resource[j];
357 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
359 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) {
363 if (res->flags & IORESOURCE_PREFETCH)
368 size = res->end - res->start;
369 if (pr->start > pr->end || size > pr->end - pr->start)
373 res->start = try - size;
375 if (probe_resource(bus->parent, pr, res, &conflict) == 0)
377 if (conflict->start <= pr->start + size)
379 try = conflict->start - 1;
381 if (request_resource(pr, res)) {
382 DBG(KERN_ERR "PCI: huh? couldn't move to %lx..%lx\n",
383 res->start, res->end);
384 return -1; /* "can't happen" */
386 update_bridge_base(bus, i);
387 printk(KERN_INFO "PCI: bridge %d resource %d moved to %lx..%lx\n",
388 bus->number, i, res->start, res->end);
393 probe_resource(struct pci_bus *parent, struct resource *pr,
394 struct resource *res, struct resource **conflict)
399 struct list_head *ln;
402 for (r = pr->child; r != NULL; r = r->sibling) {
403 if (r->end >= res->start && res->end >= r->start) {
408 for (ln = parent->children.next; ln != &parent->children;
411 for (i = 0; i < 4; ++i) {
412 if ((r = bus->resource[i]) == NULL)
414 if (!r->flags || r->start > r->end || r == res)
416 if (pci_find_parent_resource(bus->self, r) != pr)
418 if (r->end >= res->start && res->end >= r->start) {
424 for (ln = parent->devices.next; ln != &parent->devices; ln=ln->next) {
426 for (i = 0; i < 6; ++i) {
427 r = &dev->resource[i];
428 if (!r->flags || (r->flags & IORESOURCE_UNSET))
430 if (pci_find_parent_resource(bus->self, r) != pr)
432 if (r->end >= res->start && res->end >= r->start) {
442 update_bridge_base(struct pci_bus *bus, int i)
444 struct resource *res = bus->resource[i];
445 u8 io_base_lo, io_limit_lo;
446 u16 mem_base, mem_limit;
448 unsigned long start, end, off;
449 struct pci_dev *dev = bus->self;
450 struct pci_controller *hose = dev->sysdata;
453 printk("update_bridge_base: no hose?\n");
456 pci_read_config_word(dev, PCI_COMMAND, &cmd);
457 pci_write_config_word(dev, PCI_COMMAND,
458 cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
459 if (res->flags & IORESOURCE_IO) {
460 off = (unsigned long) hose->io_base_virt - isa_io_base;
461 start = res->start - off;
462 end = res->end - off;
463 io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK;
464 io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK;
466 pci_write_config_word(dev, PCI_IO_BASE_UPPER16,
468 pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
470 io_base_lo |= PCI_IO_RANGE_TYPE_32;
472 io_base_lo |= PCI_IO_RANGE_TYPE_16;
473 pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo);
474 pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo);
476 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
478 off = hose->pci_mem_offset;
479 mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK;
480 mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK;
481 pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base);
482 pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit);
484 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
485 == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) {
486 off = hose->pci_mem_offset;
487 mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK;
488 mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK;
489 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base);
490 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit);
493 DBG(KERN_ERR "PCI: ugh, bridge %s res %d has flags=%lx\n",
494 pci_name(dev), i, res->flags);
496 pci_write_config_word(dev, PCI_COMMAND, cmd);
499 static inline void alloc_resource(struct pci_dev *dev, int idx)
501 struct resource *pr, *r = &dev->resource[idx];
503 DBG("PCI:%s: Resource %d: %08lx-%08lx (f=%lx)\n",
504 pci_name(dev), idx, r->start, r->end, r->flags);
505 pr = pci_find_parent_resource(dev, r);
506 if (!pr || request_resource(pr, r) < 0) {
507 printk(KERN_ERR "PCI: Cannot allocate resource region %d"
508 " of device %s\n", idx, pci_name(dev));
510 DBG("PCI: parent is %p: %08lx-%08lx (f=%lx)\n",
511 pr, pr->start, pr->end, pr->flags);
512 /* We'll assign a new address later */
513 r->flags |= IORESOURCE_UNSET;
520 pcibios_allocate_resources(int pass)
522 struct pci_dev *dev = NULL;
527 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
528 pci_read_config_word(dev, PCI_COMMAND, &command);
529 for (idx = 0; idx < 6; idx++) {
530 r = &dev->resource[idx];
531 if (r->parent) /* Already allocated */
533 if (!r->flags || (r->flags & IORESOURCE_UNSET))
534 continue; /* Not assigned at all */
535 if (r->flags & IORESOURCE_IO)
536 disabled = !(command & PCI_COMMAND_IO);
538 disabled = !(command & PCI_COMMAND_MEMORY);
539 if (pass == disabled)
540 alloc_resource(dev, idx);
544 r = &dev->resource[PCI_ROM_RESOURCE];
545 if (r->flags & PCI_ROM_ADDRESS_ENABLE) {
546 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
548 DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
549 r->flags &= ~PCI_ROM_ADDRESS_ENABLE;
550 pci_read_config_dword(dev, dev->rom_base_reg, ®);
551 pci_write_config_dword(dev, dev->rom_base_reg,
552 reg & ~PCI_ROM_ADDRESS_ENABLE);
558 pcibios_assign_resources(void)
560 struct pci_dev *dev = NULL;
564 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
565 int class = dev->class >> 8;
567 /* Don't touch classless devices and host bridges */
568 if (!class || class == PCI_CLASS_BRIDGE_HOST)
571 for (idx = 0; idx < 6; idx++) {
572 r = &dev->resource[idx];
575 * We shall assign a new address to this resource,
576 * either because the BIOS (sic) forgot to do so
577 * or because we have decided the old address was
578 * unusable for some reason.
580 if ((r->flags & IORESOURCE_UNSET) && r->end &&
581 (!ppc_md.pcibios_enable_device_hook ||
582 !ppc_md.pcibios_enable_device_hook(dev, 1))) {
583 r->flags &= ~IORESOURCE_UNSET;
584 pci_assign_resource(dev, idx);
588 #if 0 /* don't assign ROMs */
589 r = &dev->resource[PCI_ROM_RESOURCE];
593 pci_assign_resource(dev, PCI_ROM_RESOURCE);
600 pcibios_enable_resources(struct pci_dev *dev, int mask)
606 pci_read_config_word(dev, PCI_COMMAND, &cmd);
608 for (idx=0; idx<6; idx++) {
609 /* Only set up the requested stuff */
610 if (!(mask & (1<<idx)))
613 r = &dev->resource[idx];
614 if (r->flags & IORESOURCE_UNSET) {
615 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
618 if (r->flags & IORESOURCE_IO)
619 cmd |= PCI_COMMAND_IO;
620 if (r->flags & IORESOURCE_MEM)
621 cmd |= PCI_COMMAND_MEMORY;
623 if (dev->resource[PCI_ROM_RESOURCE].start)
624 cmd |= PCI_COMMAND_MEMORY;
625 if (cmd != old_cmd) {
626 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
627 pci_write_config_word(dev, PCI_COMMAND, cmd);
632 static int next_controller_index;
634 struct pci_controller * __init
635 pcibios_alloc_controller(void)
637 struct pci_controller *hose;
639 hose = (struct pci_controller *)alloc_bootmem(sizeof(*hose));
640 memset(hose, 0, sizeof(struct pci_controller));
643 hose_tail = &hose->next;
645 hose->index = next_controller_index++;
652 * Functions below are used on OpenFirmware machines.
654 static void __openfirmware
655 make_one_node_map(struct device_node* node, u8 pci_bus)
660 if (pci_bus >= pci_bus_count)
662 bus_range = (int *) get_property(node, "bus-range", &len);
663 if (bus_range == NULL || len < 2 * sizeof(int)) {
664 printk(KERN_WARNING "Can't get bus-range for %s, "
665 "assuming it starts at 0\n", node->full_name);
666 pci_to_OF_bus_map[pci_bus] = 0;
668 pci_to_OF_bus_map[pci_bus] = bus_range[0];
670 for (node=node->child; node != 0;node = node->sibling) {
672 unsigned int *class_code, *reg;
674 class_code = (unsigned int *) get_property(node, "class-code", 0);
675 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
676 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
678 reg = (unsigned int *)get_property(node, "reg", 0);
681 dev = pci_find_slot(pci_bus, ((reg[0] >> 8) & 0xff));
682 if (!dev || !dev->subordinate)
684 make_one_node_map(node, dev->subordinate->number);
689 pcibios_make_OF_bus_map(void)
692 struct pci_controller* hose;
695 pci_to_OF_bus_map = (u8*)kmalloc(pci_bus_count, GFP_KERNEL);
696 if (!pci_to_OF_bus_map) {
697 printk(KERN_ERR "Can't allocate OF bus map !\n");
701 /* We fill the bus map with invalid values, that helps
704 for (i=0; i<pci_bus_count; i++)
705 pci_to_OF_bus_map[i] = 0xff;
707 /* For each hose, we begin searching bridges */
708 for(hose=hose_head; hose; hose=hose->next) {
709 struct device_node* node;
710 node = (struct device_node *)hose->arch_data;
713 make_one_node_map(node, hose->first_busno);
715 of_prop_map = get_property(find_path_device("/"), "pci-OF-bus-map", 0);
717 memcpy(of_prop_map, pci_to_OF_bus_map, pci_bus_count);
719 printk("PCI->OF bus map:\n");
720 for (i=0; i<pci_bus_count; i++) {
721 if (pci_to_OF_bus_map[i] == 0xff)
723 printk("%d -> %d\n", i, pci_to_OF_bus_map[i]);
728 typedef int (*pci_OF_scan_iterator)(struct device_node* node, void* data);
730 static struct device_node* __openfirmware
731 scan_OF_pci_childs(struct device_node* node, pci_OF_scan_iterator filter, void* data)
733 struct device_node* sub_node;
735 for (; node != 0;node = node->sibling) {
736 unsigned int *class_code;
738 if (filter(node, data))
741 /* For PCI<->PCI bridges or CardBus bridges, we go down
742 * Note: some OFs create a parent node "multifunc-device" as
743 * a fake root for all functions of a multi-function device,
744 * we go down them as well.
746 class_code = (unsigned int *) get_property(node, "class-code", 0);
747 if ((!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
748 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) &&
749 strcmp(node->name, "multifunc-device"))
751 sub_node = scan_OF_pci_childs(node->child, filter, data);
759 scan_OF_pci_childs_iterator(struct device_node* node, void* data)
762 u8* fdata = (u8*)data;
764 reg = (unsigned int *) get_property(node, "reg", 0);
765 if (reg && ((reg[0] >> 8) & 0xff) == fdata[1]
766 && ((reg[0] >> 16) & 0xff) == fdata[0])
771 static struct device_node* __openfirmware
772 scan_OF_childs_for_device(struct device_node* node, u8 bus, u8 dev_fn)
774 u8 filter_data[2] = {bus, dev_fn};
776 return scan_OF_pci_childs(node, scan_OF_pci_childs_iterator, filter_data);
780 * Scans the OF tree for a device node matching a PCI device
783 pci_busdev_to_OF_node(struct pci_bus *bus, int devfn)
785 struct pci_controller *hose;
786 struct device_node *node;
792 /* Lookup the hose */
794 hose = pci_bus_to_hose(busnr);
798 /* Check it has an OF node associated */
799 node = (struct device_node *) hose->arch_data;
803 /* Fixup bus number according to what OF think it is. */
804 #ifdef CONFIG_PPC_PMAC
805 /* The G5 need a special case here. Basically, we don't remap all
806 * busses on it so we don't create the pci-OF-map. However, we do
807 * remap the AGP bus and so have to deal with it. A future better
808 * fix has to be done by making the remapping per-host and always
809 * filling the pci_to_OF map. --BenH
811 if (_machine == _MACH_Pmac && busnr >= 0xf0)
815 if (pci_to_OF_bus_map)
816 busnr = pci_to_OF_bus_map[busnr];
820 /* Now, lookup childs of the hose */
821 return scan_OF_childs_for_device(node->child, busnr, devfn);
825 pci_device_to_OF_node(struct pci_dev *dev)
827 return pci_busdev_to_OF_node(dev->bus, dev->devfn);
830 /* This routine is meant to be used early during boot, when the
831 * PCI bus numbers have not yet been assigned, and you need to
832 * issue PCI config cycles to an OF device.
833 * It could also be used to "fix" RTAS config cycles if you want
834 * to set pci_assign_all_busses to 1 and still use RTAS for PCI
837 struct pci_controller*
838 pci_find_hose_for_OF_device(struct device_node* node)
843 struct pci_controller* hose;
844 for (hose=hose_head;hose;hose=hose->next)
845 if (hose->arch_data == node)
852 static int __openfirmware
853 find_OF_pci_device_filter(struct device_node* node, void* data)
855 return ((void *)node == data);
859 * Returns the PCI device matching a given OF node
862 pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn)
865 struct pci_controller* hose;
866 struct pci_dev* dev = NULL;
870 /* Make sure it's really a PCI device */
871 hose = pci_find_hose_for_OF_device(node);
872 if (!hose || !hose->arch_data)
874 if (!scan_OF_pci_childs(((struct device_node*)hose->arch_data)->child,
875 find_OF_pci_device_filter, (void *)node))
877 reg = (unsigned int *) get_property(node, "reg", 0);
880 *bus = (reg[0] >> 16) & 0xff;
881 *devfn = ((reg[0] >> 8) & 0xff);
883 /* Ok, here we need some tweak. If we have already renumbered
884 * all busses, we can't rely on the OF bus number any more.
885 * the pci_to_OF_bus_map is not enough as several PCI busses
886 * may match the same OF bus number.
888 if (!pci_to_OF_bus_map)
890 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
891 if (pci_to_OF_bus_map[dev->bus->number] != *bus)
893 if (dev->devfn != *devfn)
895 *bus = dev->bus->number;
902 pci_process_bridge_OF_ranges(struct pci_controller *hose,
903 struct device_node *dev, int primary)
905 static unsigned int static_lc_ranges[256] __initdata;
906 unsigned int *dt_ranges, *lc_ranges, *ranges, *prev;
908 int rlen = 0, orig_rlen;
910 struct resource *res;
911 int np, na = prom_n_addr_cells(dev);
914 /* First we try to merge ranges to fix a problem with some pmacs
915 * that can have more than 3 ranges, fortunately using contiguous
918 dt_ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
921 /* Sanity check, though hopefully that never happens */
922 if (rlen > sizeof(static_lc_ranges)) {
923 printk(KERN_WARNING "OF ranges property too large !\n");
924 rlen = sizeof(static_lc_ranges);
926 lc_ranges = static_lc_ranges;
927 memcpy(lc_ranges, dt_ranges, rlen);
930 /* Let's work on a copy of the "ranges" property instead of damaging
931 * the device-tree image in memory
935 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
937 if (prev[0] == ranges[0] && prev[1] == ranges[1] &&
938 (prev[2] + prev[na+4]) == ranges[2] &&
939 (prev[na+2] + prev[na+4]) == ranges[na+2]) {
940 prev[na+4] += ranges[na+4];
951 * The ranges property is laid out as an array of elements,
952 * each of which comprises:
953 * cells 0 - 2: a PCI address
954 * cells 3 or 3+4: a CPU physical address
955 * (size depending on dev->n_addr_cells)
956 * cells 4+5 or 5+6: the size of the range
960 while (ranges && (rlen -= np * sizeof(unsigned int)) >= 0) {
963 switch (ranges[0] >> 24) {
964 case 1: /* I/O space */
967 hose->io_base_phys = ranges[na+2];
968 /* limit I/O space to 16MB */
969 if (size > 0x01000000)
971 hose->io_base_virt = ioremap(ranges[na+2], size);
973 isa_io_base = (unsigned long) hose->io_base_virt;
974 res = &hose->io_resource;
975 res->flags = IORESOURCE_IO;
976 res->start = ranges[2];
978 case 2: /* memory space */
980 if (ranges[1] == 0 && ranges[2] == 0
981 && ranges[na+4] <= (16 << 20)) {
982 /* 1st 16MB, i.e. ISA memory area */
984 isa_mem_base = ranges[na+2];
987 while (memno < 3 && hose->mem_resources[memno].flags)
990 hose->pci_mem_offset = ranges[na+2] - ranges[2];
992 res = &hose->mem_resources[memno];
993 res->flags = IORESOURCE_MEM;
994 res->start = ranges[na+2];
999 res->name = dev->full_name;
1000 res->end = res->start + size - 1;
1002 res->sibling = NULL;
1009 /* We create the "pci-OF-bus-map" property now so it appears in the
1013 pci_create_OF_bus_map(void)
1015 struct property* of_prop;
1017 of_prop = (struct property*) alloc_bootmem(sizeof(struct property) + 256);
1018 if (of_prop && find_path_device("/")) {
1019 memset(of_prop, -1, sizeof(struct property) + 256);
1020 of_prop->name = "pci-OF-bus-map";
1021 of_prop->length = 256;
1022 of_prop->value = (unsigned char *)&of_prop[1];
1023 prom_add_property(find_path_device("/"), of_prop);
1027 static ssize_t pci_show_devspec(struct device *dev, char *buf)
1029 struct pci_dev *pdev;
1030 struct device_node *np;
1032 pdev = to_pci_dev (dev);
1033 np = pci_device_to_OF_node(pdev);
1034 if (np == NULL || np->full_name == NULL)
1036 return sprintf(buf, "%s", np->full_name);
1038 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
1040 #endif /* CONFIG_PPC_OF */
1042 /* Add sysfs properties */
1043 void pcibios_add_platform_entries(struct pci_dev *pdev)
1045 #ifdef CONFIG_PPC_OF
1046 device_create_file(&pdev->dev, &dev_attr_devspec);
1047 #endif /* CONFIG_PPC_OF */
1051 #ifdef CONFIG_PPC_PMAC
1053 * This set of routines checks for PCI<->PCI bridges that have closed
1054 * IO resources and have child devices. It tries to re-open an IO
1057 * This is a _temporary_ fix to workaround a problem with Apple's OF
1058 * closing IO windows on P2P bridges when the OF drivers of cards
1059 * below this bridge don't claim any IO range (typically ATI or
1062 * A more complete fix would be to use drivers/pci/setup-bus.c, which
1063 * involves a working pcibios_fixup_pbus_ranges(), some more care about
1064 * ordering when creating the host bus resources, and maybe a few more
1068 /* Initialize bridges with base/limit values we have collected */
1070 do_update_p2p_io_resource(struct pci_bus *bus, int enable_vga)
1072 struct pci_dev *bridge = bus->self;
1073 struct pci_controller* hose = (struct pci_controller *)bridge->sysdata;
1076 struct resource res;
1078 if (bus->resource[0] == NULL)
1080 res = *(bus->resource[0]);
1082 DBG("Remapping Bus %d, bridge: %s\n", bus->number, bridge->slot_name);
1083 res.start -= ((unsigned long) hose->io_base_virt - isa_io_base);
1084 res.end -= ((unsigned long) hose->io_base_virt - isa_io_base);
1085 DBG(" IO window: %08lx-%08lx\n", res.start, res.end);
1087 /* Set up the top and bottom of the PCI I/O segment for this bus. */
1088 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
1090 l |= (res.start >> 8) & 0x00f0;
1091 l |= res.end & 0xf000;
1092 pci_write_config_dword(bridge, PCI_IO_BASE, l);
1094 if ((l & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
1095 l = (res.start >> 16) | (res.end & 0xffff0000);
1096 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, l);
1099 pci_read_config_word(bridge, PCI_COMMAND, &w);
1100 w |= PCI_COMMAND_IO;
1101 pci_write_config_word(bridge, PCI_COMMAND, w);
1103 #if 0 /* Enabling this causes XFree 4.2.0 to hang during PCI probe */
1105 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, &w);
1106 w |= PCI_BRIDGE_CTL_VGA;
1107 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, w);
1112 /* This function is pretty basic and actually quite broken for the
1113 * general case, it's enough for us right now though. It's supposed
1114 * to tell us if we need to open an IO range at all or not and what
1118 check_for_io_childs(struct pci_bus *bus, struct resource* res, int *found_vga)
1120 struct list_head *ln;
1124 #define push_end(res, size) do { unsigned long __sz = (size) ; \
1125 res->end = ((res->end + __sz) / (__sz + 1)) * (__sz + 1) + __sz; \
1128 for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) {
1129 struct pci_dev *dev = pci_dev_b(ln);
1130 u16 class = dev->class >> 8;
1132 if (class == PCI_CLASS_DISPLAY_VGA ||
1133 class == PCI_CLASS_NOT_DEFINED_VGA)
1135 if (class >> 8 == PCI_BASE_CLASS_BRIDGE && dev->subordinate)
1136 rc |= check_for_io_childs(dev->subordinate, res, found_vga);
1137 if (class == PCI_CLASS_BRIDGE_CARDBUS)
1138 push_end(res, 0xfff);
1140 for (i=0; i<PCI_NUM_RESOURCES; i++) {
1142 unsigned long r_size;
1144 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI
1145 && i >= PCI_BRIDGE_RESOURCES)
1147 r = &dev->resource[i];
1148 r_size = r->end - r->start;
1151 if (r->flags & IORESOURCE_IO && (r_size) != 0) {
1153 push_end(res, r_size);
1161 /* Here we scan all P2P bridges of a given level that have a closed
1162 * IO window. Note that the test for the presence of a VGA card should
1163 * be improved to take into account already configured P2P bridges,
1164 * currently, we don't see them and might end up configuring 2 bridges
1165 * with VGA pass through enabled
1168 do_fixup_p2p_level(struct pci_bus *bus)
1170 struct list_head *ln;
1174 for (parent_io=0; parent_io<4; parent_io++)
1175 if (bus->resource[parent_io]
1176 && bus->resource[parent_io]->flags & IORESOURCE_IO)
1181 for (ln=bus->children.next; ln != &bus->children; ln=ln->next) {
1182 struct pci_bus *b = pci_bus_b(ln);
1183 struct pci_dev *d = b->self;
1184 struct pci_controller* hose = (struct pci_controller *)d->sysdata;
1185 struct resource *res = b->resource[0];
1186 struct resource tmp_res;
1190 memset(&tmp_res, 0, sizeof(tmp_res));
1191 tmp_res.start = bus->resource[parent_io]->start;
1193 /* We don't let low addresses go through that closed P2P bridge, well,
1194 * that may not be necessary but I feel safer that way
1196 if (tmp_res.start == 0)
1197 tmp_res.start = 0x1000;
1199 if (!list_empty(&b->devices) && res && res->flags == 0 &&
1200 res != bus->resource[parent_io] &&
1201 (d->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
1202 check_for_io_childs(b, &tmp_res, &found_vga)) {
1205 printk(KERN_INFO "Fixing up IO bus %s\n", b->name);
1209 printk(KERN_WARNING "Skipping VGA, already active"
1210 " on bus segment\n");
1215 pci_read_config_byte(d, PCI_IO_BASE, &io_base_lo);
1217 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32)
1218 max = ((unsigned long) hose->io_base_virt
1219 - isa_io_base) + 0xffffffff;
1221 max = ((unsigned long) hose->io_base_virt
1222 - isa_io_base) + 0xffff;
1225 res->flags = IORESOURCE_IO;
1226 res->name = b->name;
1228 /* Find a resource in the parent where we can allocate */
1229 for (i = 0 ; i < 4; i++) {
1230 struct resource *r = bus->resource[i];
1233 if ((r->flags & IORESOURCE_IO) == 0)
1235 DBG("Trying to allocate from %08lx, size %08lx from parent"
1236 " res %d: %08lx -> %08lx\n",
1237 res->start, res->end, i, r->start, r->end);
1239 if (allocate_resource(r, res, res->end + 1, res->start, max,
1240 res->end + 1, NULL, NULL) < 0) {
1244 do_update_p2p_io_resource(b, found_vga);
1248 do_fixup_p2p_level(b);
1253 pcibios_fixup_p2p_bridges(void)
1255 struct list_head *ln;
1257 for(ln=pci_root_buses.next; ln != &pci_root_buses; ln=ln->next) {
1258 struct pci_bus *b = pci_bus_b(ln);
1259 do_fixup_p2p_level(b);
1263 #endif /* CONFIG_PPC_PMAC */
1268 struct pci_controller *hose;
1269 struct pci_bus *bus;
1272 printk(KERN_INFO "PCI: Probing PCI hardware\n");
1274 /* Scan all of the recorded PCI controllers. */
1275 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
1276 if (pci_assign_all_busses)
1277 hose->first_busno = next_busno;
1278 hose->last_busno = 0xff;
1279 bus = pci_scan_bus(hose->first_busno, hose->ops, hose);
1280 hose->last_busno = bus->subordinate;
1281 if (pci_assign_all_busses || next_busno <= hose->last_busno)
1282 next_busno = hose->last_busno+1;
1284 pci_bus_count = next_busno;
1286 /* OpenFirmware based machines need a map of OF bus
1287 * numbers vs. kernel bus numbers since we may have to
1290 if (pci_assign_all_busses && have_of)
1291 pcibios_make_OF_bus_map();
1293 /* Do machine dependent PCI interrupt routing */
1294 if (ppc_md.pci_swizzle && ppc_md.pci_map_irq)
1295 pci_fixup_irqs(ppc_md.pci_swizzle, ppc_md.pci_map_irq);
1297 /* Call machine dependent fixup */
1298 if (ppc_md.pcibios_fixup)
1299 ppc_md.pcibios_fixup();
1301 /* Allocate and assign resources */
1302 pcibios_allocate_bus_resources(&pci_root_buses);
1303 pcibios_allocate_resources(0);
1304 pcibios_allocate_resources(1);
1305 #ifdef CONFIG_PPC_PMAC
1306 pcibios_fixup_p2p_bridges();
1307 #endif /* CONFIG_PPC_PMAC */
1308 pcibios_assign_resources();
1310 /* Call machine dependent post-init code */
1311 if (ppc_md.pcibios_after_init)
1312 ppc_md.pcibios_after_init();
1317 subsys_initcall(pcibios_init);
1319 unsigned char __init
1320 common_swizzle(struct pci_dev *dev, unsigned char *pinp)
1322 struct pci_controller *hose = dev->sysdata;
1324 if (dev->bus->number != hose->first_busno) {
1327 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
1328 /* Move up the chain of bridges. */
1329 dev = dev->bus->self;
1330 } while (dev->bus->self);
1333 /* The slot is the idsel of the last bridge. */
1335 return PCI_SLOT(dev->devfn);
1338 unsigned long resource_fixup(struct pci_dev * dev, struct resource * res,
1339 unsigned long start, unsigned long size)
1344 void __init pcibios_fixup_bus(struct pci_bus *bus)
1346 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1347 unsigned long io_offset;
1348 struct resource *res;
1351 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1352 if (bus->parent == NULL) {
1353 /* This is a host bridge - fill in its resources */
1356 bus->resource[0] = res = &hose->io_resource;
1359 printk(KERN_ERR "I/O resource not set for host"
1360 " bridge %d\n", hose->index);
1362 res->end = IO_SPACE_LIMIT;
1363 res->flags = IORESOURCE_IO;
1365 res->start += io_offset;
1366 res->end += io_offset;
1368 for (i = 0; i < 3; ++i) {
1369 res = &hose->mem_resources[i];
1373 printk(KERN_ERR "Memory resource not set for "
1374 "host bridge %d\n", hose->index);
1375 res->start = hose->pci_mem_offset;
1377 res->flags = IORESOURCE_MEM;
1379 bus->resource[i+1] = res;
1382 /* This is a subordinate bridge */
1383 pci_read_bridge_bases(bus);
1385 for (i = 0; i < 4; ++i) {
1386 if ((res = bus->resource[i]) == NULL)
1390 if (io_offset && (res->flags & IORESOURCE_IO)) {
1391 res->start += io_offset;
1392 res->end += io_offset;
1393 } else if (hose->pci_mem_offset
1394 && (res->flags & IORESOURCE_MEM)) {
1395 res->start += hose->pci_mem_offset;
1396 res->end += hose->pci_mem_offset;
1401 if (ppc_md.pcibios_fixup_bus)
1402 ppc_md.pcibios_fixup_bus(bus);
1405 char __init *pcibios_setup(char *str)
1410 /* the next one is stolen from the alpha port... */
1412 pcibios_update_irq(struct pci_dev *dev, int irq)
1414 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
1415 /* XXX FIXME - update OF device tree node interrupt property */
1418 int pcibios_enable_device(struct pci_dev *dev, int mask)
1424 if (ppc_md.pcibios_enable_device_hook)
1425 if (ppc_md.pcibios_enable_device_hook(dev, 0))
1428 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1430 for (idx=0; idx<6; idx++) {
1431 r = &dev->resource[idx];
1432 if (r->flags & IORESOURCE_UNSET) {
1433 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
1436 if (r->flags & IORESOURCE_IO)
1437 cmd |= PCI_COMMAND_IO;
1438 if (r->flags & IORESOURCE_MEM)
1439 cmd |= PCI_COMMAND_MEMORY;
1441 if (cmd != old_cmd) {
1442 printk("PCI: Enabling device %s (%04x -> %04x)\n",
1443 pci_name(dev), old_cmd, cmd);
1444 pci_write_config_word(dev, PCI_COMMAND, cmd);
1449 struct pci_controller*
1450 pci_bus_to_hose(int bus)
1452 struct pci_controller* hose = hose_head;
1454 for (; hose; hose = hose->next)
1455 if (bus >= hose->first_busno && bus <= hose->last_busno)
1461 pci_bus_io_base(unsigned int bus)
1463 struct pci_controller *hose;
1465 hose = pci_bus_to_hose(bus);
1468 return hose->io_base_virt;
1472 pci_bus_io_base_phys(unsigned int bus)
1474 struct pci_controller *hose;
1476 hose = pci_bus_to_hose(bus);
1479 return hose->io_base_phys;
1483 pci_bus_mem_base_phys(unsigned int bus)
1485 struct pci_controller *hose;
1487 hose = pci_bus_to_hose(bus);
1490 return hose->pci_mem_offset;
1494 pci_resource_to_bus(struct pci_dev *pdev, struct resource *res)
1496 /* Hack alert again ! See comments in chrp_pci.c
1498 struct pci_controller* hose =
1499 (struct pci_controller *)pdev->sysdata;
1500 if (hose && res->flags & IORESOURCE_MEM)
1501 return res->start - hose->pci_mem_offset;
1502 /* We may want to do something with IOs here... */
1507 * Platform support for /proc/bus/pci/X/Y mmap()s,
1508 * modelled on the sparc64 implementation by Dave Miller.
1513 * Adjust vm_pgoff of VMA such that it is the physical page offset
1514 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
1516 * Basically, the user finds the base address for his device which he wishes
1517 * to mmap. They read the 32-bit value from the config space base register,
1518 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
1519 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
1521 * Returns negative error code on failure, zero on success.
1523 static __inline__ int
1524 __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
1525 enum pci_mmap_state mmap_state)
1527 struct pci_controller *hose = (struct pci_controller *) dev->sysdata;
1528 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
1529 unsigned long size = vma->vm_end - vma->vm_start;
1531 struct resource *res;
1536 return -EINVAL; /* should never happen */
1537 if (offset + size <= offset)
1540 if (mmap_state == pci_mmap_mem) {
1541 /* PCI memory space */
1542 base = hose->pci_mem_offset;
1543 for (i = 0; i < 3; ++i) {
1544 res = &hose->mem_resources[i];
1545 if (res->flags == 0)
1547 if (offset >= res->start - base
1548 && offset + size - 1 <= res->end - base) {
1553 offset += hose->pci_mem_offset;
1556 base = (unsigned long)hose->io_base_virt - isa_io_base;
1557 res = &hose->io_resource;
1558 if (offset >= res->start - base
1559 && offset + size - 1 <= res->end - base)
1561 offset += hose->io_base_phys;
1564 vma->vm_pgoff = offset >> PAGE_SHIFT;
1569 * Set vm_flags of VMA, as appropriate for this architecture, for a pci device
1572 static __inline__ void
1573 __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
1574 enum pci_mmap_state mmap_state)
1576 vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO;
1580 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1583 static __inline__ void
1584 __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
1585 enum pci_mmap_state mmap_state, int write_combine)
1587 int prot = pgprot_val(vma->vm_page_prot);
1589 /* XXX would be nice to have a way to ask for write-through */
1590 prot |= _PAGE_NO_CACHE;
1592 prot |= _PAGE_GUARDED;
1593 vma->vm_page_prot = __pgprot(prot);
1597 * Perform the actual remap of the pages for a PCI device mapping, as
1598 * appropriate for this architecture. The region in the process to map
1599 * is described by vm_start and vm_end members of VMA, the base physical
1600 * address is found in vm_pgoff.
1601 * The pci device structure is provided so that architectures may make mapping
1602 * decisions on a per-device or per-bus basis.
1604 * Returns a negative error code on failure, zero on success.
1606 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1607 enum pci_mmap_state mmap_state,
1612 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
1616 __pci_mmap_set_flags(dev, vma, mmap_state);
1617 __pci_mmap_set_pgprot(dev, vma, mmap_state, write_combine);
1619 ret = remap_page_range(vma, vma->vm_start, vma->vm_pgoff << PAGE_SHIFT,
1620 vma->vm_end - vma->vm_start, vma->vm_page_prot);
1625 /* Obsolete functions. Should be removed once the symbios driver
1629 phys_to_bus(unsigned long pa)
1631 struct pci_controller *hose;
1634 for (hose = hose_head; hose; hose = hose->next) {
1635 for (i = 0; i < 3; ++i) {
1636 if (pa >= hose->mem_resources[i].start
1637 && pa <= hose->mem_resources[i].end) {
1639 * XXX the hose->pci_mem_offset really
1640 * only applies to mem_resources[0].
1641 * We need a way to store an offset for
1642 * the others. -- paulus
1645 pa -= hose->pci_mem_offset;
1650 /* hmmm, didn't find it */
1655 pci_phys_to_bus(unsigned long pa, int busnr)
1657 struct pci_controller* hose = pci_bus_to_hose(busnr);
1660 return pa - hose->pci_mem_offset;
1664 pci_bus_to_phys(unsigned int ba, int busnr)
1666 struct pci_controller* hose = pci_bus_to_hose(busnr);
1669 return ba + hose->pci_mem_offset;
1672 /* Provide information on locations of various I/O regions in physical
1673 * memory. Do this on a per-card basis so that we choose the right
1675 * Note that the returned IO or memory base is a physical address
1678 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1680 struct pci_controller* hose;
1681 long result = -EOPNOTSUPP;
1683 /* Argh ! Please forgive me for that hack, but that's the
1684 * simplest way to get existing XFree to not lockup on some
1685 * G5 machines... So when something asks for bus 0 io base
1686 * (bus 0 is HT root), we return the AGP one instead.
1688 #ifdef CONFIG_PPC_PMAC
1689 if (_machine == _MACH_Pmac && machine_is_compatible("MacRISC4"))
1692 #endif /* CONFIG_PPC_PMAC */
1694 hose = pci_bus_to_hose(bus);
1699 case IOBASE_BRIDGE_NUMBER:
1700 return (long)hose->first_busno;
1702 return (long)hose->pci_mem_offset;
1704 return (long)hose->io_base_phys;
1706 return (long)isa_io_base;
1707 case IOBASE_ISA_MEM:
1708 return (long)isa_mem_base;
1715 pci_init_resource(struct resource *res, unsigned long start, unsigned long end,
1716 int flags, char *name)
1723 res->sibling = NULL;
1728 * Null PCI config access functions, for the case when we can't
1731 #define NULL_PCI_OP(rw, size, type) \
1733 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1735 return PCIBIOS_DEVICE_NOT_FOUND; \
1739 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1742 return PCIBIOS_DEVICE_NOT_FOUND;
1746 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1749 return PCIBIOS_DEVICE_NOT_FOUND;
1752 static struct pci_ops null_pci_ops =
1759 * These functions are used early on before PCI scanning is done
1760 * and all of the pci_dev and pci_bus structures have been created.
1762 static struct pci_bus *
1763 fake_pci_bus(struct pci_controller *hose, int busnr)
1765 static struct pci_bus bus;
1768 hose = pci_bus_to_hose(busnr);
1770 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1774 bus.ops = hose? hose->ops: &null_pci_ops;
1778 #define EARLY_PCI_OP(rw, size, type) \
1779 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1780 int devfn, int offset, type value) \
1782 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1783 devfn, offset, value); \
1786 EARLY_PCI_OP(read, byte, u8 *)
1787 EARLY_PCI_OP(read, word, u16 *)
1788 EARLY_PCI_OP(read, dword, u32 *)
1789 EARLY_PCI_OP(write, byte, u8)
1790 EARLY_PCI_OP(write, word, u16)
1791 EARLY_PCI_OP(write, dword, u32)