2 * arch/ppc/platforms/ebony.c
4 * Ebony board specific routines
6 * Matt Porter <mporter@mvista.com>
8 * Copyright 2002 MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/config.h>
17 #include <linux/stddef.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/errno.h>
21 #include <linux/reboot.h>
22 #include <linux/pci.h>
23 #include <linux/kdev_t.h>
24 #include <linux/types.h>
25 #include <linux/major.h>
26 #include <linux/blkdev.h>
27 #include <linux/console.h>
28 #include <linux/delay.h>
29 #include <linux/ide.h>
30 #include <linux/initrd.h>
31 #include <linux/irq.h>
32 #include <linux/seq_file.h>
33 #include <linux/root_dev.h>
34 #include <linux/tty.h>
35 #include <linux/serial.h>
36 #include <linux/serial_core.h>
38 #include <asm/system.h>
39 #include <asm/pgtable.h>
43 #include <asm/machdep.h>
44 #include <asm/pci-bridge.h>
47 #include <asm/bootinfo.h>
48 #include <asm/ppc4xx_pic.h>
51 * Ebony IRQ triggering/polarity settings
53 static u_char ebony_IRQ_initsenses[] __initdata = {
54 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 0: UART 0 */
55 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 1: UART 1 */
56 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 2: IIC 0 */
57 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 3: IIC 1 */
58 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 4: PCI Inb Mess */
59 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 5: PCI Cmd Wrt */
60 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 6: PCI PM */
61 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 7: PCI MSI 0 */
62 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 8: PCI MSI 1 */
63 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 9: PCI MSI 2 */
64 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 10: MAL TX EOB */
65 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 11: MAL RX EOB */
66 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 12: DMA Chan 0 */
67 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 13: DMA Chan 1 */
68 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 14: DMA Chan 2 */
69 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 15: DMA Chan 3 */
70 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 16: Reserved */
71 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 17: Reserved */
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 18: GPT Timer 0 */
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 19: GPT Timer 1 */
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 20: GPT Timer 2 */
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 21: GPT Timer 3 */
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 22: GPT Timer 4 */
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 23: Ext Int 0 */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 24: Ext Int 1 */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 25: Ext Int 2 */
80 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 26: Ext Int 3 */
81 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 27: Ext Int 4 */
82 (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* 28: Ext Int 5 */
83 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 29: Ext Int 6 */
84 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 30: UIC1 NC Int */
85 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 31: UIC1 Crit Int */
86 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 32: MAL SERR */
87 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 33: MAL TXDE */
88 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 34: MAL RXDE */
89 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 35: ECC Unc Err */
90 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 36: ECC Corr Err */
91 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 37: Ext Bus Ctrl */
92 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 38: Ext Bus Mstr */
93 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 39: OPB->PLB */
94 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 40: PCI MSI 3 */
95 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 41: PCI MSI 4 */
96 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 42: PCI MSI 5 */
97 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 43: PCI MSI 6 */
98 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 44: PCI MSI 7 */
99 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 45: PCI MSI 8 */
100 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 46: PCI MSI 9 */
101 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 47: PCI MSI 10 */
102 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 48: PCI MSI 11 */
103 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 49: PLB Perf Mon */
104 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 50: Ext Int 7 */
105 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 51: Ext Int 8 */
106 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 52: Ext Int 9 */
107 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 53: Ext Int 10 */
108 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 54: Ext Int 11 */
109 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 55: Ext Int 12 */
110 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 56: Ser ROM Err */
111 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 57: Reserved */
112 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 58: Reserved */
113 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 59: PCI Async Err */
114 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 60: EMAC 0 */
115 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 61: EMAC 0 WOL */
116 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 62: EMAC 1 */
117 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 63: EMAC 1 WOL */
120 extern void abort(void);
122 /* Global Variables */
126 ebony_calibrate_decr(void)
131 * Determine system clock speed
133 * If we are on Rev. B silicon, then use
134 * default external system clock. If we are
135 * on Rev. C silicon then errata forces us to
136 * use the internal clock.
138 switch (PVR_REV(mfspr(PVR))) {
139 case PVR_REV(PVR_440GP_RB):
140 freq = EBONY_440GP_RB_SYSCLK;
142 case PVR_REV(PVR_440GP_RC1):
144 freq = EBONY_440GP_RC_SYSCLK;
148 tb_ticks_per_jiffy = freq / HZ;
149 tb_to_us = mulhwu_scale_factor(freq, 1000000);
151 /* Set the time base to zero */
155 /* Clear any pending timer interrupts */
156 mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
158 /* Enable decrementer interrupt */
159 mtspr(SPRN_TCR, TCR_DIE);
163 ebony_show_cpuinfo(struct seq_file *m)
165 seq_printf(m, "vendor\t\t: IBM\n");
166 seq_printf(m, "machine\t\t: Ebony\n");
172 ebony_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
174 static char pci_irq_table[][4] =
176 * PCI IDSEL/INTPIN->INTLINE
180 { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */
181 { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */
182 { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */
183 { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */
186 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
187 return PCI_IRQ_TABLE_LOOKUP;
190 #define PCIX_WRITEL(value, offset) \
191 (writel(value, (u32)pcix_reg_base+offset))
194 * FIXME: This is only here to "make it work". This will move
195 * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
196 * configuration library. -Matt
199 ebony_setup_pcix(void)
203 pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX0_REG_SIZE);
205 /* Disable all windows */
206 PCIX_WRITEL(0, PCIX0_POM0SA);
207 PCIX_WRITEL(0, PCIX0_POM1SA);
208 PCIX_WRITEL(0, PCIX0_POM2SA);
209 PCIX_WRITEL(0, PCIX0_PIM0SA);
210 PCIX_WRITEL(0, PCIX0_PIM1SA);
211 PCIX_WRITEL(0, PCIX0_PIM2SA);
213 /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
214 PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
215 PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
216 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
217 PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
218 PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
220 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
221 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
222 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
223 PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
229 ebony_setup_hose(void)
231 struct pci_controller *hose;
233 /* Configure windows on the PCI-X host bridge */
236 hose = pcibios_alloc_controller();
241 hose->first_busno = 0;
242 hose->last_busno = 0xff;
244 hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET;
246 pci_init_resource(&hose->io_resource,
252 pci_init_resource(&hose->mem_resources[0],
258 hose->io_space.start = EBONY_PCI_LOWER_IO;
259 hose->io_space.end = EBONY_PCI_UPPER_IO;
260 hose->mem_space.start = EBONY_PCI_LOWER_MEM;
261 hose->mem_space.end = EBONY_PCI_UPPER_MEM;
263 (unsigned long)ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
264 hose->io_base_virt = (void *)isa_io_base;
266 setup_indirect_pci(hose,
267 EBONY_PCI_CFGA_PLB32,
268 EBONY_PCI_CFGD_PLB32);
269 hose->set_cfg_type = 1;
271 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
273 ppc_md.pci_swizzle = common_swizzle;
274 ppc_md.pci_map_irq = ebony_map_irq;
280 ebony_early_serial_map(void)
282 struct uart_port port;
284 /* Setup ioremapped serial port access */
285 memset(&port, 0, sizeof(port));
286 port.membase = ioremap64(PPC440GP_UART0_ADDR, 8);
288 port.uartclk = BASE_BAUD * 16;
290 port.iotype = SERIAL_IO_MEM;
291 port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
294 if (early_serial_setup(&port) != 0) {
295 printk("Early serial init of port 0 failed\n");
298 port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
302 if (early_serial_setup(&port) != 0) {
303 printk("Early serial init of port 1 failed\n");
308 ebony_setup_arch(void)
310 unsigned char * vpd_base;
311 struct ibm440gp_clocks clocks;
313 #if !defined(CONFIG_BDI_SWITCH)
315 * The Abatron BDI JTAG debugger does not tolerate others
316 * mucking with the debug registers.
318 mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
321 /* Retrieve MAC addresses */
322 vpd_base = ioremap64(EBONY_VPD_BASE, EBONY_VPD_SIZE);
323 memcpy(__res.bi_enetaddr[0],EBONY_NA0_ADDR(vpd_base),6);
324 memcpy(__res.bi_enetaddr[1],EBONY_NA1_ADDR(vpd_base),6);
327 * Determine various clocks.
328 * To be completely correct we should get SysClk
329 * from FPGA, because it can be changed by on-board switches
332 ibm440gp_get_clocks(&clocks, 33333333, 6 * 1843200);
333 __res.bi_opb_busfreq = clocks.opb;
335 /* Use IIC in standard (100 kHz) mode */
336 __res.bi_iic_fast[0] = __res.bi_iic_fast[1] = 0;
338 /* Setup TODC access */
339 TODC_INIT(TODC_TYPE_DS1743,
342 ioremap64(EBONY_RTC_ADDR, EBONY_RTC_SIZE),
345 /* init to some ~sane value until calibrate_delay() runs */
346 loops_per_jiffy = 50000000/HZ;
348 /* Setup PCI host bridge */
351 #ifdef CONFIG_BLK_DEV_INITRD
353 ROOT_DEV = Root_RAM0;
356 #ifdef CONFIG_ROOT_NFS
359 ROOT_DEV = Root_HDA1;
363 conswitchp = &dummy_con;
366 ebony_early_serial_map();
368 ibm4xxPIC_InitSenses = ebony_IRQ_initsenses;
369 ibm4xxPIC_NumInitSenses = sizeof(ebony_IRQ_initsenses);
371 /* Identify the system */
372 printk("IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))\n");
376 ebony_restart(char *cmd)
383 ebony_power_off(void)
397 * Read the 440GP memory controller to get size of system memory.
399 static unsigned long __init
400 ebony_find_end_of_memory(void)
410 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B0CR);
413 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B1CR);
416 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B2CR);
419 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B3CR);
423 bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
425 if (!(bank_config & SDRAM_CONFIG_BANK_ENABLE))
427 switch (SDRAM_CONFIG_BANK_SIZE(bank_config))
429 case SDRAM_CONFIG_SIZE_8M:
430 mem_size += PPC44x_MEM_SIZE_8M;
432 case SDRAM_CONFIG_SIZE_16M:
433 mem_size += PPC44x_MEM_SIZE_16M;
435 case SDRAM_CONFIG_SIZE_32M:
436 mem_size += PPC44x_MEM_SIZE_32M;
438 case SDRAM_CONFIG_SIZE_64M:
439 mem_size += PPC44x_MEM_SIZE_64M;
441 case SDRAM_CONFIG_SIZE_128M:
442 mem_size += PPC44x_MEM_SIZE_128M;
444 case SDRAM_CONFIG_SIZE_256M:
445 mem_size += PPC44x_MEM_SIZE_256M;
447 case SDRAM_CONFIG_SIZE_512M:
448 mem_size += PPC44x_MEM_SIZE_512M;
462 for (i = 0; i < NR_IRQS; i++)
463 irq_desc[i].handler = ppc4xx_pic;
466 #ifdef CONFIG_SERIAL_TEXT_DEBUG
467 #include <linux/serialP.h>
468 #include <linux/serial_reg.h>
469 #include <asm/serial.h>
471 static struct serial_state rs_table[RS_TABLE_SIZE] = {
472 SERIAL_PORT_DFNS /* Defined in <asm/serial.h> */
476 ebony_progress(char *s, unsigned short hex)
479 volatile unsigned long com_port;
482 com_port = (unsigned long)rs_table[0].iomem_base;
483 shift = rs_table[0].iomem_reg_shift;
485 while ((c = *s++) != 0) {
486 while ((*((volatile unsigned char *)com_port +
487 (UART_LSR << shift)) & UART_LSR_THRE) == 0)
489 *(volatile unsigned char *)com_port = c;
493 /* Send LF/CR to pretty up output */
494 while ((*((volatile unsigned char *)com_port +
495 (UART_LSR << shift)) & UART_LSR_THRE) == 0)
497 *(volatile unsigned char *)com_port = '\r';
498 while ((*((volatile unsigned char *)com_port +
499 (UART_LSR << shift)) & UART_LSR_THRE) == 0)
501 *(volatile unsigned char *)com_port = '\n';
503 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
505 void __init platform_init(unsigned long r3, unsigned long r4,
506 unsigned long r5, unsigned long r6, unsigned long r7)
508 parse_bootinfo((struct bi_record *) (r3 + KERNELBASE));
510 ppc_md.setup_arch = ebony_setup_arch;
511 ppc_md.show_cpuinfo = ebony_show_cpuinfo;
512 ppc_md.init_IRQ = ebony_init_irq;
513 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
515 ppc_md.find_end_of_memory = ebony_find_end_of_memory;
517 ppc_md.restart = ebony_restart;
518 ppc_md.power_off = ebony_power_off;
519 ppc_md.halt = ebony_halt;
521 ppc_md.calibrate_decr = ebony_calibrate_decr;
522 ppc_md.time_init = todc_time_init;
523 ppc_md.set_rtc_time = todc_set_rtc_time;
524 ppc_md.get_rtc_time = todc_get_rtc_time;
526 ppc_md.nvram_read_val = todc_direct_read_val;
527 ppc_md.nvram_write_val = todc_direct_write_val;
529 #ifdef CONFIG_SERIAL_TEXT_DEBUG
530 ppc_md.progress = ebony_progress;
531 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
533 ppc_md.early_serial_map = ebony_early_serial_map;