2 * arch/ppc/platforms/4xx/ibm405gp.h
4 * Author: Armin Kuster akuster@mvista.com
6 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
13 #ifndef __ASM_IBM405GP_H__
14 #define __ASM_IBM405GP_H__
16 #include <linux/config.h>
18 /* ibm405.h at bottom of this file */
21 * PCI Bridge config reg definitions
25 #define PPC405_PCI_CONFIG_ADDR 0xeec00000
26 #define PPC405_PCI_CONFIG_DATA 0xeec00004
28 #define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
30 #define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
31 #define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
32 #define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
34 #define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */
35 #define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
36 #define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
37 #define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
39 #define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
41 #define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE)
42 #define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR
43 #define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
44 #define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR)
45 #define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR
46 #define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
47 #define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000)
48 #define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR
49 #define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
50 #define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
51 #define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
52 #define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
54 #define OPB_BASE_START 0x40000000
55 #define EBIU_BASE_START 0xF0100000
57 /* serial port defines */
58 #define RS_TABLE_SIZE 2
63 #define PCIL0_BASE 0xEF400000
64 #define UART0_IO_BASE 0xEF600300
65 #define UART1_IO_BASE 0xEF600400
66 #define IIC0_BASE 0xEF600500
67 #define OPB0_BASE 0xEF600600
68 #define GPIO0_BASE 0xEF600700
69 #define EMAC0_BASE 0xEF600800
70 #define BL_MAC_WOL 9 /* WOL */
71 #define BL_MAL_SERR 10 /* MAL SERR */
72 #define BL_MAL_TXDE 13 /* MAL TXDE */
73 #define BL_MAL_RXDE 14 /* MAL RXDE */
74 #define BL_MAL_TXEOB 11 /* MAL TX EOB */
75 #define BL_MAL_RXEOB 12 /* MAL RX EOB */
76 #define BL_MAC_ETH0 15 /* MAC */
84 #define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
86 #define STD_UART_OP(num) \
87 { 0, BASE_BAUD, 0, UART##num##_INT, \
88 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
89 iomem_base: (u8 *)UART##num##_IO_BASE, \
90 io_type: SERIAL_IO_MEM},
92 #if defined(CONFIG_UART0_TTYS0)
93 #define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
94 #define SERIAL_PORT_DFNS \
99 #if defined(CONFIG_UART0_TTYS1)
100 #define SERIAL_DEBUG_IO_BASE UART1_IO_BASE
101 #define SERIAL_PORT_DFNS \
107 #define DCRN_CHCR_BASE 0x0B1
108 #define DCRN_CHPSR_BASE 0x0B4
109 #define DCRN_CPMSR_BASE 0x0B8
110 #define DCRN_CPMFR_BASE 0x0BA
112 #define CHR0_U0EC 0x00000080 /* Select external clock for UART0 */
113 #define CHR0_U1EC 0x00000040 /* Select external clock for UART1 */
114 #define CHR0_UDIV 0x0000003E /* UART internal clock divisor */
115 #define CHR1_CETE 0x00800000 /* CPU external timer enable */
117 #define DCRN_CHPSR_BASE 0x0B4
118 #define PSR_PLL_FWD_MASK 0xC0000000
119 #define PSR_PLL_FDBACK_MASK 0x30000000
120 #define PSR_PLL_TUNING_MASK 0x0E000000
121 #define PSR_PLB_CPU_MASK 0x01800000
122 #define PSR_OPB_PLB_MASK 0x00600000
123 #define PSR_PCI_PLB_MASK 0x00180000
124 #define PSR_EB_PLB_MASK 0x00060000
125 #define PSR_ROM_WIDTH_MASK 0x00018000
126 #define PSR_ROM_LOC 0x00004000
127 #define PSR_PCI_ASYNC_EN 0x00001000
128 #define PSR_PCI_ARBIT_EN 0x00000400
130 #define IBM_CPM_IIC0 0x80000000 /* IIC interface */
131 #define IBM_CPM_PCI 0x40000000 /* PCI bridge */
132 #define IBM_CPM_CPU 0x20000000 /* processor core */
133 #define IBM_CPM_DMA 0x10000000 /* DMA controller */
134 #define IBM_CPM_OPB 0x08000000 /* PLB to OPB bridge */
135 #define IBM_CPM_DCP 0x04000000 /* CodePack */
136 #define IBM_CPM_EBC 0x02000000 /* ROM/SRAM peripheral controller */
137 #define IBM_CPM_SDRAM0 0x01000000 /* SDRAM memory controller */
138 #define IBM_CPM_PLB 0x00800000 /* PLB bus arbiter */
139 #define IBM_CPM_GPIO0 0x00400000 /* General Purpose IO (??) */
140 #define IBM_CPM_UART0 0x00200000 /* serial port 0 */
141 #define IBM_CPM_UART1 0x00100000 /* serial port 1 */
142 #define IBM_CPM_UIC 0x00080000 /* Universal Interrupt Controller */
143 #define IBM_CPM_TMRCLK 0x00040000 /* CPU timers */
144 #define IBM_CPM_EMAC0 0x00020000 /* on-chip ethernet MM unit */
145 #define DFLT_IBM4xx_PM ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \
146 | IBM_CPM_OPB | IBM_CPM_EBC \
147 | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
148 | IBM_CPM_UIC | IBM_CPM_TMRCLK)
150 #define DCRN_DMA0_BASE 0x100
151 #define DCRN_DMA1_BASE 0x108
152 #define DCRN_DMA2_BASE 0x110
153 #define DCRN_DMA3_BASE 0x118
154 #define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
155 #define DCRN_DMASR_BASE 0x120
156 #define DCRN_EBC_BASE 0x012
157 #define DCRN_DCP0_BASE 0x014
158 #define DCRN_MAL_BASE 0x180
159 #define DCRN_OCM0_BASE 0x018
160 #define DCRN_PLB0_BASE 0x084
161 #define DCRN_PLLMR_BASE 0x0B0
162 #define DCRN_POB0_BASE 0x0A0
163 #define DCRN_SDRAM0_BASE 0x010
164 #define DCRN_UIC0_BASE 0x0C0
165 #define UIC0 DCRN_UIC0_BASE
167 #include <asm/ibm405.h>
169 #endif /* __ASM_IBM405GP_H__ */
170 #endif /* __KERNEL__ */