2 * arch/ppc/platforms/ibm440gx.h
6 * Matt Porter <mporter@mvista.com>
8 * Copyright 2002 Roland Dreier
9 * Copyright 2003 MontaVista Software, Inc.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
19 #ifndef __PPC_PLATFORMS_IBM440GX_H
20 #define __PPC_PLATFORMS_IBM440GX_H
22 #include <linux/config.h>
24 #include <asm/ibm44x.h>
27 #define PPC440GX_UART0_ADDR 0x0000000140000200ULL
28 #define PPC440GX_UART1_ADDR 0x0000000140000300ULL
33 #define PPC440GX_EMAC0_ADDR 0x0000000140000800ULL
34 #define PPC440GX_EMAC1_ADDR 0x0000000140000900ULL
35 #define PPC440GX_EMAC2_ADDR 0x0000000140000C00ULL
36 #define PPC440GX_EMAC3_ADDR 0x0000000140000E00ULL
37 #define PPC440GX_EMAC_SIZE 0xFC
39 #define BL_MAC_WOL 61 /* WOL */
40 #define BL_MAC_WOL1 63 /* WOL */
41 #define BL_MAC_WOL2 65 /* WOL */
42 #define BL_MAC_WOL3 67 /* WOL */
43 #define BL_MAL_SERR 32 /* MAL SERR */
44 #define BL_MAL_TXDE 33 /* MAL TXDE */
45 #define BL_MAL_RXDE 34 /* MAL RXDE */
46 #define BL_MAL_TXEOB 10 /* MAL TX EOB */
47 #define BL_MAL_RXEOB 11 /* MAL RX EOB */
48 #define BL_MAC_ETH0 60 /* MAC */
49 #define BL_MAC_ETH1 62 /* MAC */
50 #define BL_MAC_ETH2 64 /* MAC */
51 #define BL_MAC_ETH3 66 /* MAC */
52 #define BL_TAH0 68 /* TAH 0 */
53 #define BL_TAH1 69 /* TAH 1 */
56 #define PPC440GX_TAH0_ADDR 0x0000000140000B00ULL
57 #define PPC440GX_TAH1_ADDR 0x0000000140000D00ULL
58 #define PPC440GX_TAH_SIZE 0xFC
61 #define PPC440GX_ZMII_ADDR 0x0000000140000780ULL
62 #define PPC440GX_ZMII_SIZE 0x0c
65 #define PPC440GX_RGMII_ADDR 0x0000000140000790ULL
66 #define PPC440GX_RGMII_SIZE 0x0c
69 #define PPC440GX_IIC0_ADDR 0x40000400
70 #define PPC440GX_IIC1_ADDR 0x40000500
75 #define PPC440GX_GPIO0_ADDR 0x0000000140000700ULL
77 /* Clock and Power Management */
78 #define IBM_CPM_IIC0 0x80000000 /* IIC interface */
79 #define IBM_CPM_IIC1 0x40000000 /* IIC interface */
80 #define IBM_CPM_PCI 0x20000000 /* PCI bridge */
81 #define IBM_CPM_RGMII 0x10000000 /* RGMII */
82 #define IBM_CPM_TAHOE0 0x08000000 /* TAHOE 0 */
83 #define IBM_CPM_TAHOE1 0x04000000 /* TAHOE 1 */
84 #define IBM_CPM_CPU 0x02000000 /* processor core */
85 #define IBM_CPM_DMA 0x01000000 /* DMA controller */
86 #define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
87 #define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
88 #define IBM_CPM_EBC 0x00200000 /* External Bux Controller */
89 #define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
90 #define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
91 #define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */
92 #define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */
93 #define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
94 #define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
95 #define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
96 #define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
97 #define IBM_CPM_UART0 0x00000200 /* serial port 0 */
98 #define IBM_CPM_UART1 0x00000100 /* serial port 1 */
99 #define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
100 #define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
101 #define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */
102 #define IBM_CPM_EMAC1 0x00000010 /* EMAC 1 */
103 #define IBM_CPM_EMAC2 0x00000008 /* EMAC 2 */
104 #define IBM_CPM_EMAC3 0x00000004 /* EMAC 3 */
106 #define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
107 | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
108 | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
109 | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
110 | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
111 | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
112 | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
115 #define PPC440GX_OPB_BASE_START 0x0000000140000000ULL
118 * Serial port defines
120 #define RS_TABLE_SIZE 2
122 #endif /* __PPC_PLATFORMS_IBM440GX_H */
123 #endif /* __KERNEL__ */