2 * arch/ppc/platforms/ocotea.c
4 * Ocotea board specific routines
6 * Matt Porter <mporter@mvista.com>
8 * Copyright 2003 MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/config.h>
17 #include <linux/stddef.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/errno.h>
21 #include <linux/reboot.h>
22 #include <linux/pci.h>
23 #include <linux/kdev_t.h>
24 #include <linux/types.h>
25 #include <linux/major.h>
26 #include <linux/blkdev.h>
27 #include <linux/console.h>
28 #include <linux/delay.h>
29 #include <linux/ide.h>
30 #include <linux/initrd.h>
31 #include <linux/irq.h>
32 #include <linux/seq_file.h>
33 #include <linux/root_dev.h>
34 #include <linux/tty.h>
35 #include <linux/serial.h>
36 #include <linux/serial_core.h>
38 #include <asm/system.h>
39 #include <asm/pgtable.h>
43 #include <asm/machdep.h>
45 #include <asm/pci-bridge.h>
48 #include <asm/bootinfo.h>
49 #include <asm/ppc4xx_pic.h>
51 #include <syslib/ibm440gx_common.h>
54 * This is a horrible kludge, we eventually need to abstract this
55 * generic PHY stuff, so the standard phy mode defines can be
56 * easily used from arch code.
58 #include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
60 extern void abort(void);
63 ocotea_calibrate_decr(void)
69 tb_ticks_per_jiffy = freq / HZ;
70 tb_to_us = mulhwu_scale_factor(freq, 1000000);
72 /* Set the time base to zero */
76 /* Clear any pending timer interrupts */
77 mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
79 /* Enable decrementer interrupt */
80 mtspr(SPRN_TCR, TCR_DIE);
84 ocotea_show_cpuinfo(struct seq_file *m)
86 seq_printf(m, "vendor\t\t: IBM\n");
87 seq_printf(m, "machine\t\t: PPC440GX EVB (Ocotea)\n");
92 ocotea_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
94 static char pci_irq_table[][4] =
96 * PCI IDSEL/INTPIN->INTLINE
100 { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */
101 { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */
102 { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */
103 { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */
106 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
107 return PCI_IRQ_TABLE_LOOKUP;
110 #define PCIX_READW(offset) \
111 (readw((u32)pcix_reg_base+offset))
113 #define PCIX_WRITEW(value, offset) \
114 (writew(value, (u32)pcix_reg_base+offset))
116 #define PCIX_WRITEL(value, offset) \
117 (writel(value, (u32)pcix_reg_base+offset))
120 * FIXME: This is only here to "make it work". This will move
121 * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
122 * configuration library. -Matt
125 ocotea_setup_pcix(void)
129 pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX0_REG_SIZE);
131 /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
132 PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
134 /* Disable all windows */
135 PCIX_WRITEL(0, PCIX0_POM0SA);
136 PCIX_WRITEL(0, PCIX0_POM1SA);
137 PCIX_WRITEL(0, PCIX0_POM2SA);
138 PCIX_WRITEL(0, PCIX0_PIM0SA);
139 PCIX_WRITEL(0, PCIX0_PIM0SAH);
140 PCIX_WRITEL(0, PCIX0_PIM1SA);
141 PCIX_WRITEL(0, PCIX0_PIM2SA);
142 PCIX_WRITEL(0, PCIX0_PIM2SAH);
144 /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
145 PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
146 PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
147 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
148 PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
149 PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
151 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
152 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
153 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
154 PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA);
160 ocotea_setup_hose(void)
162 struct pci_controller *hose;
164 /* Configure windows on the PCI-X host bridge */
167 hose = pcibios_alloc_controller();
172 hose->first_busno = 0;
173 hose->last_busno = 0xff;
175 hose->pci_mem_offset = OCOTEA_PCI_MEM_OFFSET;
177 pci_init_resource(&hose->io_resource,
183 pci_init_resource(&hose->mem_resources[0],
184 OCOTEA_PCI_LOWER_MEM,
185 OCOTEA_PCI_UPPER_MEM,
189 hose->io_space.start = OCOTEA_PCI_LOWER_IO;
190 hose->io_space.end = OCOTEA_PCI_UPPER_IO;
191 hose->mem_space.start = OCOTEA_PCI_LOWER_MEM;
192 hose->mem_space.end = OCOTEA_PCI_UPPER_MEM;
194 (unsigned long)ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE);
195 hose->io_base_virt = (void *)isa_io_base;
197 setup_indirect_pci(hose,
198 OCOTEA_PCI_CFGA_PLB32,
199 OCOTEA_PCI_CFGD_PLB32);
200 hose->set_cfg_type = 1;
202 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
204 ppc_md.pci_swizzle = common_swizzle;
205 ppc_md.pci_map_irq = ocotea_map_irq;
212 ocotea_early_serial_map(const struct ibm44x_clocks *clks)
214 struct uart_port port;
216 /* Setup ioremapped serial port access */
217 memset(&port, 0, sizeof(port));
218 port.membase = ioremap64(PPC440GX_UART0_ADDR, 8);
219 port.irq = UART0_INT;
220 port.uartclk = clks->uart0;
222 port.iotype = SERIAL_IO_MEM;
223 port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
226 if (early_serial_setup(&port) != 0) {
227 printk("Early serial init of port 0 failed\n");
230 port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
231 port.irq = UART1_INT;
232 port.uartclk = clks->uart1;
235 if (early_serial_setup(&port) != 0) {
236 printk("Early serial init of port 1 failed\n");
241 ocotea_setup_arch(void)
244 unsigned long long mac64;
246 struct ocp_func_emac_data *emacdata;
248 struct ibm44x_clocks clocks;
251 * Note: Current rev. board only operates in Group 4a
252 * mode, so we always set EMAC0-1 for SMII and EMAC2-3
253 * for RGMII (though these could run in RTBI just the same).
255 * The FPGA reg 3 information isn't even suitable for
256 * determining the phy_mode, so if the board becomes
257 * usable in !4a, it will be necessary to parse an environment
258 * variable from the firmware or similar to properly configure
259 * the phy_map/phy_mode.
261 /* Set phy_map, phy_mode, and mac_addr for each EMAC */
262 addr = ioremap64(OCOTEA_MAC_BASE, OCOTEA_MAC_SIZE);
263 for (i=0; i<4; i++) {
264 mac64 = simple_strtoull(addr+OCOTEA_MAC_OFFSET*i, 0, 16);
265 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
266 emacdata = def->additions;
268 emacdata->phy_map = 0x00000001; /* Skip 0x00 */
269 emacdata->phy_mode = PHY_MODE_SMII;
272 emacdata->phy_map = 0x0000ffff; /* Skip 0x00-0x0f */
273 emacdata->phy_mode = PHY_MODE_RGMII;
275 memcpy(emacdata->mac_addr, (char *)&mac64+2, 6);
279 ibm440gx_tah_enable();
281 #if !defined(CONFIG_BDI_SWITCH)
283 * The Abatron BDI JTAG debugger does not tolerate others
284 * mucking with the debug registers.
286 mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
290 * Determine various clocks.
291 * To be completely correct we should get SysClk
292 * from FPGA, because it can be changed by on-board switches
295 ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
296 ocp_sys_info.opb_bus_freq = clocks.opb;
298 /* Setup TODC access */
299 TODC_INIT(TODC_TYPE_DS1743,
302 ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE),
305 /* init to some ~sane value until calibrate_delay() runs */
306 loops_per_jiffy = 50000000/HZ;
308 /* Setup PCI host bridge */
311 #ifdef CONFIG_BLK_DEV_INITRD
313 ROOT_DEV = Root_RAM0;
316 #ifdef CONFIG_ROOT_NFS
319 ROOT_DEV = Root_HDA1;
322 #ifdef CONFIG_DUMMY_CONSOLE
323 conswitchp = &dummy_con;
326 ocotea_early_serial_map(&clocks);
328 /* Identify the system */
329 printk("IBM Ocotea port (MontaVista Software, Inc. <source@mvista.com>)\n");
333 ocotea_restart(char *cmd)
340 ocotea_power_off(void)
354 * Read the 440GX memory controller to get size of system memory.
356 static unsigned long __init
357 ocotea_find_end_of_memory(void)
367 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B0CR);
370 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B1CR);
373 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B2CR);
376 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B3CR);
380 bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
382 if (!(bank_config & SDRAM_CONFIG_BANK_ENABLE))
384 switch (SDRAM_CONFIG_BANK_SIZE(bank_config))
386 case SDRAM_CONFIG_SIZE_8M:
387 mem_size += PPC44x_MEM_SIZE_8M;
389 case SDRAM_CONFIG_SIZE_16M:
390 mem_size += PPC44x_MEM_SIZE_16M;
392 case SDRAM_CONFIG_SIZE_32M:
393 mem_size += PPC44x_MEM_SIZE_32M;
395 case SDRAM_CONFIG_SIZE_64M:
396 mem_size += PPC44x_MEM_SIZE_64M;
398 case SDRAM_CONFIG_SIZE_128M:
399 mem_size += PPC44x_MEM_SIZE_128M;
401 case SDRAM_CONFIG_SIZE_256M:
402 mem_size += PPC44x_MEM_SIZE_256M;
404 case SDRAM_CONFIG_SIZE_512M:
405 mem_size += PPC44x_MEM_SIZE_512M;
413 ocotea_init_irq(void)
419 for (i = 0; i < NR_IRQS; i++)
420 irq_desc[i].handler = ppc4xx_pic;
423 #ifdef CONFIG_SERIAL_TEXT_DEBUG
424 #include <linux/serialP.h>
425 #include <linux/serial_reg.h>
426 #include <asm/serial.h>
427 struct serial_state rs_table[RS_TABLE_SIZE] = {
428 SERIAL_PORT_DFNS /* Defined in <asm/serial.h> */
432 ocotea_progress(char *s, unsigned short hex)
435 volatile unsigned long com_port;
438 com_port = (unsigned long)rs_table[0].iomem_base;
439 shift = rs_table[0].iomem_reg_shift;
441 while ((c = *s++) != 0) {
442 while ((*((volatile unsigned char *)com_port +
443 (UART_LSR << shift)) & UART_LSR_THRE) == 0)
445 *(volatile unsigned char *)com_port = c;
449 /* Send LF/CR to pretty up output */
450 while ((*((volatile unsigned char *)com_port +
451 (UART_LSR << shift)) & UART_LSR_THRE) == 0)
453 *(volatile unsigned char *)com_port = '\r';
454 while ((*((volatile unsigned char *)com_port +
455 (UART_LSR << shift)) & UART_LSR_THRE) == 0)
457 *(volatile unsigned char *)com_port = '\n';
459 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
465 io_block_mapping(0xe0000000, 0x0000000140000000,
466 0x00001000, _PAGE_IO);
470 void __init platform_init(unsigned long r3, unsigned long r4,
471 unsigned long r5, unsigned long r6, unsigned long r7)
473 parse_bootinfo((struct bi_record *) (r3 + KERNELBASE));
475 /* Disable L2-Cache due to hardware issues */
476 ibm440gx_l2c_disable();
478 ppc_md.setup_arch = ocotea_setup_arch;
479 ppc_md.show_cpuinfo = ocotea_show_cpuinfo;
480 ppc_md.init_IRQ = ocotea_init_irq;
481 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
483 ppc_md.find_end_of_memory = ocotea_find_end_of_memory;
485 ppc_md.restart = ocotea_restart;
486 ppc_md.power_off = ocotea_power_off;
487 ppc_md.halt = ocotea_halt;
489 ppc_md.calibrate_decr = ocotea_calibrate_decr;
490 ppc_md.time_init = todc_time_init;
491 ppc_md.set_rtc_time = todc_set_rtc_time;
492 ppc_md.get_rtc_time = todc_get_rtc_time;
494 ppc_md.nvram_read_val = todc_direct_read_val;
495 ppc_md.nvram_write_val = todc_direct_write_val;
497 #ifdef CONFIG_SERIAL_TEXT_DEBUG
498 ppc_md.progress = ocotea_progress;
499 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
501 ppc_md.early_serial_map = ocotea_early_serial_map;