2 * arch/ppc/platforms/ocotea.h
4 * Ocotea board definitions
6 * Matt Porter <mporter@mvista.com>
8 * Copyright 2003 MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
18 #ifndef __ASM_OCOTEA_H__
19 #define __ASM_OCOTEA_H__
21 #include <linux/config.h>
22 #include <platforms/4xx/ibm440gx.h>
24 /* F/W TLB mapping used in bootloader glue to reset EMAC */
25 #define PPC44x_EMAC0_MR0 0xE0000800
27 /* Location of MAC addresses in firmware */
28 #define OCOTEA_MAC_BASE (OCOTEA_SMALL_FLASH_HIGH+0xb0500)
29 #define OCOTEA_MAC_SIZE 0x200
30 #define OCOTEA_MAC_OFFSET 0x100
32 /* Default clock rate */
33 #define OCOTEA_SYSCLK 25000000
35 /* RTC/NVRAM location */
36 #define OCOTEA_RTC_ADDR 0x0000000148000000ULL
37 #define OCOTEA_RTC_SIZE 0x2000
40 #define OCOTEA_FPGA_REG_0 0x0000000148300000ULL
41 #define OCOTEA_BOOT_LARGE_FLASH(x) (x & 0x40)
42 #define OCOTEA_SMALL_FLASH_LOW 0x00000001ff900000ULL
43 #define OCOTEA_SMALL_FLASH_HIGH 0x00000001fff00000ULL
44 #define OCOTEA_SMALL_FLASH_SIZE 0x100000
45 #define OCOTEA_LARGE_FLASH_LOW 0x00000001ff800000ULL
46 #define OCOTEA_LARGE_FLASH_HIGH 0x00000001ffc00000ULL
47 #define OCOTEA_LARGE_FLASH_SIZE 0x400000
49 /* FPGA_REG_3 (Ethernet Groups) */
50 #define OCOTEA_FPGA_REG_3 0x0000000148300003ULL
55 #define RS_TABLE_SIZE 2
57 /* OpenBIOS defined UART mappings, used before early_serial_setup */
58 #define UART0_IO_BASE (u8 *) 0xE0000200
59 #define UART1_IO_BASE (u8 *) 0xE0000300
61 #define BASE_BAUD 11059200/16
62 #define STD_UART_OP(num) \
63 { 0, BASE_BAUD, 0, UART##num##_INT, \
64 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
65 iomem_base: UART##num##_IO_BASE, \
66 io_type: SERIAL_IO_MEM},
68 #define SERIAL_PORT_DFNS \
73 #define OCOTEA_PCI_LOWER_IO 0x00000000
74 #define OCOTEA_PCI_UPPER_IO 0x0000ffff
75 #define OCOTEA_PCI_LOWER_MEM 0x80000000
76 #define OCOTEA_PCI_UPPER_MEM 0xffffefff
78 #define OCOTEA_PCI_CFGREGS_BASE 0x000000020ec00000ULL
79 #define OCOTEA_PCI_CFGA_PLB32 0x0ec00000
80 #define OCOTEA_PCI_CFGD_PLB32 0x0ec00004
82 #define OCOTEA_PCI_IO_BASE 0x0000000208000000ULL
83 #define OCOTEA_PCI_IO_SIZE 0x00010000
84 #define OCOTEA_PCI_MEM_OFFSET 0x00000000
86 #endif /* __ASM_OCOTEA_H__ */
87 #endif /* __KERNEL__ */