2 * arch/ppc/platform/85xx/mpc85xx_cds_common.c
4 * MPC85xx CDS board specific routines
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
8 * Copyright 2004 Freescale Semiconductor, Inc
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/config.h>
17 #include <linux/stddef.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/errno.h>
21 #include <linux/reboot.h>
22 #include <linux/pci.h>
23 #include <linux/kdev_t.h>
24 #include <linux/major.h>
25 #include <linux/console.h>
26 #include <linux/delay.h>
27 #include <linux/irq.h>
28 #include <linux/seq_file.h>
29 #include <linux/serial.h>
30 #include <linux/module.h>
31 #include <linux/root_dev.h>
32 #include <linux/initrd.h>
33 #include <linux/tty.h>
34 #include <linux/serial_core.h>
35 #include <linux/fsl_devices.h>
37 #include <asm/system.h>
38 #include <asm/pgtable.h>
40 #include <asm/atomic.h>
43 #include <asm/machdep.h>
45 #include <asm/open_pic.h>
46 #include <asm/bootinfo.h>
47 #include <asm/pci-bridge.h>
48 #include <asm/mpc85xx.h>
50 #include <asm/immap_85xx.h>
51 #include <asm/immap_cpm2.h>
52 #include <asm/ppc_sys.h>
55 #include <mm/mmu_decl.h>
56 #include <syslib/cpm2_pic.h>
57 #include <syslib/ppc85xx_common.h>
58 #include <syslib/ppc85xx_setup.h>
62 unsigned long isa_io_base = 0;
63 unsigned long isa_mem_base = 0;
66 extern unsigned long total_memory; /* in mm/init */
68 unsigned char __res[sizeof (bd_t)];
70 static int cds_pci_slot = 2;
71 static volatile u8 * cadmus;
73 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
75 static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
80 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
81 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
82 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
83 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
84 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
85 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
86 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
87 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
88 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
89 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
90 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
91 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
92 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
93 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
94 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
95 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
96 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
97 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
98 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
99 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
100 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
101 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
102 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
103 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
104 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
105 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
106 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
107 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
108 #if defined(CONFIG_PCI)
109 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 0: PCI1 slot */
110 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI1 slot */
111 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI1 slot */
112 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI1 slot */
114 0x0, /* External 0: */
115 0x0, /* External 1: */
116 0x0, /* External 2: */
117 0x0, /* External 3: */
119 0x0, /* External 4: */
120 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
121 0x0, /* External 6: */
122 0x0, /* External 7: */
123 0x0, /* External 8: */
124 0x0, /* External 9: */
125 0x0, /* External 10: */
126 #if defined(CONFIG_85xx_PCI2) && defined(CONFIG_PCI)
127 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 11: PCI2 slot 0 */
129 0x0, /* External 11: */
133 /* ************************************************************************ */
135 mpc85xx_cds_show_cpuinfo(struct seq_file *m)
137 uint pvid, svid, phid1;
138 uint memsize = total_memory;
139 bd_t *binfo = (bd_t *) __res;
142 /* get the core frequency */
143 freq = binfo->bi_intfreq;
148 seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
149 seq_printf(m, "Machine\t\t: CDS (%x)\n", cadmus[CM_VER]);
150 seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
151 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
152 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
154 /* Display cpu Pll setting */
156 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
158 /* Display the amount of memory */
159 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
165 static void cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
167 while((irq = cpm2_get_irq(regs)) >= 0)
171 static struct irqaction cpm2_irqaction = {
172 .handler = cpm2_cascade,
173 .flags = SA_INTERRUPT,
174 .mask = CPU_MASK_NONE,
175 .name = "cpm2_cascade",
177 #endif /* CONFIG_CPM2 */
180 mpc85xx_cds_init_IRQ(void)
182 bd_t *binfo = (bd_t *) __res;
184 volatile cpm2_map_t *immap = cpm2_immr;
188 /* Determine the Physical Address of the OpenPIC regs */
189 phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
190 OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
191 OpenPIC_InitSenses = mpc85xx_cds_openpic_initsenses;
192 OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses);
194 /* Skip reserved space and internal sources */
195 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
196 /* Map PIC IRQs 0-11 */
197 openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);
199 /* we let openpic interrupts starting from an offset, to
200 * leave space for cascading interrupts underneath.
202 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
205 /* disable all CPM interupts */
206 immap->im_intctl.ic_simrh = 0x0;
207 immap->im_intctl.ic_simrl = 0x0;
209 for (i = CPM_IRQ_OFFSET; i < (NR_CPM_INTS + CPM_IRQ_OFFSET); i++)
210 irq_desc[i].handler = &cpm2_pic;
212 /* Initialize the default interrupt mapping priorities,
213 * in case the boot rom changed something on us.
215 immap->im_intctl.ic_sicr = 0;
216 immap->im_intctl.ic_scprrh = 0x05309770;
217 immap->im_intctl.ic_scprrl = 0x05309770;
219 setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
230 mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
232 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
236 /* Handle PCI1 interrupts */
237 char pci_irq_table[][4] =
239 * PCI IDSEL/INTPIN->INTLINE
243 /* Note IRQ assignment for slots is based on which slot the elysium is
244 * in -- in this setup elysium is in slot #2 (this PIRQA as first
245 * interrupt on slot */
247 { 0, 1, 2, 3 }, /* 16 - PMC */
248 { 3, 0, 0, 0 }, /* 17 P2P (Tsi320) */
249 { 0, 1, 2, 3 }, /* 18 - Slot 1 */
250 { 1, 2, 3, 0 }, /* 19 - Slot 2 */
251 { 2, 3, 0, 1 }, /* 20 - Slot 3 */
252 { 3, 0, 1, 2 }, /* 21 - Slot 4 */
255 const long min_idsel = 16, max_idsel = 21, irqs_per_slot = 4;
258 for (i = 0; i < 6; i++)
259 for (j = 0; j < 4; j++)
260 pci_irq_table[i][j] =
261 ((pci_irq_table[i][j] + 5 -
262 cds_pci_slot) & 0x3) + PIRQ0A;
264 return PCI_IRQ_TABLE_LOOKUP;
266 /* Handle PCI2 interrupts (if we have one) */
267 char pci_irq_table[][4] =
270 * We only have one slot and one interrupt
271 * going to PIRQA - PIRQD */
272 { PIRQ1A, PIRQ1A, PIRQ1A, PIRQ1A }, /* 21 - slot 0 */
275 const long min_idsel = 21, max_idsel = 21, irqs_per_slot = 4;
277 return PCI_IRQ_TABLE_LOOKUP;
281 #define ARCADIA_HOST_BRIDGE_IDSEL 17
282 #define ARCADIA_2ND_BRIDGE_IDSEL 3
284 extern int mpc85xx_pci1_last_busno;
287 mpc85xx_exclude_device(u_char bus, u_char devfn)
289 if (bus == 0 && PCI_SLOT(devfn) == 0)
290 return PCIBIOS_DEVICE_NOT_FOUND;
291 #ifdef CONFIG_85xx_PCI2
292 if (mpc85xx_pci1_last_busno)
293 if (bus == (mpc85xx_pci1_last_busno + 1) && PCI_SLOT(devfn) == 0)
294 return PCIBIOS_DEVICE_NOT_FOUND;
296 /* We explicitly do not go past the Tundra 320 Bridge */
298 return PCIBIOS_DEVICE_NOT_FOUND;
299 if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
300 return PCIBIOS_DEVICE_NOT_FOUND;
302 return PCIBIOS_SUCCESSFUL;
304 #endif /* CONFIG_PCI */
306 /* ************************************************************************
308 * Setup the architecture
312 mpc85xx_cds_setup_arch(void)
314 bd_t *binfo = (bd_t *) __res;
316 struct gianfar_platform_data *pdata;
318 /* get the core frequency */
319 freq = binfo->bi_intfreq;
321 printk("mpc85xx_cds_setup_arch\n");
327 cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
328 cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
329 printk("CDS Version = %x in PCI slot %d\n", cadmus[CM_VER], cds_pci_slot);
331 /* Set loops_per_jiffy to a half-way reasonable value,
332 for use until calibrate_delay gets called. */
333 loops_per_jiffy = freq / HZ;
336 /* setup PCI host bridges */
337 mpc85xx_setup_hose();
340 #ifdef CONFIG_SERIAL_8250
341 mpc85xx_early_serial_map();
344 #ifdef CONFIG_SERIAL_TEXT_DEBUG
345 /* Invalidate the entry we stole earlier the serial ports
346 * should be properly mapped */
347 invalidate_tlbcam_entry(NUM_TLBCAMS - 1);
350 /* setup the board related information for the enet controllers */
351 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
352 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
353 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
355 /* fixup phy address */
356 pdata->phy_reg_addr += binfo->bi_immr_base;
357 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
359 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
360 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
361 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
363 /* fixup phy address */
364 pdata->phy_reg_addr += binfo->bi_immr_base;
365 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
368 #ifdef CONFIG_BLK_DEV_INITRD
370 ROOT_DEV = Root_RAM0;
373 #ifdef CONFIG_ROOT_NFS
376 ROOT_DEV = Root_HDA1;
380 /* ************************************************************************ */
382 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
383 unsigned long r6, unsigned long r7)
385 /* parse_bootinfo must always be called first */
386 parse_bootinfo(find_bootinfo());
389 * If we were passed in a board information, copy it into the
390 * residual data area.
393 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
397 #ifdef CONFIG_SERIAL_TEXT_DEBUG
399 bd_t *binfo = (bd_t *) __res;
402 /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
403 settlbcam(NUM_TLBCAMS - 1, binfo->bi_immr_base,
404 binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
406 memset(&p, 0, sizeof (p));
407 p.iotype = SERIAL_IO_MEM;
408 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET;
409 p.uartclk = binfo->bi_busfreq;
413 memset(&p, 0, sizeof (p));
414 p.iotype = SERIAL_IO_MEM;
415 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET;
416 p.uartclk = binfo->bi_busfreq;
422 #if defined(CONFIG_BLK_DEV_INITRD)
424 * If the init RAM disk has been configured in, and there's a valid
425 * starting address for it, set it up.
428 initrd_start = r4 + KERNELBASE;
429 initrd_end = r5 + KERNELBASE;
431 #endif /* CONFIG_BLK_DEV_INITRD */
433 /* Copy the kernel command line arguments to a safe place. */
436 *(char *) (r7 + KERNELBASE) = 0;
437 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
440 identify_ppc_sys_by_id(mfspr(SVR));
442 /* setup the PowerPC module struct */
443 ppc_md.setup_arch = mpc85xx_cds_setup_arch;
444 ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo;
446 ppc_md.init_IRQ = mpc85xx_cds_init_IRQ;
447 ppc_md.get_irq = openpic_get_irq;
449 ppc_md.restart = mpc85xx_restart;
450 ppc_md.power_off = mpc85xx_power_off;
451 ppc_md.halt = mpc85xx_halt;
453 ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
455 ppc_md.time_init = NULL;
456 ppc_md.set_rtc_time = NULL;
457 ppc_md.get_rtc_time = NULL;
458 ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
460 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
461 ppc_md.progress = gen550_progress;
462 #endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
465 ppc_md.progress("mpc85xx_cds_init(): exit", 0);