2 * arch/ppc/platforms/chestnut.c
4 * Board setup routines for IBM Chestnut
6 * Author: <source@mvista.com>
8 * <2004> (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
14 #include <linux/config.h>
15 #include <linux/stddef.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/errno.h>
19 #include <linux/reboot.h>
20 #include <linux/kdev_t.h>
21 #include <linux/major.h>
22 #include <linux/blkdev.h>
23 #include <linux/console.h>
24 #include <linux/root_dev.h>
25 #include <linux/initrd.h>
26 #include <linux/delay.h>
27 #include <linux/seq_file.h>
28 #include <linux/ide.h>
29 #include <linux/serial.h>
30 #include <linux/serial_core.h>
31 #include <asm/system.h>
32 #include <asm/pgtable.h>
37 #include <linux/irq.h>
38 #include <asm/hw_irq.h>
39 #include <asm/machdep.h>
41 #include <asm/bootinfo.h>
42 #include <asm/mv64x60.h>
43 #include <platforms/chestnut.h>
45 static u32 boot_base; /* Virtual addr of 8bit boot */
46 static u32 cpld_base; /* Virtual addr of CPLD Regs */
48 static mv64x60_handle_t bh;
50 extern void gen550_progress(char *, unsigned short);
51 extern void gen550_init(int, struct uart_port *);
52 extern void mv64360_pcibios_fixup(mv64x60_handle_t *bh);
55 #define CHESTNUT_PRESERVE_MASK (BIT(MV64x60_CPU2DEV_0_WIN) | \
56 BIT(MV64x60_CPU2DEV_1_WIN) | \
57 BIT(MV64x60_CPU2DEV_2_WIN) | \
58 BIT(MV64x60_CPU2DEV_3_WIN) | \
59 BIT(MV64x60_CPU2BOOT_WIN))
60 /**************************************************************************
61 * FUNCTION: chestnut_calibrate_decr
63 * DESCRIPTION: initialize decrementer interrupt frequency (used as system
68 chestnut_calibrate_decr(void){
71 freq = CHESTNUT_BUS_SPEED / 4;
73 printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
74 freq/1000000, freq%1000000);
76 tb_ticks_per_jiffy = freq / HZ;
77 tb_to_us = mulhwu_scale_factor(freq, 1000000);
83 chestnut_show_cpuinfo(struct seq_file *m)
85 seq_printf(m, "vendor\t\t: IBM\n");
86 seq_printf(m, "machine\t\t: 750FX/GX Eval Board (Chestnut/Buckeye)\n");
91 /**************************************************************************
92 * FUNCTION: chestnut_find_end_of_memory
94 * DESCRIPTION: ppc_md memory size callback
98 chestnut_find_end_of_memory(void)
100 static int mem_size = 0;
103 mem_size = mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
104 MV64x60_TYPE_MV64460);
109 #if defined(CONFIG_SERIAL_8250)
111 chestnut_early_serial_map(void)
113 struct uart_port port;
115 /* Setup serial port access */
116 memset(&port, 0, sizeof(port));
117 port.uartclk = BASE_BAUD * 16;
118 port.irq = UART0_INT;
119 port.flags = STD_COM_FLAGS | UPF_IOREMAP;
120 port.iotype = SERIAL_IO_MEM;
121 port.mapbase = CHESTNUT_UART0_IO_BASE;
124 if (early_serial_setup(&port) != 0)
125 printk("Early serial init of port 0 failed\n");
127 /* Assume early_serial_setup() doesn't modify serial_req */
129 port.irq = UART1_INT;
130 port.mapbase = CHESTNUT_UART1_IO_BASE;
132 if (early_serial_setup(&port) != 0)
133 printk("Early serial init of port 1 failed\n");
137 /**************************************************************************
138 * FUNCTION: chestnut_map_irq
140 * DESCRIPTION: 0 return since PCI IRQs not needed
144 chestnut_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
146 static char pci_irq_table[][4] = {
147 {CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ,
148 CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ},
149 {CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ,
150 CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ},
151 {CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ,
152 CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ},
153 {CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ,
154 CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ},
156 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
158 return (PCI_IRQ_TABLE_LOOKUP);
162 /**************************************************************************
163 * FUNCTION: chestnut_setup_bridge
165 * DESCRIPTION: initalize board-specific settings on the MV64360
169 chestnut_setup_bridge(void)
171 struct mv64x60_setup_info si;
174 if ( ppc_md.progress )
175 ppc_md.progress("chestnut_setup_bridge: enter", 0);
177 memset(&si, 0, sizeof(si));
179 si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
181 /* setup only PCI bus 0 (bus 1 not used) */
182 si.pci_0.enable_bus = 1;
183 si.pci_0.pci_io.cpu_base = CHESTNUT_PCI0_IO_PROC_ADDR;
184 si.pci_0.pci_io.pci_base_hi = 0;
185 si.pci_0.pci_io.pci_base_lo = CHESTNUT_PCI0_IO_PCI_ADDR;
186 si.pci_0.pci_io.size = CHESTNUT_PCI0_IO_SIZE;
187 si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
188 si.pci_0.pci_mem[0].cpu_base = CHESTNUT_PCI0_MEM_PROC_ADDR;
189 si.pci_0.pci_mem[0].pci_base_hi = CHESTNUT_PCI0_MEM_PCI_HI_ADDR;
190 si.pci_0.pci_mem[0].pci_base_lo = CHESTNUT_PCI0_MEM_PCI_LO_ADDR;
191 si.pci_0.pci_mem[0].size = CHESTNUT_PCI0_MEM_SIZE;
192 si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
193 si.pci_0.pci_cmd_bits = 0;
194 si.pci_0.latency_timer = 0x80;
196 si.window_preserve_mask_32_lo = CHESTNUT_PRESERVE_MASK;
198 for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
199 si.cpu_prot_options[i] = 0;
200 #ifdef CONFIG_NOT_CACHE_COHERENT
201 si.cpu_snoop_options[i] = MV64360_CPU_SNOOP_NONE;
203 si.cpu_snoop_options[i] = MV64360_CPU_SNOOP_WB; /* risky */
205 si.pci_0.acc_cntl_options[i] =
206 #ifdef CONFIG_NOT_CACHE_COHERENT
207 MV64360_PCI_ACC_CNTL_SNOOP_NONE |
209 MV64360_PCI_ACC_CNTL_SNOOP_WB | /* risky */
211 MV64360_PCI_ACC_CNTL_SWAP_NONE |
212 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
213 MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
216 /* Lookup host bridge - on CPU 0 - no SMP support */
217 if (mv64x60_init(&bh, &si)) {
218 printk("\n\nPCI Bridge initialization failed!\n");
222 ppc_md.pci_swizzle = common_swizzle;
223 ppc_md.pci_map_irq = chestnut_map_irq;
224 ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
226 mv64x60_set_bus(&bh, 0, 0);
227 bh.hose_a->first_busno = 0;
228 bh.hose_a->last_busno = 0xff;
229 bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
234 chestnut_setup_peripherals(void)
237 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
238 CHESTNUT_BOOT_8BIT_BASE, CHESTNUT_BOOT_8BIT_SIZE, 0);
240 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
241 CHESTNUT_32BIT_BASE, CHESTNUT_32BIT_SIZE, 0);
242 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
243 CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE, 0);
245 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
246 CHESTNUT_UART_BASE, CHESTNUT_UART_SIZE, 0);
247 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
248 CHESTNUT_FRAM_BASE, CHESTNUT_FRAM_SIZE, 0);
249 /* Set up window for internal sram (256KByte insize) */
250 mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
251 CHESTNUT_INTERNAL_SRAM_BASE,
252 CHESTNUT_INTERNAL_SRAM_SIZE, 0);
254 boot_base = (u32)ioremap(CHESTNUT_BOOT_8BIT_BASE,
255 CHESTNUT_BOOT_8BIT_SIZE);
256 cpld_base = (u32)ioremap(CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE);
259 * Configure internal SRAM -
260 * Cache coherent write back, incase
261 * CONFIG_MV64360_SRAM_CACHE_COHERENT set
263 * Parity error propagation
264 * Arbitration not parked for CPU only
265 * Other bits are reserved.
267 #ifdef CONFIG_MV64360_SRAM_CACHE_COHERENT
268 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
270 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0);
274 * Setting the SRAM to 0. Note that this generates parity errors on
275 * internal data path in SRAM since it's first time accessing it
276 * while after reset it's not configured
278 memset((void *)CHESTNUT_INTERNAL_SRAM_BASE, 0, CHESTNUT_INTERNAL_SRAM_SIZE);
280 * Configure MPP pins for PCI DMA
282 * PCI Slot GNT pin REQ pin
288 mv64x60_write(&bh, MV64x60_MPP_CNTL_2,
289 (0x1 << 0) | /* MPPSel16 PCI0_GNT[0] */
290 (0x1 << 4) | /* MPPSel17 PCI0_REQ[0] */
291 (0x1 << 8) | /* MPPSel18 PCI0_GNT[1] */
292 (0x1 << 12) | /* MPPSel19 PCI0_REQ[1] */
293 (0x1 << 16) | /* MPPSel20 PCI0_GNT[2] */
294 (0x1 << 20) | /* MPPSel21 PCI0_REQ[2] */
295 (0x1 << 24) | /* MPPSel22 PCI0_GNT[3] */
296 (0x1 << 28)); /* MPPSel23 PCI0_REQ[3] */
298 * Set unused MPP pins for output, as per schematic note
300 * Unused Pins: MPP01, MPP02, MPP04, MPP05, MPP06
301 * MPP09, MPP10, MPP13, MPP14, MPP15
303 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_0,
304 (0xf << 4) | /* MPPSel01 GPIO[1] */
305 (0xf << 8) | /* MPPSel02 GPIO[2] */
306 (0xf << 16) | /* MPPSel04 GPIO[4] */
307 (0xf << 20) | /* MPPSel05 GPIO[5] */
308 (0xf << 24)); /* MPPSel06 GPIO[6] */
309 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1,
310 (0xf << 4) | /* MPPSel09 GPIO[9] */
311 (0xf << 8) | /* MPPSel10 GPIO[10] */
312 (0xf << 20) | /* MPPSel13 GPIO[13] */
313 (0xf << 24) | /* MPPSel14 GPIO[14] */
314 (0xf << 28)); /* MPPSel15 GPIO[15] */
315 mv64x60_set_bits(&bh, MV64x60_GPP_IO_CNTL,
316 BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(6) |
317 BIT(9) | BIT(10) | BIT(13) | BIT(14) | BIT(15)); /* Output */
320 * Configure the following MPP pins to indicate a level
321 * triggered interrupt
323 * MPP24 - Board Reset (just map the MPP & GPP for chestnut_reset)
324 * MPP25 - UART A (high)
325 * MPP26 - UART B (high)
326 * MPP28 - PCI Slot 3 (low)
327 * MPP29 - PCI Slot 2 (low)
328 * MPP30 - PCI Slot 1 (low)
329 * MPP31 - PCI Slot 0 (low)
331 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3,
332 BIT(3) | BIT(2) | BIT(1) | BIT(0) | /* MPP 24 */
333 BIT(7) | BIT(6) | BIT(5) | BIT(4) | /* MPP 25 */
334 BIT(11) | BIT(10) | BIT(9) | BIT(8) | /* MPP 26 */
335 BIT(19) | BIT(18) | BIT(17) | BIT(16) | /* MPP 28 */
336 BIT(23) | BIT(22) | BIT(21) | BIT(20) | /* MPP 29 */
337 BIT(27) | BIT(26) | BIT(25) | BIT(24) | /* MPP 30 */
338 BIT(31) | BIT(30) | BIT(29) | BIT(28)); /* MPP 31 */
341 * Define GPP 25 (high), 26 (high), 28 (low), 29 (low), 30 (low),
342 * 31 (low) interrupt polarity input signal and level triggered
344 mv64x60_clr_bits(&bh, MV64x60_GPP_LEVEL_CNTL, BIT(25) | BIT(26));
345 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL,
346 BIT(28) | BIT(29) | BIT(30) | BIT(31));
347 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL,
348 BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
351 /* Config GPP interrupt controller to respond to level trigger */
352 mv64x60_set_bits(&bh, MV64360_COMM_ARBITER_CNTL, BIT(10));
355 * Dismiss and then enable interrupt on GPP interrupt cause for CPU #0
357 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE,
358 ~(BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
360 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK,
361 BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
365 * Dismiss and then enable interrupt on CPU #0 high cause register
366 * BIT27 summarizes GPP interrupts 24-31
368 mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, BIT(27));
371 ppc_md.progress("chestnut_setup_bridge: exit", 0);
374 /**************************************************************************
375 * FUNCTION: chestnut_setup_arch
377 * DESCRIPTION: ppc_md machine configuration callback
381 chestnut_setup_arch(void)
384 ppc_md.progress("chestnut_setup_arch: enter", 0);
386 /* init to some ~sane value until calibrate_delay() runs */
387 loops_per_jiffy = 50000000 / HZ;
389 /* if the time base value is greater than bus freq/4 (the TB and
390 * decrementer tick rate) + signed integer rollover value, we
391 * can spend a fair amount of time waiting for the rollover to
392 * happen. To get around this, initialize the time base register
397 #ifdef CONFIG_BLK_DEV_INITRD
399 ROOT_DEV = Root_RAM0;
402 #ifdef CONFIG_ROOT_NFS
405 ROOT_DEV = Root_SDA2;
409 * Set up the L2CR register.
411 _set_L2CR(_get_L2CR() | L2CR_L2E);
413 chestnut_setup_bridge();
414 chestnut_setup_peripherals();
416 #ifdef CONFIG_DUMMY_CONSOLE
417 conswitchp = &dummy_con;
420 #if defined(CONFIG_SERIAL_8250)
421 chestnut_early_serial_map();
424 /* Identify the system */
425 printk(KERN_INFO "System Identification: IBM 750FX/GX Eval Board\n");
426 printk(KERN_INFO "IBM 750FX/GX port (C) 2004 MontaVista Software, Inc. (source@mvista.com)\n");
429 ppc_md.progress("chestnut_setup_arch: exit", 0);
434 /**************************************************************************
435 * FUNCTION: chestnut_restart
437 * DESCRIPTION: ppc_md machine reset callback
438 * reset the board via the CPLD command register
442 chestnut_restart(char *cmd)
444 volatile ulong i = 10000000;
449 * Set CPLD Reg 3 bit 0 to 1 to allow MPP signals on reset to work
451 * MPP24 - board reset
453 writeb(0x1, (void __iomem *)(cpld_base+3));
455 /* GPP pin tied to MPP earlier */
456 mv64x60_set_bits(&bh, MV64x60_GPP_VALUE_SET, BIT(24));
459 panic("restart failed\n");
471 chestnut_power_off(void)
477 #define SET_PCI_COMMAND_INVALIDATE
478 #ifdef SET_PCI_COMMAND_INVALIDATE
480 * Dave Wilhardt found that PCI_COMMAND_INVALIDATE must
481 * be set for each device if you are using cache coherency.
484 set_pci_command_invalidate(void)
486 struct pci_dev *dev = NULL;
489 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
490 pci_read_config_word(dev, PCI_COMMAND, &val);
491 val |= PCI_COMMAND_INVALIDATE;
492 pci_write_config_word(dev, PCI_COMMAND, val);
494 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
495 L1_CACHE_LINE_SIZE >> 2);
501 chestnut_pci_fixups(void)
503 #ifdef SET_PCI_COMMAND_INVALIDATE
504 set_pci_command_invalidate();
508 /**************************************************************************
509 * FUNCTION: chestnut_map_io
511 * DESCRIPTION: configure fixed memory-mapped IO
515 chestnut_map_io(void)
517 #ifdef CONFIG_MV64360_SRAM_CACHEABLE
518 io_block_mapping(CHESTNUT_INTERNAL_SRAM_BASE,
519 CHESTNUT_INTERNAL_SRAM_BASE,
520 CHESTNUT_INTERNAL_SRAM_SIZE,
521 _PAGE_KERNEL | _PAGE_GUARDED);
523 #ifdef CONFIG_MV64360_SRAM_CACHE_COHERENT
524 io_block_mapping(CHESTNUT_INTERNAL_SRAM_BASE,
525 CHESTNUT_INTERNAL_SRAM_BASE,
526 CHESTNUT_INTERNAL_SRAM_SIZE,
527 _PAGE_KERNEL | _PAGE_GUARDED | _PAGE_COHERENT);
529 io_block_mapping(CHESTNUT_INTERNAL_SRAM_BASE,
530 CHESTNUT_INTERNAL_SRAM_BASE,
531 CHESTNUT_INTERNAL_SRAM_SIZE,
533 #endif /* !CONFIG_MV64360_SRAM_CACHE_COHERENT */
534 #endif /* !CONFIG_MV64360_SRAM_CACHEABLE */
536 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
537 io_block_mapping(CHESTNUT_UART_BASE, CHESTNUT_UART_BASE, 0x100000, _PAGE_IO);
541 /**************************************************************************
542 * FUNCTION: chestnut_set_bat
544 * DESCRIPTION: configures a (temporary) bat mapping for early access to
548 static __inline__ void
549 chestnut_set_bat(void)
552 mtspr(DBAT3U, 0xf0001ffe);
553 mtspr(DBAT3L, 0xf000002a);
559 /**************************************************************************
560 * FUNCTION: platform_init
562 * DESCRIPTION: main entry point for configuring board-specific machine
567 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
568 unsigned long r6, unsigned long r7)
570 parse_bootinfo(find_bootinfo());
572 /* Copy the kernel command line arguments to a safe place. */
575 *(char *) (r7 + KERNELBASE) = 0;
576 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
581 ppc_md.setup_arch = chestnut_setup_arch;
582 ppc_md.show_cpuinfo = chestnut_show_cpuinfo;
583 ppc_md.irq_canonicalize = NULL;
584 ppc_md.init_IRQ = mv64360_init_irq;
585 ppc_md.get_irq = mv64360_get_irq;
588 ppc_md.find_end_of_memory = chestnut_find_end_of_memory;
589 ppc_md.setup_io_mappings = chestnut_map_io;
590 ppc_md.pcibios_fixup = chestnut_pci_fixups;
592 ppc_md.restart = chestnut_restart;
593 ppc_md.power_off = chestnut_power_off;
594 ppc_md.halt = chestnut_halt;
596 ppc_md.time_init = NULL;
597 ppc_md.set_rtc_time = NULL;
598 ppc_md.get_rtc_time = NULL;
599 ppc_md.calibrate_decr = chestnut_calibrate_decr;
601 ppc_md.nvram_read_val = NULL;
602 ppc_md.nvram_write_val = NULL;
604 ppc_md.heartbeat = NULL;
606 ppc_md.pcibios_fixup = chestnut_pci_fixups;
608 bh.p_base = CONFIG_MV64X60_NEW_BASE;
612 #if defined(CONFIG_SERIAL_TEXT_DEBUG)
613 ppc_md.progress = gen550_progress;
615 #if defined(CONFIG_KGDB)
616 ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
620 ppc_md.progress("chestnut_init(): exit", 0);