2 * arch/ppc/platforms/ev64260.c
4 * Board setup routines for the Marvell/Galileo EV-64260-BP Evaluation Board.
6 * Author: Mark A. Greer <mgreer@mvista.com>
8 * 2001-2003 (c) MontaVista, Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
15 * The EV-64260-BP port is the result of hard work from many people from
16 * many companies. In particular, employees of Marvell/Galileo, Mission
17 * Critical Linux, Xyterra, and MontaVista Software were heavily involved.
19 * Note: I have not been able to get *all* PCI slots to work reliably
20 * at 66 MHz. I recommend setting jumpers J15 & J16 to short pins 1&2
21 * so that 33 MHz is used. --MAG
22 * Note: The 750CXe and 7450 are not stable with a 125MHz or 133MHz TCLK/SYSCLK.
23 * At 100MHz, they are solid.
25 #include <linux/config.h>
27 #include <linux/delay.h>
28 #include <linux/pci.h>
29 #include <linux/ide.h>
30 #include <linux/irq.h>
32 #include <linux/seq_file.h>
33 #include <linux/console.h>
34 #include <linux/initrd.h>
35 #include <linux/root_dev.h>
36 #if !defined(CONFIG_SERIAL_MPSC_CONSOLE)
37 #include <linux/serial.h>
38 #include <linux/tty.h>
39 #include <linux/serial_core.h>
41 #include <asm/bootinfo.h>
42 #include <asm/machdep.h>
43 #include <asm/mv64x60.h>
44 #include <asm/ppcboot.h>
49 #include <platforms/ev64260.h>
51 #define BOARD_VENDOR "Marvell/Galileo"
52 #define BOARD_MACHINE "EV-64260-BP"
54 /* Set IDE controllers into Native mode? */
56 #define SET_PCI_IDE_NATIVE
59 ulong ev64260_mem_size = 0;
61 int ppcboot_bd_valid=0;
63 static mv64x60_handle_t bh;
65 #if !defined(CONFIG_SERIAL_MPSC_CONSOLE)
66 extern void gen550_progress(char *, unsigned short);
67 extern void gen550_init(int, struct serial_struct *);
70 static const unsigned int cpu_7xx[16] = { /* 7xx & 74xx (but not 745x) */
71 18, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0
73 static const unsigned int cpu_745x[2][16] = { /* PLL_EXT 0 & 1 */
74 { 1, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0 },
75 { 0, 30, 0, 2, 0, 26, 0, 18, 0, 22, 20, 24, 28, 32, 0, 0 }
82 ev64260_get_bus_speed(void)
86 if (ppcboot_bd_valid) {
87 speed = ppcboot_bd.bi_busfreq;
90 speed = 100000000; /* Only 100MHz is stable */
97 ev64260_get_cpu_speed(void)
99 unsigned long pvr, hid1, pll_ext;
101 pvr = PVR_VER(mfspr(PVR));
103 if (pvr != PVR_VER(PVR_7450)) {
104 hid1 = mfspr(HID1) >> 28;
105 return ev64260_get_bus_speed() * cpu_7xx[hid1]/2;
108 hid1 = (mfspr(HID1) & 0x0001e000) >> 13;
109 pll_ext = 0; /* No way to read; must get from schematic */
110 return ev64260_get_bus_speed() * cpu_745x[pll_ext][hid1]/2;
115 ev64260_find_end_of_memory(void)
117 if(!ppcboot_bd_valid) {
118 return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
119 MV64x60_TYPE_GT64260A);
121 return ppcboot_bd.bi_memsize;
125 #ifdef SET_PCI_IDE_NATIVE
127 set_pci_native_mode(void)
131 /* Better way of doing this ??? */
132 pci_for_each_dev(dev) {
133 int class = dev->class >> 8;
135 /* enable pci native mode */
136 if (class == PCI_CLASS_STORAGE_IDE) {
139 pci_read_config_byte(dev, 0x9, ®);
141 printk("PCI: Enabling PCI IDE native mode on %s\n", dev->slot_name);
142 pci_write_config_byte(dev, 0x9, 0x8f);
144 /* let the pci code set this device up after we change it */
145 pci_setup_device(dev);
146 } else if (reg != 0x8f) {
147 printk("PCI: IDE chip in unknown mode 0x%02x on %s", reg, dev->slot_name);
156 ev64260_pci_fixups(void)
158 #ifdef SET_PCI_IDE_NATIVE
159 set_pci_native_mode();
165 * Marvell/Galileo EV-64260-BP Evaluation Board PCI interrupt routing.
166 * Note: By playing with J8 and JP1-4, you can get 2 IRQ's from the first
167 * PCI bus (in which cast, INTPIN B would be EV64260_PCI_1_IRQ).
168 * This is the most IRQs you can get from one bus with this board, though.
171 ev64260_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
173 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
175 if (hose->index == 0) {
176 static char pci_irq_table[][4] =
178 * PCI IDSEL/INTPIN->INTLINE
182 {EV64260_PCI_0_IRQ,0,0,0}, /* IDSEL 7 - PCI bus 0 */
183 {EV64260_PCI_0_IRQ,0,0,0}, /* IDSEL 8 - PCI bus 0 */
186 const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4;
187 return PCI_IRQ_TABLE_LOOKUP;
190 static char pci_irq_table[][4] =
192 * PCI IDSEL/INTPIN->INTLINE
196 { EV64260_PCI_1_IRQ,0,0,0}, /* IDSEL 7 - PCI bus 1 */
197 { EV64260_PCI_1_IRQ,0,0,0}, /* IDSEL 8 - PCI bus 1 */
200 const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4;
201 return PCI_IRQ_TABLE_LOOKUP;
206 ev64260_setup_peripherals(void)
208 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
209 EV64260_EMB_FLASH_BASE, EV64260_EMB_FLASH_SIZE, 0);
210 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
211 EV64260_EXT_SRAM_BASE, EV64260_EXT_SRAM_SIZE, 0);
212 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
213 EV64260_TODC_BASE, EV64260_TODC_SIZE, 0);
214 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
215 EV64260_UART_BASE, EV64260_UART_SIZE, 0);
216 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
217 EV64260_EXT_FLASH_BASE, EV64260_EXT_FLASH_SIZE, 0);
219 TODC_INIT(TODC_TYPE_DS1501, 0, 0,
220 ioremap(EV64260_TODC_BASE, EV64260_TODC_SIZE), 8);
222 mv64x60_clr_bits(&bh, MV64x60_CPU_CONFIG, ((1<<28) | (1<<29)));
223 mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1<<27));
225 if (ev64260_get_bus_speed() > 100000000) {
226 mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1<<23));
229 mv64x60_set_bits(&bh, MV64x60_PCI0_PCI_DECODE_CNTL,((1<<0) | (1<<3)));
230 mv64x60_set_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL,((1<<0) | (1<<3)));
233 * Enabling of PCI internal-vs-external arbitration
234 * is a platform- and errata-dependent decision.
236 if (bh.type == MV64x60_TYPE_GT64260A ) {
237 mv64x60_set_bits(&bh, MV64x60_PCI0_ARBITER_CNTL, (1<<31));
238 mv64x60_set_bits(&bh, MV64x60_PCI1_ARBITER_CNTL, (1<<31));
241 mv64x60_set_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1<<9)); /* Only 1 cpu */
244 * The EV-64260-BP uses several Multi-Purpose Pins (MPP) on the 64260
245 * bridge as interrupt inputs (via the General Purpose Ports (GPP)
246 * register). Need to route the MPP inputs to the GPP and set the
247 * polarity correctly.
249 * In MPP Control 2 Register
250 * MPP 21 -> GPP 21 (DUART channel A intr) bits 20-23 -> 0
251 * MPP 22 -> GPP 22 (DUART channel B intr) bits 24-27 -> 0
253 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_2, (0xf<<20) | (0xf<<24) );
256 * In MPP Control 3 Register
257 * MPP 26 -> GPP 26 (RTC INT) bits 8-11 -> 0
258 * MPP 27 -> GPP 27 (PCI 0 INTA) bits 12-15 -> 0
259 * MPP 29 -> GPP 29 (PCI 1 INTA) bits 20-23 -> 0
261 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3,
262 (0xf<<8) | (0xf<<12) | (0xf<<20));
264 #define GPP_EXTERNAL_INTERRUPTS \
265 ((1<<21) | (1<<22) | (1<<26) | (1<<27) | (1<<29))
266 /* DUART & PCI interrupts are inputs */
267 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, GPP_EXTERNAL_INTERRUPTS);
268 /* DUART & PCI interrupts are active low */
269 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, GPP_EXTERNAL_INTERRUPTS);
271 /* Clear any pending interrupts for these inputs and enable them. */
272 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~GPP_EXTERNAL_INTERRUPTS);
273 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, GPP_EXTERNAL_INTERRUPTS);
276 * Set MPSC Multiplex RMII
277 * NOTE: ethernet driver modifies bit 0 and 1
279 mv64x60_write(&bh, GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
285 ev64260_setup_bridge(void)
287 mv64x60_setup_info_t si;
290 memset(&si, 0, sizeof(si));
292 si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
293 si.map_irq = ev64260_map_irq;
295 si.pci_0.enable_bus = 1;
296 si.pci_0.enumerate_bus = 1;
297 si.pci_0.pci_io.cpu_base = 0xa0000000;
298 si.pci_0.pci_io.pci_base_hi = 0;
299 si.pci_0.pci_io.pci_base_lo = 0;
300 si.pci_0.pci_io.size = 0x01000000;
301 si.pci_0.pci_io.swap = 0x01000000; /* XXXX No swapping */
302 si.pci_0.pci_mem[0].cpu_base = 0x80000000;
303 si.pci_0.pci_mem[0].pci_base_hi = 0;
304 si.pci_0.pci_mem[0].pci_base_lo = 0x80000000;
305 si.pci_0.pci_mem[0].size = 0x10000000;
306 si.pci_0.pci_mem[0].swap = 0x01000000; /* XXXX No swapping */
307 si.pci_0.pci_mem[1].cpu_base = 0;
308 si.pci_0.pci_mem[1].pci_base_hi = 0;
309 si.pci_0.pci_mem[1].pci_base_lo = 0;
310 si.pci_0.pci_mem[1].size = 0; /* Don't use this window */
311 si.pci_0.pci_mem[1].swap = 0;
312 si.pci_0.pci_mem[2].cpu_base = 0;
313 si.pci_0.pci_mem[2].pci_base_hi = 0;
314 si.pci_0.pci_mem[2].pci_base_lo = 0;
315 si.pci_0.pci_mem[2].size = 0; /* Don't use this window */
316 si.pci_0.pci_mem[1].swap = 0;
317 si.pci_0.pci_cmd_bits = 0;
318 si.pci_0.latency_timer = 0x8;
320 si.pci_1.enable_bus = 1;
321 si.pci_1.enumerate_bus = 1;
322 si.pci_1.pci_io.cpu_base = 0xa1000000;
323 si.pci_1.pci_io.pci_base_hi = 0;
324 si.pci_1.pci_io.pci_base_lo = 0x01000000;
325 si.pci_1.pci_io.size = 0x01000000;
326 si.pci_1.pci_io.swap = 0x01000000; /* XXXX No swapping */
327 si.pci_1.pci_mem[0].cpu_base = 0x90000000;
328 si.pci_1.pci_mem[0].pci_base_hi = 0;
329 si.pci_1.pci_mem[0].pci_base_lo = 0x90000000;
330 si.pci_1.pci_mem[0].size = 0x10000000;
331 si.pci_1.pci_mem[0].swap = 0x01000000; /* XXXX No swapping */
332 si.pci_1.pci_mem[1].cpu_base = 0;
333 si.pci_1.pci_mem[1].pci_base_hi = 0;
334 si.pci_1.pci_mem[1].pci_base_lo = 0;
335 si.pci_1.pci_mem[1].size = 0; /* Don't use this window */
336 si.pci_1.pci_mem[1].swap = 0;
337 si.pci_1.pci_mem[2].cpu_base = 0;
338 si.pci_1.pci_mem[2].pci_base_hi = 0;
339 si.pci_1.pci_mem[2].pci_base_lo = 0;
340 si.pci_1.pci_mem[2].size = 0; /* Don't use this window */
341 si.pci_1.pci_mem[1].swap = 0;
342 si.pci_1.pci_cmd_bits = 0;
343 si.pci_1.latency_timer = 0x8;
344 si.pci_1.pci_cmd_bits = 0;
345 si.pci_1.latency_timer = 0x8;
347 for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
348 si.cpu_prot_options[i] = 0;
349 si.cpu_snoop_options[i] = GT64260_CPU_SNOOP_WB;
350 si.pci_0.acc_cntl_options[i] =
351 /* Breaks PCI (especially slot 4)
352 GT64260_PCI_ACC_CNTL_PREFETCHEN |
354 GT64260_PCI_ACC_CNTL_DREADEN |
355 GT64260_PCI_ACC_CNTL_RDPREFETCH |
356 GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
357 GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
358 GT64260_PCI_ACC_CNTL_SWAP_NONE |
359 GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
360 si.pci_0.snoop_options[i] = GT64260_PCI_SNOOP_WB;
361 si.pci_1.acc_cntl_options[i] =
362 /* Breaks PCI (especially slot 4)
363 GT64260_PCI_ACC_CNTL_PREFETCHEN |
365 GT64260_PCI_ACC_CNTL_DREADEN |
366 GT64260_PCI_ACC_CNTL_RDPREFETCH |
367 GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
368 GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
369 GT64260_PCI_ACC_CNTL_SWAP_NONE |
370 GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
371 si.pci_1.snoop_options[i] = GT64260_PCI_SNOOP_WB;
374 /* Lookup PCI host bridges */
375 if (mv64x60_init(&bh, &si)) {
376 printk("Bridge initialization failed.\n");
382 #if defined(CONFIG_SERIAL_8250) && !defined(CONFIG_SERIAL_MPSC_CONSOLE)
384 ev64260_early_serial_map(void)
386 struct uart_port port;
387 static char first_time = 1;
390 memset(&port, 0, sizeof(port));
392 port.membase = ioremap(EV64260_SERIAL_0, EV64260_UART_SIZE);
393 port.irq = EV64260_UART_0_IRQ;
394 port.uartclk = BASE_BAUD * 16;
396 port.iotype = SERIAL_IO_MEM;
397 port.flags = STD_COM_FLAGS;
399 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
400 gen550_init(0, &port);
403 if (early_serial_setup(&port) != 0) {
404 printk("Early serial init of port 0 failed\n");
408 /* Assume early_serial_setup() doesn't modify port */
409 port.membase = ioremap(EV64260_SERIAL_1, EV64260_UART_SIZE);
410 port.irq = EV64260_UART_1_IRQ;
412 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
413 gen550_init(1, &port);
416 if (early_serial_setup(&port) != 0) {
417 printk("Early serial init of port 1 failed\n");
426 #elif defined(CONFIG_SERIAL_MPSC_CONSOLE)
428 ev64260_early_serial_map(void)
431 static char first_time = 1;
434 #if defined(CONFIG_KGDB_TTYS0)
436 #elif defined(CONFIG_KGDB_TTYS1)
439 #error "Invalid kgdb_tty port"
443 gt_early_mpsc_init(KGDB_PORT, B9600|CS8|CREAD|HUPCL|CLOCAL);
453 ev64260_fixup_ocp(void)
455 #if defined(CONFIG_SERIAL_MPSC)
456 struct ocp_device *dev;
457 mv64x60_ocp_mpsc_data_t *dp;
459 if ((dev = ocp_find_device(OCP_VENDOR_MARVELL, OCP_FUNC_MPSC, 0))
461 dp = (mv64x60_ocp_mpsc_data_t *)dev->def->additions;
463 dp->max_idle = 40; /* XXXX what should this be? */
464 dp->default_baud = EV64260_DEFAULT_BAUD;
465 dp->brg_clk_src = EV64260_MPSC_CLK_SRC;
466 dp->brg_clk_freq = EV64260_MPSC_CLK_FREQ;
469 if ((dev = ocp_find_device(OCP_VENDOR_MARVELL, OCP_FUNC_MPSC, 1))
471 dp = (mv64x60_ocp_mpsc_data_t *)dev->def->additions;
473 dp->max_idle = 40; /* XXXX what should this be? */
474 dp->default_baud = 9600; /* XXXX */
475 dp->brg_clk_src = EV64260_MPSC_CLK_SRC;
476 dp->brg_clk_freq = EV64260_MPSC_CLK_FREQ;
484 ev64260_setup_arch(void)
486 if ( ppc_md.progress )
487 ppc_md.progress("ev64260_setup_arch: enter", 0);
489 #ifdef CONFIG_BLK_DEV_INITRD
491 ROOT_DEV = Root_RAM0;
494 #ifdef CONFIG_ROOT_NFS
497 ROOT_DEV = Root_SDA2;
500 if ( ppc_md.progress )
501 ppc_md.progress("ev64260_setup_arch: Enabling L2 cache", 0);
503 /* Enable L2 and L3 caches (if 745x) */
504 _set_L2CR(_get_L2CR() | L2CR_L2E);
505 _set_L3CR(_get_L3CR() | L3CR_L3E);
507 if ( ppc_md.progress )
508 ppc_md.progress("ev64260_setup_arch: Initializing bridge", 0);
510 ev64260_setup_bridge(); /* set up PCI bridge(s) */
511 ev64260_setup_peripherals(); /* set up chip selects/GPP/MPP etc */
513 if ( ppc_md.progress )
514 ppc_md.progress("ev64260_setup_arch: bridge init complete", 0);
516 /* Set OCP values to reflect this board's setup */
519 #ifdef CONFIG_DUMMY_CONSOLE
520 conswitchp = &dummy_con;
522 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_MPSC_CONSOLE)
523 ev64260_early_serial_map();
526 printk(BOARD_VENDOR " " BOARD_MACHINE "\n");
527 printk("EV-64260-BP port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n");
529 if ( ppc_md.progress )
530 ppc_md.progress("ev64260_setup_arch: exit", 0);
536 ev64260_reset_board(void *addr)
540 /* disable and invalidate the L2 cache */
544 /* flush and disable L1 I/D cache */
558 /* unmap any other random cs's that might overlap with bootcs */
559 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, 0, 0, 0);
560 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, 0, 0, 0);
561 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, 0, 0, 0);
562 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, 0, 0, 0);
564 /* map bootrom back in to gt @ reset defaults */
565 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
566 0xff800000, 8*1024*1024, 0);
568 /* move gt reg base back to default, setup default pci0 swapping
570 mv64x60_write(&bh, MV64x60_INTERNAL_SPACE_DECODE,
571 (1<<24) | MV64x60_INTERNAL_SPACE_DEFAULT_ADDR>>20);
573 /* NOTE: FROM NOW ON no more GT_REGS accesses.. 0x1 is not mapped
574 * via BAT or MMU, and MSR IR/DR is ON */
576 /* BROKEN... IR/DR is still on !! won't work!! */
577 /* Set exception prefix high - to the firmware */
578 _nmask_and_or_msr(0, MSR_IP);
580 out_8((u_char *)EV64260_BOARD_MODRST_REG, 0x01);
582 /* SRR0 has system reset vector, SRR1 has default MSR value */
583 /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
584 /* NOTE: assumes reset vector is at 0xfff00100 */
596 ev64260_restart(char *cmd)
598 volatile ulong i = 10000000;
600 ev64260_reset_board((void *)0xfff00100);
603 panic("restart failed\n");
615 ev64260_power_off(void)
622 ev64260_show_cpuinfo(struct seq_file *m)
627 seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
628 seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
629 seq_printf(m, "cpu MHz\t\t: %d\n", ev64260_get_cpu_speed()/1000/1000);
630 seq_printf(m, "bus MHz\t\t: %d\n", ev64260_get_bus_speed()/1000/1000);
635 /* DS1501 RTC has too much variation to use RTC for calibration */
637 ev64260_calibrate_decr(void)
641 freq = ev64260_get_bus_speed()/4;
643 printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
644 freq/1000000, freq%1000000);
646 tb_ticks_per_jiffy = freq / HZ;
647 tb_to_us = mulhwu_scale_factor(freq, 1000000);
653 #ifdef CONFIG_USE_PPCBOOT
654 static void parse_ppcbootinfo(unsigned long r3,
655 unsigned long r4, unsigned long r5,
656 unsigned long r6, unsigned long r7)
659 char *cmdline_start=NULL;
663 if((r3 & 0xf0000000) == 0) r3 += KERNELBASE;
664 if((r3 & 0xf0000000) == KERNELBASE) {
667 /* hack for ppcboot loaders that report freqs in Mhz */
668 if(bd->bi_intfreq<1000000) bd->bi_intfreq*=1000000;
669 if(bd->bi_busfreq<1000000) bd->bi_busfreq*=1000000;
671 memcpy(&ppcboot_bd,bd,sizeof(ppcboot_bd));
676 #ifdef CONFIG_BLK_DEV_INITRD
677 if(r4 && r5 && r5>r4) {
678 if((r4 & 0xf0000000) == 0) r4 += KERNELBASE;
679 if((r5 & 0xf0000000) == 0) r5 += KERNELBASE;
680 if((r4 & 0xf0000000) == KERNELBASE) {
683 initrd_below_start_ok = 1;
686 #endif /* CONFIG_BLK_DEV_INITRD */
688 if(r6 && r7 && r7>r6) {
689 if((r6 & 0xf0000000) == 0) r6 += KERNELBASE;
690 if((r7 & 0xf0000000) == 0) r7 += KERNELBASE;
691 if((r6 & 0xf0000000) == KERNELBASE) {
692 cmdline_start=(void *)r6;
694 strncpy(cmd_line,cmdline_start,cmdline_len);
698 if(ppcboot_bd_valid) {
699 printk("found bd_t @%p\n", bd);
700 printk("memstart=%08lx\n", bd->bi_memstart);
701 printk("memsize=%08lx\n", bd->bi_memsize);
702 printk("enetaddr=%02x%02x%02x%02x%02x%02x\n",
710 printk("intfreq=%ld\n", bd->bi_intfreq);
711 printk("busfreq=%ld\n", bd->bi_busfreq);
712 printk("baudrate=%ld\n", bd->bi_baudrate);
715 #ifdef CONFIG_BLK_DEV_INITRD
717 printk("found initrd @%lx-%lx\n", initrd_start, initrd_end);
719 #endif /* CONFIG_BLK_DEV_INITRD */
721 if(cmdline_start && cmdline_len) {
722 printk("found cmdline: '%s'\n", cmd_line);
725 #endif /* USE PPC_BOOT */
729 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
731 ev64260_ide_check_region(ide_ioreg_t from, unsigned int extent)
733 return check_region(from, extent);
737 ev64260_ide_request_region(ide_ioreg_t from,
741 request_region(from, extent, name);
746 ev64260_ide_release_region(ide_ioreg_t from,
749 release_region(from, extent);
754 ev64260_ide_pci_init_hwif_ports(hw_regs_t *hw, ide_ioreg_t data_port,
755 ide_ioreg_t ctrl_port, int *irq)
761 //printk("regs %d to %d @ 0x%x\n", IDE_DATA_OFFSET, IDE_STATUS_OFFSET, data_port);
762 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
763 hw->io_ports[i] = data_port;
767 //printk("ctrl %d @ 0x%x\n", IDE_CONTROL_OFFSET, ctrl_port);
768 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
771 pci_for_each_dev(dev) {
772 if (((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) ||
773 ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)) {
787 #if !defined(CONFIG_USE_PPCBOOT)
789 * Set BAT 3 to map 0xfb000000 to 0xfc000000 of physical memory space.
791 static __inline__ void
792 ev64260_set_bat(void)
795 mtspr(DBAT1U, 0xfb0001fe);
796 mtspr(DBAT1L, 0xfb00002a);
803 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
807 io_block_mapping(0xfb000000, 0xfb000000, 0x01000000, _PAGE_IO);
812 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
813 unsigned long r6, unsigned long r7)
815 #ifdef CONFIG_BLK_DEV_INITRD
816 extern int initrd_below_start_ok;
818 initrd_start=initrd_end=0;
819 initrd_below_start_ok=0;
820 #endif /* CONFIG_BLK_DEV_INITRD */
823 memset(&ppcboot_bd,0,sizeof(ppcboot_bd));
825 #ifdef CONFIG_USE_PPCBOOT
826 parse_ppcbootinfo(r3, r4, r5, r6, r7);
828 parse_bootinfo(find_bootinfo());
832 isa_io_base = 0xa0000000; /* XXXX */
833 pci_dram_offset = 0x80000000; /* XXXX */
835 loops_per_jiffy = ev64260_get_cpu_speed() / HZ;
837 ppc_md.setup_arch = ev64260_setup_arch;
838 ppc_md.show_cpuinfo = ev64260_show_cpuinfo;
839 ppc_md.init_IRQ = gt64260_init_irq;
840 ppc_md.get_irq = gt64260_get_irq;
842 ppc_md.pcibios_fixup = ev64260_pci_fixups;
844 ppc_md.restart = ev64260_restart;
845 ppc_md.power_off = ev64260_power_off;
846 ppc_md.halt = ev64260_halt;
848 ppc_md.find_end_of_memory = ev64260_find_end_of_memory;
852 ppc_md.time_init = todc_time_init;
853 ppc_md.set_rtc_time = todc_set_rtc_time;
854 ppc_md.get_rtc_time = todc_get_rtc_time;
856 ppc_md.nvram_read_val = todc_direct_read_val;
857 ppc_md.nvram_write_val = todc_direct_write_val;
859 ppc_md.calibrate_decr = ev64260_calibrate_decr;
861 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
862 ppc_ide_md.ide_init_hwif = ev64260_ide_pci_init_hwif_ports;
865 bh.p_base = CONFIG_MV64X60_NEW_BASE;
867 #if !defined(CONFIG_USE_PPCBOOT)
871 #ifdef CONFIG_SERIAL_8250
872 #if defined(CONFIG_SERIAL_TEXT_DEBUG)
873 ppc_md.setup_io_mappings = ev64260_map_io;
874 ppc_md.progress = gen550_progress;
876 #if defined(CONFIG_KGDB)
877 ppc_md.setup_io_mappings = ev64260_map_io;
878 ppc_md.early_serial_map = ev64260_early_serial_map;
880 #elif defined(CONFIG_SERIAL_MPSC_CONSOLE)
881 #ifdef CONFIG_SERIAL_TEXT_DEBUG
882 ppc_md.setup_io_mappings = ev64260_map_io;
883 ppc_md.progress = gt64260_mpsc_progress;
884 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
886 ppc_md.setup_io_mappings = ev64260_map_io;
887 ppc_md.early_serial_map = ev64260_early_serial_map;
888 #endif /* CONFIG_KGDB */