2 * arch/ppc/platforms/ev64260_setup.c
4 * Board setup routines for the Marvell/Galileo EV-64260-BP Evaluation Board.
6 * Author: Mark A. Greer <mgreer@mvista.com>
8 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
15 * The EV-64260-BP port is the result of hard work from many people from
16 * many companies. In particular, employees of Marvell/Galileo, Mission
17 * Critical Linux, Xyterra, and MontaVista Software were heavily involved.
19 #include <linux/config.h>
20 #include <linux/stddef.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/errno.h>
24 #include <linux/reboot.h>
25 #include <linux/pci.h>
26 #include <linux/kdev_t.h>
27 #include <linux/major.h>
28 #include <linux/initrd.h>
29 #include <linux/console.h>
30 #include <linux/delay.h>
31 #include <linux/irq.h>
32 #include <linux/ide.h>
33 #include <linux/seq_file.h>
34 #include <linux/root_dev.h>
35 #if !defined(CONFIG_GT64260_CONSOLE)
36 #include <linux/serial.h>
39 #include <asm/system.h>
40 #include <asm/pgtable.h>
45 #include <asm/machdep.h>
49 #include <asm/bootinfo.h>
50 #include <asm/gt64260.h>
51 #include <platforms/ev64260.h>
54 extern char cmd_line[];
55 unsigned long ev64260_find_end_of_memory(void);
60 * Marvell/Galileo EV-64260-BP Evaluation Board PCI interrupt routing.
63 ev64260_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
65 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
67 if (hose->index == 0) {
68 static char pci_irq_table[][4] =
70 * PCI IDSEL/INTPIN->INTLINE
74 { 91, 0, 0, 0 }, /* IDSEL 7 - PCI bus 0 */
75 { 91, 0, 0, 0 }, /* IDSEL 8 - PCI bus 0 */
78 const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4;
79 return PCI_IRQ_TABLE_LOOKUP;
82 static char pci_irq_table[][4] =
84 * PCI IDSEL/INTPIN->INTLINE
88 { 93, 0, 0, 0 }, /* IDSEL 7 - PCI bus 1 */
89 { 93, 0, 0, 0 }, /* IDSEL 8 - PCI bus 1 */
92 const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4;
93 return PCI_IRQ_TABLE_LOOKUP;
98 ev64260_setup_bridge(void)
100 gt64260_bridge_info_t info;
103 GT64260_BRIDGE_INFO_DEFAULT(&info, ev64260_find_end_of_memory());
105 /* Lookup PCI host bridges */
106 if (gt64260_find_bridges(EV64260_BRIDGE_REG_BASE,
109 printk("Bridge initialization failed.\n");
113 * Enabling of PCI internal-vs-external arbitration
114 * is a platform- and errata-dependent decision.
116 if(gt64260_revision == GT64260) {
118 gt_clr_bits(GT64260_PCI_0_ARBITER_CNTL, (1<<31));
119 gt_clr_bits(GT64260_PCI_1_ARBITER_CNTL, (1<<31));
120 } else if( gt64260_revision == GT64260A ) {
121 gt_set_bits(GT64260_PCI_0_ARBITER_CNTL, (1<<31));
122 gt_set_bits(GT64260_PCI_1_ARBITER_CNTL, (1<<31));
123 /* Make external GPP interrupts level sensitive */
124 gt_set_bits(GT64260_COMM_ARBITER_CNTL, (1<<10));
125 /* Doc Change 9: > 100 MHz so must be set */
126 gt_set_bits(GT64260_CPU_CONFIG, (1<<23));
129 gt_set_bits(GT64260_CPU_MASTER_CNTL, (1<<9)); /* Only 1 cpu */
131 /* SCS windows not disabled above, disable all but SCS 0 */
132 for (window=1; window<GT64260_CPU_SCS_DECODE_WINDOWS; window++) {
133 gt64260_cpu_scs_set_window(window, 0, 0);
136 /* Set up windows to RTC/TODC and DUART on device module (CS 1 & 2) */
137 gt64260_cpu_cs_set_window(1, EV64260_TODC_BASE, EV64260_TODC_LEN);
138 gt64260_cpu_cs_set_window(2, EV64260_UART_BASE, EV64260_UART_LEN);
141 * The EV-64260-BP uses several Multi-Purpose Pins (MPP) on the 64260
142 * bridge as interrupt inputs (via the General Purpose Ports (GPP)
143 * register). Need to route the MPP inputs to the GPP and set the
144 * polarity correctly.
146 * In MPP Control 2 Register
147 * MPP 21 -> GPP 21 (DUART channel A intr)
148 * MPP 22 -> GPP 22 (DUART channel B intr)
150 * In MPP Control 3 Register
151 * MPP 27 -> GPP 27 (PCI 0 INTA)
152 * MPP 29 -> GPP 29 (PCI 1 INTA)
154 gt_clr_bits(GT64260_MPP_CNTL_2,
155 ((1<<20) | (1<<21) | (1<<22) | (1<<23) |
156 (1<<24) | (1<<25) | (1<<26) | (1<<27)));
158 gt_clr_bits(GT64260_MPP_CNTL_3,
159 ((1<<12) | (1<<13) | (1<<14) | (1<<15) |
160 (1<<20) | (1<<21) | (1<<22) | (1<<23)));
162 gt_write(GT64260_GPP_LEVEL_CNTL, 0x000002c6);
164 /* DUART & PCI interrupts are active low */
165 gt_set_bits(GT64260_GPP_LEVEL_CNTL,
166 ((1<<21) | (1<<22) | (1<<27) | (1<<29)));
168 /* Clear any pending interrupts for these inputs and enable them. */
169 gt_write(GT64260_GPP_INTR_CAUSE,
170 ~((1<<21) | (1<<22) | (1<<27) | (1<<29)));
171 gt_set_bits(GT64260_GPP_INTR_MASK,
172 ((1<<21) | (1<<22)| (1<<27) | (1<<29)));
173 gt_set_bits(GT64260_IC_CPU_INTR_MASK_HI, ((1<<26) | (1<<27)));
175 /* Set MPSC Multiplex RMII */
176 /* NOTE: ethernet driver modifies bit 0 and 1 */
177 gt_write(GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
184 ev64260_setup_arch(void)
186 #if !defined(CONFIG_GT64260_CONSOLE)
187 struct serial_struct serial_req;
190 if ( ppc_md.progress )
191 ppc_md.progress("ev64260_setup_arch: enter", 0);
193 loops_per_jiffy = 50000000 / HZ;
195 #ifdef CONFIG_BLK_DEV_INITRD
197 ROOT_DEV = Root_RAM0;
200 #ifdef CONFIG_ROOT_NFS
203 ROOT_DEV = Root_SDA2;
206 if ( ppc_md.progress )
207 ppc_md.progress("ev64260_setup_arch: find_bridges", 0);
210 * Set up the L2CR register.
211 * L2 cache was invalidated by bootloader.
213 switch (PVR_VER(mfspr(PVR))) {
214 case PVR_VER(PVR_750):
215 _set_L2CR(0xfd100000);
217 case PVR_VER(PVR_7400):
218 case PVR_VER(PVR_7410):
219 _set_L2CR(0xcd100000);
221 /* case PVR_VER(PVR_7450): */
222 /* XXXX WHAT VALUE?? FIXME */
226 ev64260_setup_bridge();
228 TODC_INIT(TODC_TYPE_DS1501, 0, 0, ioremap(EV64260_TODC_BASE,0x20), 8);
230 #if !defined(CONFIG_GT64260_CONSOLE)
231 memset(&serial_req, 0, sizeof(serial_req));
233 serial_req.baud_base = BASE_BAUD;
236 serial_req.flags = STD_COM_FLAGS;
237 serial_req.io_type = SERIAL_IO_MEM;
238 serial_req.iomem_base = ioremap(EV64260_SERIAL_0, 0x20);
239 serial_req.iomem_reg_shift = 2;
241 if (early_serial_setup(&serial_req) != 0) {
242 printk("Early serial init of port 0 failed\n");
245 /* Assume early_serial_setup() doesn't modify serial_req */
249 serial_req.iomem_base = ioremap(EV64260_SERIAL_1, 0x20);
251 if (early_serial_setup(&serial_req) != 0) {
252 printk("Early serial init of port 1 failed\n");
256 printk("Marvell/Galileo EV-64260-BP Evaluation Board\n");
257 printk("EV-64260-BP port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n");
259 if ( ppc_md.progress )
260 ppc_md.progress("ev64260_setup_arch: exit", 0);
266 ev64260_init_irq(void)
270 if(gt64260_revision != GT64260) {
271 /* XXXX Kludge--need to fix gt64260_init_irq() interface */
272 /* Mark PCI intrs level sensitive */
273 irq_desc[91].status |= IRQ_LEVEL;
274 irq_desc[93].status |= IRQ_LEVEL;
279 ev64260_find_end_of_memory(void)
281 return 32*1024*1024; /* XXXX FIXME */
285 ev64260_reset_board(void)
289 /* Set exception prefix high - to the firmware */
290 _nmask_and_or_msr(0, MSR_IP);
293 printk("XXXX **** trying to reset board ****\n");
298 ev64260_restart(char *cmd)
300 volatile ulong i = 10000000;
302 ev64260_reset_board();
305 panic("restart failed\n");
317 ev64260_power_off(void)
324 ev64260_show_cpuinfo(struct seq_file *m)
329 seq_printf(m, "vendor\t\t: Marvell/Galileo\n");
330 seq_printf(m, "machine\t\t: EV-64260-BP\n");
331 seq_printf(m, "PVID\t\t: 0x%x, vendor: %s\n",
332 pvid, (pvid & (1<<15) ? "IBM" : "Motorola"));
337 /* DS1501 RTC has too much variation to use RTC for calibration */
339 ev64260_calibrate_decr(void)
343 freq = 100000000 / 4;
345 printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
346 freq/1000000, freq%1000000);
348 tb_ticks_per_jiffy = freq / HZ;
349 tb_to_us = mulhwu_scale_factor(freq, 1000000);
354 #if defined(CONFIG_SERIAL_TEXT_DEBUG)
356 * Set BAT 3 to map 0xf0000000 to end of physical memory space.
358 static __inline__ void
359 ev64260_set_bat(void)
361 unsigned long bat3u, bat3l;
362 static int mapping_set = 0;
366 __asm__ __volatile__(
374 : "=r" (bat3u), "=r" (bat3l));
382 #if !defined(CONFIG_GT64260_CONSOLE)
383 #include <linux/serialP.h>
384 #include <linux/serial_reg.h>
385 #include <asm/serial.h>
387 static struct serial_state rs_table[RS_TABLE_SIZE] = {
388 SERIAL_PORT_DFNS /* Defined in <asm/serial.h> */
392 ev64260_16550_progress(char *s, unsigned short hex)
395 volatile unsigned long com_port;
398 com_port = rs_table[0].port;
399 shift = rs_table[0].iomem_reg_shift;
401 while ((c = *s++) != 0) {
402 while ((*((volatile unsigned char *)com_port +
403 (UART_LSR << shift)) & UART_LSR_THRE) == 0)
405 *(volatile unsigned char *)com_port = c;
408 while ((*((volatile unsigned char *)com_port +
409 (UART_LSR << shift)) & UART_LSR_THRE) == 0)
411 *(volatile unsigned char *)com_port = '\r';
415 /* Move to next line on */
416 while ((*((volatile unsigned char *)com_port +
417 (UART_LSR << shift)) & UART_LSR_THRE) == 0)
419 *(volatile unsigned char *)com_port = '\n';
420 while ((*((volatile unsigned char *)com_port +
421 (UART_LSR << shift)) & UART_LSR_THRE) == 0)
423 *(volatile unsigned char *)com_port = '\r';
427 #endif /* !CONFIG_GT64260_CONSOLE */
428 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
431 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
432 unsigned long r6, unsigned long r7)
434 parse_bootinfo(find_bootinfo());
438 ppc_md.setup_arch = ev64260_setup_arch;
439 ppc_md.show_cpuinfo = ev64260_show_cpuinfo;
440 ppc_md.irq_canonicalize = NULL;
441 ppc_md.init_IRQ = ev64260_init_irq;
442 ppc_md.get_irq = gt64260_get_irq;
445 ppc_md.restart = ev64260_restart;
446 ppc_md.power_off = ev64260_power_off;
447 ppc_md.halt = ev64260_halt;
449 ppc_md.find_end_of_memory = ev64260_find_end_of_memory;
451 ppc_md.time_init = todc_time_init;
452 ppc_md.set_rtc_time = todc_set_rtc_time;
453 ppc_md.get_rtc_time = todc_get_rtc_time;
454 ppc_md.calibrate_decr = ev64260_calibrate_decr;
456 ppc_md.nvram_read_val = todc_direct_read_val;
457 ppc_md.nvram_write_val = todc_direct_write_val;
459 ppc_md.heartbeat = NULL;
460 ppc_md.heartbeat_reset = 0;
461 ppc_md.heartbeat_count = 0;
463 #ifdef CONFIG_SERIAL_TEXT_DEBUG
465 #ifdef CONFIG_GT64260_CONSOLE
466 gt64260_base = EV64260_BRIDGE_REG_BASE;
467 ppc_md.progress = gt64260_mpsc_progress; /* embedded UART */
469 ppc_md.progress = ev64260_16550_progress; /* Dev module DUART */
471 #else /* !CONFIG_SERIAL_TEXT_DEBUG */
472 ppc_md.progress = NULL;
473 #endif /* CONFIG_SERIAL_TEXT_DEBUG */