2 * arch/ppc/platforms/k2.c
4 * Board setup routines for SBS K2
6 * Author: Matt Porter <mporter@mvista.com>
8 * Updated by: Randy Vinson <rvinson@mvista.com.
10 * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
16 #include <linux/config.h>
17 #include <linux/stddef.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/errno.h>
21 #include <linux/reboot.h>
22 #include <linux/pci.h>
23 #include <linux/kdev_t.h>
24 #include <linux/types.h>
25 #include <linux/major.h>
26 #include <linux/initrd.h>
27 #include <linux/console.h>
28 #include <linux/delay.h>
29 #include <linux/ide.h>
30 #include <linux/irq.h>
31 #include <linux/seq_file.h>
32 #include <linux/root_dev.h>
34 #include <asm/system.h>
35 #include <asm/pgtable.h>
39 #include <asm/machdep.h>
41 #include <asm/i8259.h>
43 #include <asm/bootinfo.h>
45 #include <syslib/cpc710.h>
48 extern unsigned long loops_per_jiffy;
49 extern void gen550_progress(char *, unsigned short);
51 static unsigned int cpu_7xx[16] = {
52 0, 15, 14, 0, 0, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0
54 static unsigned int cpu_6xx[16] = {
55 0, 0, 14, 0, 0, 13, 5, 9, 6, 11, 8, 10, 0, 12, 7, 0
58 static inline int __init
59 k2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
61 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
63 * Check our hose index. If we are zero then we are on the
64 * local PCI hose, otherwise we are on the cPCI hose.
67 static char pci_irq_table[][4] =
69 * PCI IDSEL/INTPIN->INTLINE
73 {1, 0, 0, 0}, /* Ethernet */
74 {5, 5, 5, 5}, /* PMC Site 1 */
75 {6, 6, 6, 6}, /* PMC Site 2 */
76 {0, 0, 0, 0}, /* unused */
77 {0, 0, 0, 0}, /* unused */
78 {0, 0, 0, 0}, /* PCI-ISA Bridge */
79 {0, 0, 0, 0}, /* unused */
80 {0, 0, 0, 0}, /* unused */
81 {0, 0, 0, 0}, /* unused */
82 {0, 0, 0, 0}, /* unused */
83 {0, 0, 0, 0}, /* unused */
84 {0, 0, 0, 0}, /* unused */
85 {0, 0, 0, 0}, /* unused */
86 {0, 0, 0, 0}, /* unused */
87 {15, 0, 0, 0}, /* M5229 IDE */
89 const long min_idsel = 3, max_idsel = 17, irqs_per_slot = 4;
90 return PCI_IRQ_TABLE_LOOKUP;
92 static char pci_irq_table[][4] =
94 * PCI IDSEL/INTPIN->INTLINE
98 {10, 11, 12, 9}, /* cPCI slot 8 */
99 {11, 12, 9, 10}, /* cPCI slot 7 */
100 {12, 9, 10, 11}, /* cPCI slot 6 */
101 {9, 10, 11, 12}, /* cPCI slot 5 */
102 {10, 11, 12, 9}, /* cPCI slot 4 */
103 {11, 12, 9, 10}, /* cPCI slot 3 */
104 {12, 9, 10, 11}, /* cPCI slot 2 */
106 const long min_idsel = 15, max_idsel = 21, irqs_per_slot = 4;
107 return PCI_IRQ_TABLE_LOOKUP;
111 void k2_pcibios_fixup(void)
113 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
114 struct pci_dev *ide_dev;
117 * Enable DMA support on hdc
119 ide_dev = pci_find_device(PCI_VENDOR_ID_AL,
120 PCI_DEVICE_ID_AL_M5229, NULL);
124 unsigned long ide_dma_base;
126 ide_dma_base = pci_resource_start(ide_dev, 4);
127 outb(0x00, ide_dma_base + 0x2);
128 outb(0x20, ide_dma_base + 0xa);
133 void k2_pcibios_fixup_resources(struct pci_dev *dev)
137 if ((dev->vendor == PCI_VENDOR_ID_IBM) &&
138 (dev->device == PCI_DEVICE_ID_IBM_CPC710_PCI64)) {
139 pr_debug("Fixup CPC710 resources\n");
140 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
141 dev->resource[i].start = 0;
142 dev->resource[i].end = 0;
147 void k2_setup_hoses(void)
149 struct pci_controller *hose_a, *hose_b;
152 * Reconfigure CPC710 memory map so
153 * we have some more PCI memory space.
157 __raw_writel(0x808000e0, PGCHP); /* Set FPHB mode */
160 __raw_writel(0x00000000, K2_PCI32_BAR + PIBAR); /* PCI I/O base */
161 __raw_writel(0x00000000, K2_PCI32_BAR + PMBAR); /* PCI Mem base */
162 __raw_writel(0xf0000000, K2_PCI32_BAR + MSIZE); /* 256MB */
163 __raw_writel(0xfff00000, K2_PCI32_BAR + IOSIZE); /* 1MB */
164 __raw_writel(0xc0000000, K2_PCI32_BAR + SMBAR); /* Base@0xc0000000 */
165 __raw_writel(0x80000000, K2_PCI32_BAR + SIBAR); /* Base@0x80000000 */
166 __raw_writel(0x000000c0, K2_PCI32_BAR + PSSIZE); /* 1GB space */
167 __raw_writel(0x000000c0, K2_PCI32_BAR + PPSIZE); /* 1GB space */
168 __raw_writel(0x00000000, K2_PCI32_BAR + BARPS); /* Base@0x00000000 */
169 __raw_writel(0x00000000, K2_PCI32_BAR + BARPP); /* Base@0x00000000 */
170 __raw_writel(0x00000080, K2_PCI32_BAR + PSBAR); /* Base@0x80 */
171 __raw_writel(0x00000000, K2_PCI32_BAR + PPBAR);
173 __raw_writel(0xc0000000, K2_PCI32_BAR + BPMDLK);
174 __raw_writel(0xd0000000, K2_PCI32_BAR + TPMDLK);
175 __raw_writel(0x80000000, K2_PCI32_BAR + BIODLK);
176 __raw_writel(0x80100000, K2_PCI32_BAR + TIODLK);
177 __raw_writel(0xe0008000, K2_PCI32_BAR + DLKCTRL);
178 __raw_writel(0xffffffff, K2_PCI32_BAR + DLKDEV);
181 __raw_writel(0x00100000, K2_PCI64_BAR + PIBAR); /* PCI I/O base */
182 __raw_writel(0x10000000, K2_PCI64_BAR + PMBAR); /* PCI Mem base */
183 __raw_writel(0xf0000000, K2_PCI64_BAR + MSIZE); /* 256MB */
184 __raw_writel(0xfff00000, K2_PCI64_BAR + IOSIZE); /* 1MB */
185 __raw_writel(0xd0000000, K2_PCI64_BAR + SMBAR); /* Base@0xd0000000 */
186 __raw_writel(0x80100000, K2_PCI64_BAR + SIBAR); /* Base@0x80100000 */
187 __raw_writel(0x000000c0, K2_PCI64_BAR + PSSIZE); /* 1GB space */
188 __raw_writel(0x000000c0, K2_PCI64_BAR + PPSIZE); /* 1GB space */
189 __raw_writel(0x00000000, K2_PCI64_BAR + BARPS); /* Base@0x00000000 */
190 __raw_writel(0x00000000, K2_PCI64_BAR + BARPP); /* Base@0x00000000 */
192 /* Setup PCI32 hose */
193 hose_a = pcibios_alloc_controller();
197 hose_a->first_busno = 0;
198 hose_a->last_busno = 0xff;
199 hose_a->pci_mem_offset = K2_PCI32_MEM_BASE;
201 pci_init_resource(&hose_a->io_resource,
204 IORESOURCE_IO, "PCI32 host bridge");
206 pci_init_resource(&hose_a->mem_resources[0],
207 K2_PCI32_LOWER_MEM + K2_PCI32_MEM_BASE,
208 K2_PCI32_UPPER_MEM + K2_PCI32_MEM_BASE,
209 IORESOURCE_MEM, "PCI32 host bridge");
211 hose_a->io_space.start = K2_PCI32_LOWER_IO;
212 hose_a->io_space.end = K2_PCI32_UPPER_IO;
213 hose_a->mem_space.start = K2_PCI32_LOWER_MEM;
214 hose_a->mem_space.end = K2_PCI32_UPPER_MEM;
215 hose_a->io_base_virt = (void *)K2_ISA_IO_BASE;
217 setup_indirect_pci(hose_a, K2_PCI32_CONFIG_ADDR, K2_PCI32_CONFIG_DATA);
219 /* Initialize PCI32 bus registers */
220 early_write_config_byte(hose_a,
223 CPC710_BUS_NUMBER, hose_a->first_busno);
225 early_write_config_byte(hose_a,
228 CPC710_SUB_BUS_NUMBER, hose_a->last_busno);
230 /* Enable PCI interrupt polling */
231 early_write_config_byte(hose_a,
233 PCI_DEVFN(8, 0), 0x45, 0x80);
235 /* Route polled PCI interrupts */
236 early_write_config_byte(hose_a,
238 PCI_DEVFN(8, 0), 0x48, 0x58);
240 early_write_config_byte(hose_a,
242 PCI_DEVFN(8, 0), 0x49, 0x07);
244 early_write_config_byte(hose_a,
246 PCI_DEVFN(8, 0), 0x4a, 0x31);
248 early_write_config_byte(hose_a,
250 PCI_DEVFN(8, 0), 0x4b, 0xb9);
252 /* route secondary IDE channel interrupt to IRQ 15 */
253 early_write_config_byte(hose_a,
255 PCI_DEVFN(8, 0), 0x75, 0x0f);
257 /* enable IDE controller IDSEL */
258 early_write_config_byte(hose_a,
260 PCI_DEVFN(8, 0), 0x58, 0x48);
262 /* Enable IDE function */
263 early_write_config_byte(hose_a,
265 PCI_DEVFN(17, 0), 0x50, 0x03);
267 /* Set M5229 IDE controller to native mode */
268 early_write_config_byte(hose_a,
270 PCI_DEVFN(17, 0), PCI_CLASS_PROG, 0xdf);
272 hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
274 /* Write out correct max subordinate bus number for hose A */
275 early_write_config_byte(hose_a,
278 CPC710_SUB_BUS_NUMBER, hose_a->last_busno);
280 /* Only setup PCI64 hose if we are in the system slot */
281 if (!(readb(K2_MISC_REG) & K2_SYS_SLOT_MASK)) {
282 /* Setup PCI64 hose */
283 hose_b = pcibios_alloc_controller();
287 hose_b->first_busno = hose_a->last_busno + 1;
288 hose_b->last_busno = 0xff;
290 /* Reminder: quit changing the following, it is correct. */
291 hose_b->pci_mem_offset = K2_PCI32_MEM_BASE;
293 pci_init_resource(&hose_b->io_resource,
296 IORESOURCE_IO, "PCI64 host bridge");
298 pci_init_resource(&hose_b->mem_resources[0],
299 K2_PCI64_LOWER_MEM + K2_PCI32_MEM_BASE,
300 K2_PCI64_UPPER_MEM + K2_PCI32_MEM_BASE,
301 IORESOURCE_MEM, "PCI64 host bridge");
303 hose_b->io_space.start = K2_PCI64_LOWER_IO;
304 hose_b->io_space.end = K2_PCI64_UPPER_IO;
305 hose_b->mem_space.start = K2_PCI64_LOWER_MEM;
306 hose_b->mem_space.end = K2_PCI64_UPPER_MEM;
307 hose_b->io_base_virt = (void *)K2_ISA_IO_BASE;
309 setup_indirect_pci(hose_b,
310 K2_PCI64_CONFIG_ADDR, K2_PCI64_CONFIG_DATA);
312 /* Initialize PCI64 bus registers */
313 early_write_config_byte(hose_b,
316 CPC710_SUB_BUS_NUMBER, 0xff);
318 early_write_config_byte(hose_b,
321 CPC710_BUS_NUMBER, hose_b->first_busno);
323 hose_b->last_busno = pciauto_bus_scan(hose_b,
324 hose_b->first_busno);
326 /* Write out correct max subordinate bus number for hose B */
327 early_write_config_byte(hose_b,
330 CPC710_SUB_BUS_NUMBER,
333 /* Configure PCI64 PSBAR */
334 early_write_config_dword(hose_b,
338 K2_PCI64_SYS_MEM_BASE);
341 /* Configure i8259 level/edge settings */
345 #ifdef CONFIG_CPC710_DATA_GATHERING
348 tmp = __raw_readl(ABCNTL);
349 /* Enable data gathering on both PCI interfaces */
350 __raw_writel(tmp | 0x05000000, ABCNTL);
354 ppc_md.pcibios_fixup = k2_pcibios_fixup;
355 ppc_md.pcibios_fixup_resources = k2_pcibios_fixup_resources;
356 ppc_md.pci_swizzle = common_swizzle;
357 ppc_md.pci_map_irq = k2_map_irq;
360 static int k2_get_bus_speed(void)
363 unsigned char board_id;
365 board_id = *(unsigned char *)K2_BOARD_ID_REG;
367 switch (K2_BUS_SPD(board_id)) {
371 bus_speed = 100000000;
375 bus_speed = 83333333;
379 bus_speed = 75000000;
383 bus_speed = 66666666;
389 static int k2_get_cpu_speed(void)
394 hid1 = mfspr(HID1) >> 28;
396 if ((mfspr(PVR) >> 16) == 8)
397 hid1 = cpu_7xx[hid1];
399 hid1 = cpu_6xx[hid1];
401 cpu_speed = k2_get_bus_speed() * hid1 / 2;
405 static void __init k2_calibrate_decr(void)
407 int freq, divisor = 4;
409 /* determine processor bus speed */
410 freq = k2_get_bus_speed();
411 tb_ticks_per_jiffy = freq / HZ / divisor;
412 tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
415 static int k2_show_cpuinfo(struct seq_file *m)
417 unsigned char k2_geo_bits, k2_system_slot;
419 seq_printf(m, "vendor\t\t: SBS\n");
420 seq_printf(m, "machine\t\t: K2\n");
421 seq_printf(m, "cpu speed\t: %dMhz\n", k2_get_cpu_speed() / 1000000);
422 seq_printf(m, "bus speed\t: %dMhz\n", k2_get_bus_speed() / 1000000);
423 seq_printf(m, "memory type\t: SDRAM\n");
425 k2_geo_bits = readb(K2_MSIZ_GEO_REG) & K2_GEO_ADR_MASK;
426 k2_system_slot = !(readb(K2_MISC_REG) & K2_SYS_SLOT_MASK);
427 seq_printf(m, "backplane\t: %s slot board",
428 k2_system_slot ? "System" : "Non system");
429 seq_printf(m, "with geographical address %x\n", k2_geo_bits);
436 static void __init k2_setup_arch(void)
440 /* Setup TODC access */
441 TODC_INIT(TODC_TYPE_MK48T37, 0, 0,
442 ioremap(K2_RTC_BASE_ADDRESS, K2_RTC_SIZE), 8);
444 /* init to some ~sane value until calibrate_delay() runs */
445 loops_per_jiffy = 50000000 / HZ;
447 /* make FLASH transactions higher priority than PCI to avoid deadlock */
448 __raw_writel(__raw_readl(SIOC1) | 0x80000000, SIOC1);
450 /* Set hardware to access FLASH page 2 */
451 __raw_writel(1 << 29, GPOUT);
453 /* Setup PCI host bridges */
456 #ifdef CONFIG_BLK_DEV_INITRD
458 ROOT_DEV = Root_RAM0;
461 #ifdef CONFIG_ROOT_NFS
464 ROOT_DEV = Root_HDC1;
467 #ifdef CONFIG_DUMMY_CONSOLE
468 conswitchp = &dummy_con;
471 /* Identify the system */
472 printk(KERN_INFO "System Identification: SBS K2 - PowerPC 750 @ "
473 "%d Mhz\n", k2_get_cpu_speed() / 1000000);
474 printk(KERN_INFO "Port by MontaVista Software, Inc. "
475 "(source@mvista.com)\n");
477 /* Identify the CPU manufacturer */
478 cpu = PVR_REV(mfspr(PVR));
479 printk(KERN_INFO "CPU manufacturer: %s [rev=%04x]\n",
480 (cpu & (1 << 15)) ? "IBM" : "Motorola", cpu);
483 static void k2_restart(char *cmd)
487 /* Flip FLASH back to page 1 to access firmware image */
488 __raw_writel(0, GPOUT);
490 /* SRR0 has system reset vector, SRR1 has default MSR value */
491 /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
492 mtspr(SRR0, 0xfff00100);
494 __asm__ __volatile__("rfi\n\t");
500 static void k2_power_off(void)
505 static void k2_halt(void)
511 * Set BAT 3 to map PCI32 I/O space.
513 static __inline__ void k2_set_bat(void)
515 /* wait for all outstanding memory accesses to complete */
519 mtspr(DBAT2U, 0x80001ffe);
520 mtspr(DBAT2L, 0x8000002a);
521 mtspr(DBAT3U, 0xf0001ffe);
522 mtspr(DBAT3L, 0xf000002a);
524 /* wait for updates */
528 static unsigned long __init k2_find_end_of_memory(void)
531 unsigned char msize = 7; /* Default to 128MB */
533 msize = K2_MEM_SIZE(readb(K2_MSIZ_GEO_REG));
538 * This will break without a lowered
539 * KERNELBASE or CONFIG_HIGHMEM on.
540 * It seems non 1GB builds exist yet,
543 total = K2_MEM_SIZE_1GB;
547 total = K2_MEM_SIZE_512MB;
551 total = K2_MEM_SIZE_256MB;
554 total = K2_MEM_SIZE_128MB;
558 ("K2: Invalid memory size detected, defaulting to 128MB\n");
559 total = K2_MEM_SIZE_128MB;
565 static void __init k2_map_io(void)
567 io_block_mapping(K2_PCI32_IO_BASE,
568 K2_PCI32_IO_BASE, 0x00200000, _PAGE_IO);
569 io_block_mapping(0xff000000, 0xff000000, 0x01000000, _PAGE_IO);
572 static void __init k2_init_irq(void)
576 for (i = 0; i < 16; i++)
577 irq_desc[i].handler = &i8259_pic;
582 void __init platform_init(unsigned long r3, unsigned long r4,
583 unsigned long r5, unsigned long r6, unsigned long r7)
585 parse_bootinfo((struct bi_record *)(r3 + KERNELBASE));
589 isa_io_base = K2_ISA_IO_BASE;
590 isa_mem_base = K2_ISA_MEM_BASE;
591 pci_dram_offset = K2_PCI32_SYS_MEM_BASE;
593 ppc_md.setup_arch = k2_setup_arch;
594 ppc_md.show_cpuinfo = k2_show_cpuinfo;
595 ppc_md.init_IRQ = k2_init_irq;
596 ppc_md.get_irq = i8259_irq;
598 ppc_md.find_end_of_memory = k2_find_end_of_memory;
599 ppc_md.setup_io_mappings = k2_map_io;
601 ppc_md.restart = k2_restart;
602 ppc_md.power_off = k2_power_off;
603 ppc_md.halt = k2_halt;
605 ppc_md.time_init = todc_time_init;
606 ppc_md.set_rtc_time = todc_set_rtc_time;
607 ppc_md.get_rtc_time = todc_get_rtc_time;
608 ppc_md.calibrate_decr = k2_calibrate_decr;
610 ppc_md.nvram_read_val = todc_direct_read_val;
611 ppc_md.nvram_write_val = todc_direct_write_val;
613 #ifdef CONFIG_SERIAL_TEXT_DEBUG
614 ppc_md.progress = gen550_progress;