2 * arch/ppc/platforms/lopec_setup.c
4 * Setup routines for the Motorola LoPEC.
9 * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/delay.h>
18 #include <linux/pci_ids.h>
19 #include <linux/ioport.h>
20 #include <linux/init.h>
21 #include <linux/ide.h>
22 #include <linux/seq_file.h>
23 #include <linux/initrd.h>
24 #include <linux/console.h>
25 #include <linux/root_dev.h>
28 #include <asm/open_pic.h>
29 #include <asm/i8259.h>
31 #include <asm/bootinfo.h>
32 #include <asm/mpc10x.h>
33 #include <asm/hw_irq.h>
34 #include <asm/prep_nvram.h>
36 extern void lopec_find_bridges(void);
39 * Define all of the IRQ senses and polarities. Taken from the
40 * LoPEC Programmer's Reference Guide.
42 static u_char lopec_openpic_initsenses[16] __initdata = {
43 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 0 */
44 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 1 */
45 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 2 */
46 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 3 */
47 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 4 */
48 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 5 */
49 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 6 */
50 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 7 */
51 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 8 */
52 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 9 */
53 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 10 */
54 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 11 */
55 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 12 */
56 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 13 */
57 (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ 14 */
58 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE) /* IRQ 15 */
62 lopec_show_cpuinfo(struct seq_file *m)
64 seq_printf(m, "machine\t\t: Motorola LoPEC\n");
69 lopec_irq_canonicalize(u32 irq)
78 lopec_restart(char *cmd)
80 #define LOPEC_SYSSTAT1 0xffe00000
81 /* force a hard reset, if possible */
82 unsigned char reg = *((unsigned char *) LOPEC_SYSSTAT1);
84 *((unsigned char *) LOPEC_SYSSTAT1) = reg;
104 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
105 int lopec_ide_ports_known = 0;
106 static unsigned long lopec_ide_regbase[MAX_HWIFS];
107 static unsigned long lopec_ide_ctl_regbase[MAX_HWIFS];
108 static unsigned long lopec_idedma_regbase;
111 lopec_ide_probe(void)
113 struct pci_dev *dev = pci_find_device(PCI_VENDOR_ID_WINBOND,
114 PCI_DEVICE_ID_WINBOND_82C105,
116 lopec_ide_ports_known = 1;
119 lopec_ide_regbase[0] = dev->resource[0].start;
120 lopec_ide_regbase[1] = dev->resource[2].start;
121 lopec_ide_ctl_regbase[0] = dev->resource[1].start;
122 lopec_ide_ctl_regbase[1] = dev->resource[3].start;
123 lopec_idedma_regbase = dev->resource[4].start;
128 lopec_ide_default_irq(unsigned long base)
130 if (lopec_ide_ports_known == 0)
133 if (base == lopec_ide_regbase[0])
135 else if (base == lopec_ide_regbase[1])
142 lopec_ide_default_io_base(int index)
144 if (lopec_ide_ports_known == 0)
146 return lopec_ide_regbase[index];
150 lopec_ide_init_hwif_ports(hw_regs_t *hw, unsigned long data,
151 unsigned long ctl, int *irq)
153 unsigned long reg = data;
154 uint alt_status_base;
157 for(i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
158 hw->io_ports[i] = reg++;
160 if (data == lopec_ide_regbase[0]) {
161 alt_status_base = lopec_ide_ctl_regbase[0] + 2;
164 else if (data == lopec_ide_regbase[1]) {
165 alt_status_base = lopec_ide_ctl_regbase[1] + 2;
174 hw->io_ports[IDE_CONTROL_OFFSET] = ctl;
176 hw->io_ports[IDE_CONTROL_OFFSET] = alt_status_base;
182 #endif /* BLK_DEV_IDE */
190 * Provide the open_pic code with the correct table of interrupts.
192 OpenPIC_InitSenses = lopec_openpic_initsenses;
193 OpenPIC_NumInitSenses = sizeof(lopec_openpic_initsenses);
195 mpc10x_set_openpic();
197 /* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */
198 openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
201 /* Map i8259 interrupts */
202 for(i = 0; i < NUM_8259_INTERRUPTS; i++)
203 irq_desc[i].handler = &i8259_pic;
206 * The EPIC allows for a read in the range of 0xFEF00000 ->
207 * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
209 i8259_init(0xfef00000);
213 lopec_request_io(void)
218 request_region(0x00, 0x20, "dma1");
219 request_region(0x20, 0x20, "pic1");
220 request_region(0x40, 0x20, "timer");
221 request_region(0x80, 0x10, "dma page reg");
222 request_region(0xa0, 0x20, "pic2");
223 request_region(0xc0, 0x20, "dma2");
228 device_initcall(lopec_request_io);
233 io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO);
234 io_block_mapping(0xb0000000, 0xb0000000, 0x10000000, _PAGE_IO);
240 unsigned long batu, batl;
242 __asm__ __volatile__(
250 : "=r" (batu), "=r" (batl));
253 #ifdef CONFIG_SERIAL_TEXT_DEBUG
254 #include <linux/serial.h>
255 #include <linux/serialP.h>
256 #include <linux/serial_reg.h>
257 #include <asm/serial.h>
259 static struct serial_state rs_table[RS_TABLE_SIZE] = {
260 SERIAL_PORT_DFNS /* Defined in <asm/serial.h> */
263 volatile unsigned char *com_port;
264 volatile unsigned char *com_port_lsr;
267 serial_writechar(char c)
269 while ((*com_port_lsr & UART_LSR_THRE) == 0)
275 lopec_progress(char *s, unsigned short hex)
279 com_port = (volatile unsigned char *) rs_table[0].port;
280 com_port_lsr = com_port + UART_LSR;
282 while ((c = *s++) != 0)
285 /* Most messages don't have a newline in them */
286 serial_writechar('\n');
287 serial_writechar('\r');
289 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
294 lopec_setup_arch(void)
297 TODC_INIT(TODC_TYPE_MK48T37, 0, 0,
298 ioremap(0xffe80000, 0x8000), 8);
300 loops_per_jiffy = 100000000/HZ;
302 lopec_find_bridges();
304 #ifdef CONFIG_BLK_DEV_INITRD
306 ROOT_DEV = Root_RAM0;
308 #elif defined(CONFIG_ROOT_NFS)
310 #elif defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
311 ROOT_DEV = Root_HDA1;
313 ROOT_DEV = Root_SDA1;
317 conswitchp = &dummy_con;
319 #ifdef CONFIG_PPCBUG_NVRAM
320 /* Read in NVRAM data */
323 /* if no bootargs, look in NVRAM */
324 if ( cmd_line[0] == '\0' ) {
326 bootargs = prep_nvram_get_var("bootargs");
327 if (bootargs != NULL) {
328 strcpy(cmd_line, bootargs);
330 strcpy(saved_command_line, cmd_line);
337 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
338 unsigned long r6, unsigned long r7)
340 parse_bootinfo(find_bootinfo());
343 isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
344 isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
345 pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
346 ISA_DMA_THRESHOLD = 0x00ffffff;
347 DMA_MODE_READ = 0x44;
348 DMA_MODE_WRITE = 0x48;
350 ppc_md.setup_arch = lopec_setup_arch;
351 ppc_md.show_cpuinfo = lopec_show_cpuinfo;
352 ppc_md.irq_canonicalize = lopec_irq_canonicalize;
353 ppc_md.init_IRQ = lopec_init_IRQ;
354 ppc_md.get_irq = openpic_get_irq;
356 ppc_md.restart = lopec_restart;
357 ppc_md.power_off = lopec_power_off;
358 ppc_md.halt = lopec_halt;
360 ppc_md.setup_io_mappings = lopec_map_io;
362 ppc_md.time_init = todc_time_init;
363 ppc_md.set_rtc_time = todc_set_rtc_time;
364 ppc_md.get_rtc_time = todc_get_rtc_time;
365 ppc_md.calibrate_decr = todc_calibrate_decr;
367 ppc_md.nvram_read_val = todc_direct_read_val;
368 ppc_md.nvram_write_val = todc_direct_write_val;
370 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
371 ppc_ide_md.default_irq = lopec_ide_default_irq;
372 ppc_ide_md.default_io_base = lopec_ide_default_io_base;
373 ppc_ide_md.ide_init_hwif = lopec_ide_init_hwif_ports;
375 #ifdef CONFIG_SERIAL_TEXT_DEBUG
376 ppc_md.progress = lopec_progress;