2 * arch/ppc/platforms/mcpn765.c
4 * Board setup routines for the Motorola MCG MCPN765 cPCI Board.
6 * Author: Mark A. Greer
9 * Modified by Randy Vinson (rvinson@mvista.com)
11 * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
18 * This file adds support for the Motorola MCG MCPN765.
20 #include <linux/config.h>
21 #include <linux/stddef.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/errno.h>
25 #include <linux/reboot.h>
26 #include <linux/pci.h>
27 #include <linux/kdev_t.h>
28 #include <linux/major.h>
29 #include <linux/initrd.h>
30 #include <linux/console.h>
31 #include <linux/delay.h>
32 #include <linux/irq.h>
33 #include <linux/seq_file.h>
34 #include <linux/root_dev.h>
35 #include <linux/serial.h>
36 #include <linux/tty.h> /* for linux/serial_core.h */
37 #include <linux/serial_core.h>
38 #include <linux/slab.h>
40 #include <asm/system.h>
41 #include <asm/pgtable.h>
45 #include <asm/byteorder.h>
47 #include <asm/machdep.h>
50 #include <asm/open_pic.h>
51 #include <asm/i8259.h>
53 #include <asm/pci-bridge.h>
55 #include <asm/uaccess.h>
56 #include <asm/bootinfo.h>
61 #include "mcpn765_serial.h"
64 static u_char mcpn765_openpic_initsenses[] __initdata = {
65 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE),/* 16: i8259 cascade */
66 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 17: COM1,2,3,4 */
67 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 18: Enet 1 (front) */
68 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 19: HAWK WDT XXXX */
69 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 20: 21554 bridge */
70 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 21: cPCI INTA# */
71 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 22: cPCI INTB# */
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 23: cPCI INTC# */
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 24: cPCI INTD# */
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 25: PMC1 INTA#,PMC2 INTB#*/
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 26: PMC1 INTB#,PMC2 INTC#*/
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 27: PMC1 INTC#,PMC2 INTD#*/
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 28: PMC1 INTD#,PMC2 INTA#*/
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 29: Enet 2 (J3) */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 30: Abort Switch */
80 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 31: RTC Alarm */
83 extern void mcpn765_set_VIA_IDE_native(void);
85 extern u_int openpic_irq(void);
86 extern char cmd_line[];
88 extern void gen550_progress(char *, unsigned short);
89 extern void gen550_init(int, struct uart_port *);
91 int use_of_interrupt_tree = 0;
93 static void mcpn765_halt(void);
98 * Motorola MCG MCPN765 interrupt routing.
101 mcpn765_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
103 static char pci_irq_table[][4] =
105 * PCI IDSEL/INTPIN->INTLINE
109 { 14, 0, 0, 0 }, /* IDSEL 11 - have to manually set */
110 { 0, 0, 0, 0 }, /* IDSEL 12 - unused */
111 { 0, 0, 0, 0 }, /* IDSEL 13 - unused */
112 { 18, 0, 0, 0 }, /* IDSEL 14 - Enet 0 */
113 { 0, 0, 0, 0 }, /* IDSEL 15 - unused */
114 { 25, 26, 27, 28 }, /* IDSEL 16 - PMC Slot 1 */
115 { 28, 25, 26, 27 }, /* IDSEL 17 - PMC Slot 2 */
116 { 0, 0, 0, 0 }, /* IDSEL 18 - PMC 2B Connector XXXX */
117 { 29, 0, 0, 0 }, /* IDSEL 19 - Enet 1 */
118 { 20, 0, 0, 0 }, /* IDSEL 20 - 21554 cPCI bridge */
121 const long min_idsel = 11, max_idsel = 20, irqs_per_slot = 4;
122 return PCI_IRQ_TABLE_LOOKUP;
126 mcpn765_set_VIA_IDE_legacy(void)
128 unsigned short vend, dev;
130 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend);
131 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev);
133 if ((vend == PCI_VENDOR_ID_VIA) &&
134 (dev == PCI_DEVICE_ID_VIA_82C586_1)) {
138 /* put back original "standard" port base addresses */
139 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
140 PCI_BASE_ADDRESS_0, 0x1f1);
141 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
142 PCI_BASE_ADDRESS_1, 0x3f5);
143 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
144 PCI_BASE_ADDRESS_2, 0x171);
145 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
146 PCI_BASE_ADDRESS_3, 0x375);
147 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
148 PCI_BASE_ADDRESS_4, 0xcc01);
150 /* put into legacy mode */
151 early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
154 early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
160 mcpn765_set_VIA_IDE_native(void)
162 unsigned short vend, dev;
164 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend);
165 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev);
167 if ((vend == PCI_VENDOR_ID_VIA) &&
168 (dev == PCI_DEVICE_ID_VIA_82C586_1)) {
172 /* put into native mode */
173 early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
176 early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
182 * Initialize the VIA 82c586b.
185 mcpn765_setup_via_82c586b(void)
190 if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
191 PCI_DEVICE_ID_VIA_82C586_0,
193 printk("No VIA ISA bridge found\n");
199 * If the firmware left the EISA 4d0/4d1 ports enabled, make sure
200 * IRQ 14 is set for edge.
202 pci_read_config_byte(dev, 0x47, &c);
210 /* Disable PNP IRQ routing since we use the Hawk's MPIC */
211 pci_write_config_dword(dev, 0x54, 0);
212 pci_write_config_byte(dev, 0x58, 0);
215 if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
216 PCI_DEVICE_ID_VIA_82C586_1,
218 printk("No VIA ISA bridge found\n");
224 * PPCBug doesn't set the enable bits for the IDE device.
227 pci_read_config_byte(dev, 0x40, &c);
229 pci_write_config_byte(dev, 0x40, c);
235 mcpn765_pcibios_fixup(void)
237 /* Do MCPN765 board specific initialization. */
238 mcpn765_setup_via_82c586b();
242 mcpn765_find_bridges(void)
244 struct pci_controller *hose;
246 hose = pcibios_alloc_controller();
251 hose->first_busno = 0;
252 hose->last_busno = 0xff;
253 hose->pci_mem_offset = MCPN765_PCI_PHY_MEM_OFFSET;
255 pci_init_resource(&hose->io_resource,
256 MCPN765_PCI_IO_START,
261 pci_init_resource(&hose->mem_resources[0],
262 MCPN765_PCI_MEM_START,
267 hose->io_space.start = MCPN765_PCI_IO_START;
268 hose->io_space.end = MCPN765_PCI_IO_END;
269 hose->mem_space.start = MCPN765_PCI_MEM_START;
270 hose->mem_space.end = MCPN765_PCI_MEM_END - HAWK_MPIC_SIZE;
273 MCPN765_HAWK_PPC_REG_BASE,
274 MCPN765_PROC_PCI_MEM_START,
275 MCPN765_PROC_PCI_MEM_END - HAWK_MPIC_SIZE,
276 MCPN765_PROC_PCI_IO_START,
277 MCPN765_PROC_PCI_IO_END,
278 MCPN765_PCI_MEM_END - HAWK_MPIC_SIZE + 1) != 0) {
279 printk("Could not initialize HAWK bridge\n");
282 /* VIA IDE BAR decoders are only 16-bits wide. PCI Auto Config
283 * will reassign the bars outside of 16-bit I/O space, which will
284 * "break" things. To prevent this, we'll set the IDE chip into
285 * legacy mode and seed the bars with their legacy addresses (in 16-bit
286 * I/O space). The Auto Config code will skip the IDE contoller in
287 * legacy mode, so our bar values will stick.
289 mcpn765_set_VIA_IDE_legacy();
291 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
293 /* Now that we've got 16-bit addresses in the bars, we can switch the
294 * IDE controller back into native mode so we can do "modern" resource
295 * and interrupt management.
297 mcpn765_set_VIA_IDE_native();
299 ppc_md.pcibios_fixup = mcpn765_pcibios_fixup;
300 ppc_md.pcibios_fixup_bus = NULL;
301 ppc_md.pci_swizzle = common_swizzle;
302 ppc_md.pci_map_irq = mcpn765_map_irq;
307 mcpn765_setup_arch(void)
309 struct pci_controller *hose;
311 if ( ppc_md.progress )
312 ppc_md.progress("mcpn765_setup_arch: enter", 0);
314 loops_per_jiffy = 50000000 / HZ;
316 #ifdef CONFIG_BLK_DEV_INITRD
318 ROOT_DEV = Root_RAM0;
321 #ifdef CONFIG_ROOT_NFS
324 ROOT_DEV = Root_SDA2;
327 #ifdef CONFIG_DUMMY_CONSOLE
328 conswitchp = &dummy_con;
331 if ( ppc_md.progress )
332 ppc_md.progress("mcpn765_setup_arch: find_bridges", 0);
334 /* Lookup PCI host bridges */
335 mcpn765_find_bridges();
337 hose = pci_bus_to_hose(0);
338 isa_io_base = (ulong)hose->io_base_virt;
340 TODC_INIT(TODC_TYPE_MK48T37,
341 (MCPN765_PHYS_NVRAM_AS0 - isa_io_base),
342 (MCPN765_PHYS_NVRAM_AS1 - isa_io_base),
343 (MCPN765_PHYS_NVRAM_DATA - isa_io_base),
346 OpenPIC_InitSenses = mcpn765_openpic_initsenses;
347 OpenPIC_NumInitSenses = sizeof(mcpn765_openpic_initsenses);
349 printk("Motorola MCG MCPN765 cPCI Non-System Board\n");
350 printk("MCPN765 port (MontaVista Software, Inc. (source@mvista.com))\n");
352 if ( ppc_md.progress )
353 ppc_md.progress("mcpn765_setup_arch: exit", 0);
362 request_region(0x00,0x20,"dma1");
363 request_region(0x20,0x20,"pic1");
364 request_region(0x40,0x20,"timer");
365 request_region(0x80,0x10,"dma page reg");
366 request_region(0xa0,0x20,"pic2");
367 request_region(0xc0,0x20,"dma2");
373 * Interrupt setup and service.
374 * Have MPIC on HAWK and cascaded 8259s on VIA 82586 cascaded to MPIC.
377 mcpn765_init_IRQ(void)
381 if ( ppc_md.progress )
382 ppc_md.progress("init_irq: enter", 0);
384 openpic_init(NUM_8259_INTERRUPTS);
385 openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
388 for(i=0; i < NUM_8259_INTERRUPTS; i++)
389 irq_desc[i].handler = &i8259_pic;
393 if ( ppc_md.progress )
394 ppc_md.progress("init_irq: exit", 0);
400 mcpn765_irq_canonicalize(u32 irq)
408 static unsigned long __init
409 mcpn765_find_end_of_memory(void)
411 return hawk_get_mem_size(MCPN765_HAWK_SMC_BASE);
417 io_block_mapping(0xfe800000, 0xfe800000, 0x00800000, _PAGE_IO);
421 mcpn765_reset_board(void)
425 /* set VIA IDE controller into native mode */
426 mcpn765_set_VIA_IDE_native();
428 /* Set exception prefix high - to the firmware */
429 _nmask_and_or_msr(0, MSR_IP);
431 out_8((u_char *)MCPN765_BOARD_MODRST_REG, 0x01);
437 mcpn765_restart(char *cmd)
439 volatile ulong i = 10000000;
441 mcpn765_reset_board();
444 panic("restart failed\n");
448 mcpn765_power_off(void)
463 mcpn765_show_cpuinfo(struct seq_file *m)
465 seq_printf(m, "vendor\t\t: Motorola MCG\n");
466 seq_printf(m, "machine\t\t: MCPN765\n");
472 * Set BAT 3 to map 0xf0000000 to end of physical memory space.
474 static __inline__ void
475 mcpn765_set_bat(void)
478 mtspr(DBAT1U, 0xfe8000fe);
479 mtspr(DBAT1L, 0xfe80002a);
484 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
485 unsigned long r6, unsigned long r7)
487 parse_bootinfo(find_bootinfo());
489 /* Map in board regs, etc. */
492 isa_mem_base = MCPN765_ISA_MEM_BASE;
493 pci_dram_offset = MCPN765_PCI_DRAM_OFFSET;
494 ISA_DMA_THRESHOLD = 0x00ffffff;
495 DMA_MODE_READ = 0x44;
496 DMA_MODE_WRITE = 0x48;
498 ppc_md.setup_arch = mcpn765_setup_arch;
499 ppc_md.show_cpuinfo = mcpn765_show_cpuinfo;
500 ppc_md.irq_canonicalize = mcpn765_irq_canonicalize;
501 ppc_md.init_IRQ = mcpn765_init_IRQ;
502 ppc_md.get_irq = openpic_get_irq;
503 ppc_md.init = mcpn765_init2;
505 ppc_md.restart = mcpn765_restart;
506 ppc_md.power_off = mcpn765_power_off;
507 ppc_md.halt = mcpn765_halt;
509 ppc_md.find_end_of_memory = mcpn765_find_end_of_memory;
510 ppc_md.setup_io_mappings = mcpn765_map_io;
512 ppc_md.time_init = todc_time_init;
513 ppc_md.set_rtc_time = todc_set_rtc_time;
514 ppc_md.get_rtc_time = todc_get_rtc_time;
515 ppc_md.calibrate_decr = todc_calibrate_decr;
517 ppc_md.nvram_read_val = todc_m48txx_read_val;
518 ppc_md.nvram_write_val = todc_m48txx_write_val;
520 ppc_md.heartbeat = NULL;
521 ppc_md.heartbeat_reset = 0;
522 ppc_md.heartbeat_count = 0;
524 #ifdef CONFIG_SERIAL_TEXT_DEBUG
525 ppc_md.progress = gen550_progress;
528 ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;