2 * This file contains low-level cache management functions
3 * used for sleep and CPU speed changes on Apple machines.
4 * (In fact the only thing that is Apple-specific is that we assume
5 * that we can read from ROM at physical address 0xfff00000.)
7 * Copyright (C) 2004 Paul Mackerras (paulus@samba.org) and
8 * Benjamin Herrenschmidt (benh@kernel.crashing.org)
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
17 #include <linux/config.h>
18 #include <asm/processor.h>
19 #include <asm/ppc_asm.h>
20 #include <asm/cputable.h>
23 * Flush and disable all data caches (dL1, L2, L3). This is used
24 * when going to sleep, when doing a PMU based cpufreq transition,
25 * or when "offlining" a CPU on SMP machines. This code is over
26 * paranoid, but I've had enough issues with various CPU revs and
27 * bugs that I decided it was worth beeing over cautious
30 _GLOBAL(flush_disable_caches)
33 END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
36 END_FTR_SECTION_IFSET(CPU_FTR_L2CR)
39 /* This is the code for G3 and 74[01]0 */
43 /* Turn off EE and DR in MSR */
45 rlwinm r0,r11,0,~MSR_EE
46 rlwinm r0,r0,0,~MSR_DR
51 /* Stop DST streams */
55 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
58 mfspr r8,SPRN_HID0 /* Save HID0 in r8 */
59 rlwinm r4,r8,0,12,10 /* Turn off HID0[DPM] */
61 mtspr SPRN_HID0,r4 /* Disable DPM */
74 /* disable / invalidate / enable L1 data */
76 rlwinm r0,r0,0,~HID0_DCE
80 ori r3,r3,HID0_DCE|HID0_DCI
88 /* Get the current enable bit of the L2CR into r4 */
90 /* Set to data-only (pre-745x bit) */
91 oris r3,r5,L2CR_L2DO@h
93 /* When disabling L2, code must be in L1 */
103 1: /* disp-flush L2. The interesting thing here is that the L2 can be
104 * up to 2Mb ... so using the ROM, we'll end up wrapping back to memory
105 * but that is probbaly fine. We disp-flush over 4Mb to be safe
116 rlwinm r5,r5,0,~L2CR_L2E
118 /* When disabling L2, code must be in L1 */
130 /* Invalidate L2. This is pre-745x, we clear the L2I bit ourselves */
131 oris r4,r5,L2CR_L2I@h
135 xoris r4,r4,L2CR_L2I@h
140 /* now disable the L1 data cache */
142 rlwinm r0,r0,0,~HID0_DCE
147 /* Restore HID0[DPM] to whatever it was before */
152 /* restore DR and EE */
160 /* This code is for 745x processors */
162 /* Turn off EE and DR in MSR */
164 rlwinm r0,r11,0,~MSR_EE
165 rlwinm r0,r0,0,~MSR_DR
170 /* Stop prefetch streams */
174 /* Disable L2 prefetching */
190 /* Due to a bug with the HW flush on some CPU revs, we occasionally
191 * experience data corruption. I'm adding a displacement flush along
192 * with a dcbf loop over a few Mb to "help". The problem isn't totally
193 * fixed by this in theory, but at least, in practice, I couldn't reproduce
194 * it even with a big hammer...
202 addi r4,r4,32 /* Go to start of next cache line */
206 /* Now, flush the first 4MB of memory */
213 addi r4,r4,32 /* Go to start of next cache line */
216 /* Flush and disable the L1 data cache */
218 lis r3,0xfff0 /* read from ROM for displacement flush */
219 li r4,0xfe /* start with only way 0 unlocked */
220 li r5,128 /* 128 lines in each way */
226 2: lwz r0,0(r3) /* touch each cache line */
229 rlwinm r4,r4,1,24,30 /* move on to the next way */
231 cmpwi r4,0xff /* all done? */
233 /* now unlock the L1 data cache */
241 /* Flush the L2 cache using the hardware assist */
243 cmpwi r3,0 /* check if it is enabled first */
245 oris r0,r3,(L2CR_L2IO_745x|L2CR_L2DO_745x)@h
247 /* When disabling/locking L2, code must be in L1 */
249 1: mtspr L2CR,r0 /* lock the L2 cache */
259 ori r0,r3,L2CR_L2HWF_745x
261 mtspr L2CR,r0 /* set the hardware flush bit */
262 3: mfspr r0,L2CR /* wait for it to go to 0 */
263 andi. r0,r0,L2CR_L2HWF_745x
266 rlwinm r3,r3,0,~L2CR_L2E
268 /* When disabling L2, code must be in L1 */
270 1: mtspr L2CR,r3 /* disable the L2 cache */
280 oris r4,r3,L2CR_L2I@h
285 andis. r0,r4,L2CR_L2I@h
290 /* Flush the L3 cache using the hardware assist */
292 cmpwi r3,0 /* check if it is enabled */
294 oris r0,r3,L3CR_L3IO@h
297 mtspr L3CR,r0 /* lock the L3 cache */
302 mtspr L3CR,r0 /* set the hardware flush bit */
303 5: mfspr r0,L3CR /* wait for it to go to zero */
304 andi. r0,r0,L3CR_L3HWF
306 rlwinm r3,r3,0,~L3CR_L3E
308 mtspr L3CR,r3 /* disable the L3 cache */
312 1: mfspr r4,SPRN_L3CR
316 END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
318 6: mfspr r0,HID0 /* now disable the L1 data cache */
319 rlwinm r0,r0,0,~HID0_DCE
323 mtmsr r11 /* restore DR and EE */