2 * arch/ppc/platforms/pmac_feature.c
4 * Copyright (C) 1996-2001 Paul Mackerras (paulus@cs.anu.edu.au)
5 * Ben. Herrenschmidt (benh@kernel.crashing.org)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
14 * - Replace mdelay with some schedule loop if possible
15 * - Shorten some obfuscated delays on some routines (like modem
17 * - Refcount some clocks (see darwin)
18 * - Split split split...
21 #include <linux/config.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/spinlock.h>
28 #include <linux/adb.h>
29 #include <linux/pmu.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <asm/sections.h>
33 #include <asm/errno.h>
34 #include <asm/ohare.h>
35 #include <asm/heathrow.h>
36 #include <asm/keylargo.h>
37 #include <asm/uninorth.h>
40 #include <asm/machdep.h>
41 #include <asm/pmac_feature.h>
42 #include <asm/dbdma.h>
43 #include <asm/pci-bridge.h>
44 #include <asm/pmac_low_i2c.h>
49 #define DBG(fmt,...) printk(KERN_DEBUG fmt)
55 extern int powersave_lowspeed;
58 extern int powersave_nap;
59 extern struct pci_dev *k2_skiplist[2];
63 * We use a single global lock to protect accesses. Each driver has
64 * to take care of its own locking
66 static spinlock_t feature_lock __pmacdata = SPIN_LOCK_UNLOCKED;
68 #define LOCK(flags) spin_lock_irqsave(&feature_lock, flags);
69 #define UNLOCK(flags) spin_unlock_irqrestore(&feature_lock, flags);
73 * Instance of some macio stuffs
75 struct macio_chip macio_chips[MAX_MACIO_CHIPS] __pmacdata;
77 struct macio_chip* __pmac
78 macio_find(struct device_node* child, int type)
83 for (i=0; i < MAX_MACIO_CHIPS && macio_chips[i].of_node; i++)
84 if (child == macio_chips[i].of_node &&
85 (!type || macio_chips[i].type == type))
86 return &macio_chips[i];
87 child = child->parent;
92 static const char* macio_names[] __pmacdata =
110 * Uninorth reg. access. Note that Uni-N regs are big endian
113 #define UN_REG(r) (uninorth_base + ((r) >> 2))
114 #define UN_IN(r) (in_be32(UN_REG(r)))
115 #define UN_OUT(r,v) (out_be32(UN_REG(r), (v)))
116 #define UN_BIS(r,v) (UN_OUT((r), UN_IN(r) | (v)))
117 #define UN_BIC(r,v) (UN_OUT((r), UN_IN(r) & ~(v)))
119 static struct device_node* uninorth_node __pmacdata;
120 static u32* uninorth_base __pmacdata;
121 static u32 uninorth_rev __pmacdata;
122 static int uninorth_u3 __pmacdata;
126 * For each motherboard family, we have a table of functions pointers
127 * that handle the various features.
130 typedef long (*feature_call)(struct device_node* node, long param, long value);
132 struct feature_table_entry {
133 unsigned int selector;
134 feature_call function;
139 const char* model_string;
140 const char* model_name;
142 struct feature_table_entry* features;
143 unsigned long board_flags;
145 static struct pmac_mb_def pmac_mb __pmacdata;
148 * Here are the chip specific feature functions
151 static inline int __pmac
152 simple_feature_tweak(struct device_node* node, int type, int reg, u32 mask, int value)
154 struct macio_chip* macio;
157 macio = macio_find(node, type);
162 MACIO_BIS(reg, mask);
164 MACIO_BIC(reg, mask);
165 (void)MACIO_IN32(reg);
171 #ifndef CONFIG_POWER4
174 ohare_htw_scc_enable(struct device_node* node, long param, long value)
176 struct macio_chip* macio;
177 unsigned long chan_mask;
183 macio = macio_find(node, 0);
186 if (!strcmp(node->name, "ch-a"))
187 chan_mask = MACIO_FLAG_SCCA_ON;
188 else if (!strcmp(node->name, "ch-b"))
189 chan_mask = MACIO_FLAG_SCCB_ON;
193 htw = (macio->type == macio_heathrow || macio->type == macio_paddington
194 || macio->type == macio_gatwick);
195 /* On these machines, the HRW_SCC_TRANS_EN_N bit mustn't be touched */
196 trans = (pmac_mb.model_id != PMAC_TYPE_YOSEMITE &&
197 pmac_mb.model_id != PMAC_TYPE_YIKES);
199 #ifdef CONFIG_ADB_PMU
200 if ((param & 0xfff) == PMAC_SCC_IRDA)
202 #endif /* CONFIG_ADB_PMU */
204 fcr = MACIO_IN32(OHARE_FCR);
205 /* Check if scc cell need enabling */
206 if (!(fcr & OH_SCC_ENABLE)) {
207 fcr |= OH_SCC_ENABLE;
209 /* Side effect: this will also power up the
210 * modem, but it's too messy to figure out on which
211 * ports this controls the tranceiver and on which
212 * it controls the modem
215 fcr &= ~HRW_SCC_TRANS_EN_N;
216 MACIO_OUT32(OHARE_FCR, fcr);
217 fcr |= (rmask = HRW_RESET_SCC);
218 MACIO_OUT32(OHARE_FCR, fcr);
220 fcr |= (rmask = OH_SCC_RESET);
221 MACIO_OUT32(OHARE_FCR, fcr);
224 (void)MACIO_IN32(OHARE_FCR);
228 MACIO_OUT32(OHARE_FCR, fcr);
230 if (chan_mask & MACIO_FLAG_SCCA_ON)
232 if (chan_mask & MACIO_FLAG_SCCB_ON)
234 MACIO_OUT32(OHARE_FCR, fcr);
235 macio->flags |= chan_mask;
237 if (param & PMAC_SCC_FLAG_XMON)
238 macio->flags |= MACIO_FLAG_SCC_LOCKED;
240 if (macio->flags & MACIO_FLAG_SCC_LOCKED)
243 fcr = MACIO_IN32(OHARE_FCR);
244 if (chan_mask & MACIO_FLAG_SCCA_ON)
246 if (chan_mask & MACIO_FLAG_SCCB_ON)
248 MACIO_OUT32(OHARE_FCR, fcr);
249 if ((fcr & (OH_SCCA_IO | OH_SCCB_IO)) == 0) {
250 fcr &= ~OH_SCC_ENABLE;
252 fcr |= HRW_SCC_TRANS_EN_N;
253 MACIO_OUT32(OHARE_FCR, fcr);
255 macio->flags &= ~(chan_mask);
258 #ifdef CONFIG_ADB_PMU
259 if ((param & 0xfff) == PMAC_SCC_IRDA)
261 #endif /* CONFIG_ADB_PMU */
267 ohare_floppy_enable(struct device_node* node, long param, long value)
269 return simple_feature_tweak(node, macio_ohare,
270 OHARE_FCR, OH_FLOPPY_ENABLE, value);
274 ohare_mesh_enable(struct device_node* node, long param, long value)
276 return simple_feature_tweak(node, macio_ohare,
277 OHARE_FCR, OH_MESH_ENABLE, value);
281 ohare_ide_enable(struct device_node* node, long param, long value)
285 /* For some reason, setting the bit in set_initial_features()
286 * doesn't stick. I'm still investigating... --BenH.
289 simple_feature_tweak(node, macio_ohare,
290 OHARE_FCR, OH_IOBUS_ENABLE, 1);
291 return simple_feature_tweak(node, macio_ohare,
292 OHARE_FCR, OH_IDE0_ENABLE, value);
294 return simple_feature_tweak(node, macio_ohare,
295 OHARE_FCR, OH_BAY_IDE_ENABLE, value);
302 ohare_ide_reset(struct device_node* node, long param, long value)
306 return simple_feature_tweak(node, macio_ohare,
307 OHARE_FCR, OH_IDE0_RESET_N, !value);
309 return simple_feature_tweak(node, macio_ohare,
310 OHARE_FCR, OH_IDE1_RESET_N, !value);
317 ohare_sleep_state(struct device_node* node, long param, long value)
319 struct macio_chip* macio = &macio_chips[0];
321 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
324 MACIO_BIC(OHARE_FCR, OH_IOBUS_ENABLE);
325 } else if (value == 0) {
326 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
333 heathrow_modem_enable(struct device_node* node, long param, long value)
335 struct macio_chip* macio;
339 macio = macio_find(node, macio_unknown);
342 gpio = MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1;
345 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio);
347 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
350 if (pmac_mb.model_id != PMAC_TYPE_YOSEMITE &&
351 pmac_mb.model_id != PMAC_TYPE_YIKES) {
354 MACIO_BIC(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
356 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
358 (void)MACIO_IN32(HEATHROW_FCR);
363 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1);
364 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
365 UNLOCK(flags); mdelay(250); LOCK(flags);
366 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio);
367 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
368 UNLOCK(flags); mdelay(250); LOCK(flags);
369 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1);
370 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
371 UNLOCK(flags); mdelay(250);
377 heathrow_floppy_enable(struct device_node* node, long param, long value)
379 return simple_feature_tweak(node, macio_unknown,
381 HRW_SWIM_ENABLE|HRW_BAY_FLOPPY_ENABLE,
386 heathrow_mesh_enable(struct device_node* node, long param, long value)
388 struct macio_chip* macio;
391 macio = macio_find(node, macio_unknown);
395 /* Set clear mesh cell enable */
397 MACIO_BIS(HEATHROW_FCR, HRW_MESH_ENABLE);
399 MACIO_BIC(HEATHROW_FCR, HRW_MESH_ENABLE);
400 (void)MACIO_IN32(HEATHROW_FCR);
402 /* Set/Clear termination power */
404 MACIO_BIC(HEATHROW_MBCR, 0x04000000);
406 MACIO_BIS(HEATHROW_MBCR, 0x04000000);
407 (void)MACIO_IN32(HEATHROW_MBCR);
415 heathrow_ide_enable(struct device_node* node, long param, long value)
419 return simple_feature_tweak(node, macio_unknown,
420 HEATHROW_FCR, HRW_IDE0_ENABLE, value);
422 return simple_feature_tweak(node, macio_unknown,
423 HEATHROW_FCR, HRW_BAY_IDE_ENABLE, value);
430 heathrow_ide_reset(struct device_node* node, long param, long value)
434 return simple_feature_tweak(node, macio_unknown,
435 HEATHROW_FCR, HRW_IDE0_RESET_N, !value);
437 return simple_feature_tweak(node, macio_unknown,
438 HEATHROW_FCR, HRW_IDE1_RESET_N, !value);
445 heathrow_bmac_enable(struct device_node* node, long param, long value)
447 struct macio_chip* macio;
450 macio = macio_find(node, 0);
455 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_IO_ENABLE);
456 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_RESET);
458 (void)MACIO_IN32(HEATHROW_FCR);
461 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_RESET);
463 (void)MACIO_IN32(HEATHROW_FCR);
467 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE);
474 heathrow_sound_enable(struct device_node* node, long param, long value)
476 struct macio_chip* macio;
479 /* B&W G3 and Yikes don't support that properly (the
480 * sound appear to never come back after beeing shut down).
482 if (pmac_mb.model_id == PMAC_TYPE_YOSEMITE ||
483 pmac_mb.model_id == PMAC_TYPE_YIKES)
486 macio = macio_find(node, 0);
491 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
492 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N);
494 (void)MACIO_IN32(HEATHROW_FCR);
497 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N);
498 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
504 static u32 save_fcr[6] __pmacdata;
505 static u32 save_mbcr __pmacdata;
506 static u32 save_gpio_levels[2] __pmacdata;
507 static u8 save_gpio_extint[KEYLARGO_GPIO_EXTINT_CNT] __pmacdata;
508 static u8 save_gpio_normal[KEYLARGO_GPIO_CNT] __pmacdata;
509 static u32 save_unin_clock_ctl __pmacdata;
510 static struct dbdma_regs save_dbdma[13] __pmacdata;
511 static struct dbdma_regs save_alt_dbdma[13] __pmacdata;
514 dbdma_save(struct macio_chip* macio, struct dbdma_regs* save)
518 /* Save state & config of DBDMA channels */
519 for (i=0; i<13; i++) {
520 volatile struct dbdma_regs* chan = (volatile struct dbdma_regs*)
521 (macio->base + ((0x8000+i*0x100)>>2));
522 save[i].cmdptr_hi = in_le32(&chan->cmdptr_hi);
523 save[i].cmdptr = in_le32(&chan->cmdptr);
524 save[i].intr_sel = in_le32(&chan->intr_sel);
525 save[i].br_sel = in_le32(&chan->br_sel);
526 save[i].wait_sel = in_le32(&chan->wait_sel);
531 dbdma_restore(struct macio_chip* macio, struct dbdma_regs* save)
535 /* Save state & config of DBDMA channels */
536 for (i=0; i<13; i++) {
537 volatile struct dbdma_regs* chan = (volatile struct dbdma_regs*)
538 (macio->base + ((0x8000+i*0x100)>>2));
539 out_le32(&chan->control, (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);
540 while (in_le32(&chan->status) & ACTIVE)
542 out_le32(&chan->cmdptr_hi, save[i].cmdptr_hi);
543 out_le32(&chan->cmdptr, save[i].cmdptr);
544 out_le32(&chan->intr_sel, save[i].intr_sel);
545 out_le32(&chan->br_sel, save[i].br_sel);
546 out_le32(&chan->wait_sel, save[i].wait_sel);
551 heathrow_sleep(struct macio_chip* macio, int secondary)
554 dbdma_save(macio, save_alt_dbdma);
555 save_fcr[2] = MACIO_IN32(0x38);
556 save_fcr[3] = MACIO_IN32(0x3c);
558 dbdma_save(macio, save_dbdma);
559 save_fcr[0] = MACIO_IN32(0x38);
560 save_fcr[1] = MACIO_IN32(0x3c);
561 save_mbcr = MACIO_IN32(0x34);
562 /* Make sure sound is shut down */
563 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N);
564 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
565 /* This seems to be necessary as well or the fan
566 * keeps coming up and battery drains fast */
567 MACIO_BIC(HEATHROW_FCR, HRW_IOBUS_ENABLE);
568 MACIO_BIC(HEATHROW_FCR, HRW_IDE0_RESET_N);
569 /* Make sure eth is down even if module or sleep
570 * won't work properly */
571 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE | HRW_BMAC_RESET);
573 /* Make sure modem is shut down */
574 MACIO_OUT8(HRW_GPIO_MODEM_RESET,
575 MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1);
576 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
577 MACIO_BIC(HEATHROW_FCR, OH_SCCA_IO|OH_SCCB_IO|HRW_SCC_ENABLE);
579 /* Let things settle */
580 (void)MACIO_IN32(HEATHROW_FCR);
584 heathrow_wakeup(struct macio_chip* macio, int secondary)
587 MACIO_OUT32(0x38, save_fcr[2]);
588 (void)MACIO_IN32(0x38);
590 MACIO_OUT32(0x3c, save_fcr[3]);
591 (void)MACIO_IN32(0x38);
593 dbdma_restore(macio, save_alt_dbdma);
595 MACIO_OUT32(0x38, save_fcr[0] | HRW_IOBUS_ENABLE);
596 (void)MACIO_IN32(0x38);
598 MACIO_OUT32(0x3c, save_fcr[1]);
599 (void)MACIO_IN32(0x38);
601 MACIO_OUT32(0x34, save_mbcr);
602 (void)MACIO_IN32(0x38);
604 dbdma_restore(macio, save_dbdma);
609 heathrow_sleep_state(struct device_node* node, long param, long value)
611 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
614 if (macio_chips[1].type == macio_gatwick)
615 heathrow_sleep(&macio_chips[0], 1);
616 heathrow_sleep(&macio_chips[0], 0);
617 } else if (value == 0) {
618 heathrow_wakeup(&macio_chips[0], 0);
619 if (macio_chips[1].type == macio_gatwick)
620 heathrow_wakeup(&macio_chips[0], 1);
626 core99_scc_enable(struct device_node* node, long param, long value)
628 struct macio_chip* macio;
630 unsigned long chan_mask;
633 macio = macio_find(node, 0);
636 if (!strcmp(node->name, "ch-a"))
637 chan_mask = MACIO_FLAG_SCCA_ON;
638 else if (!strcmp(node->name, "ch-b"))
639 chan_mask = MACIO_FLAG_SCCB_ON;
644 int need_reset_scc = 0;
645 int need_reset_irda = 0;
648 fcr = MACIO_IN32(KEYLARGO_FCR0);
649 /* Check if scc cell need enabling */
650 if (!(fcr & KL0_SCC_CELL_ENABLE)) {
651 fcr |= KL0_SCC_CELL_ENABLE;
654 if (chan_mask & MACIO_FLAG_SCCA_ON) {
655 fcr |= KL0_SCCA_ENABLE;
656 /* Don't enable line drivers for I2S modem */
657 if ((param & 0xfff) == PMAC_SCC_I2S1)
658 fcr &= ~KL0_SCC_A_INTF_ENABLE;
660 fcr |= KL0_SCC_A_INTF_ENABLE;
662 if (chan_mask & MACIO_FLAG_SCCB_ON) {
663 fcr |= KL0_SCCB_ENABLE;
664 /* Perform irda specific inits */
665 if ((param & 0xfff) == PMAC_SCC_IRDA) {
666 fcr &= ~KL0_SCC_B_INTF_ENABLE;
667 fcr |= KL0_IRDA_ENABLE;
668 fcr |= KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE;
669 fcr |= KL0_IRDA_SOURCE1_SEL;
670 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);
671 fcr &= ~(KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);
674 fcr |= KL0_SCC_B_INTF_ENABLE;
676 MACIO_OUT32(KEYLARGO_FCR0, fcr);
677 macio->flags |= chan_mask;
678 if (need_reset_scc) {
679 MACIO_BIS(KEYLARGO_FCR0, KL0_SCC_RESET);
680 (void)MACIO_IN32(KEYLARGO_FCR0);
684 MACIO_BIC(KEYLARGO_FCR0, KL0_SCC_RESET);
686 if (need_reset_irda) {
687 MACIO_BIS(KEYLARGO_FCR0, KL0_IRDA_RESET);
688 (void)MACIO_IN32(KEYLARGO_FCR0);
692 MACIO_BIC(KEYLARGO_FCR0, KL0_IRDA_RESET);
695 if (param & PMAC_SCC_FLAG_XMON)
696 macio->flags |= MACIO_FLAG_SCC_LOCKED;
698 if (macio->flags & MACIO_FLAG_SCC_LOCKED)
701 fcr = MACIO_IN32(KEYLARGO_FCR0);
702 if (chan_mask & MACIO_FLAG_SCCA_ON)
703 fcr &= ~KL0_SCCA_ENABLE;
704 if (chan_mask & MACIO_FLAG_SCCB_ON) {
705 fcr &= ~KL0_SCCB_ENABLE;
706 /* Perform irda specific clears */
707 if ((param & 0xfff) == PMAC_SCC_IRDA) {
708 fcr &= ~KL0_IRDA_ENABLE;
709 fcr &= ~(KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE);
710 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);
711 fcr &= ~(KL0_IRDA_SOURCE1_SEL|KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);
714 MACIO_OUT32(KEYLARGO_FCR0, fcr);
715 if ((fcr & (KL0_SCCA_ENABLE | KL0_SCCB_ENABLE)) == 0) {
716 fcr &= ~KL0_SCC_CELL_ENABLE;
717 MACIO_OUT32(KEYLARGO_FCR0, fcr);
719 macio->flags &= ~(chan_mask);
727 core99_modem_enable(struct device_node* node, long param, long value)
729 struct macio_chip* macio;
733 /* Hack for internal USB modem */
735 if (macio_chips[0].type != macio_keylargo)
737 node = macio_chips[0].of_node;
739 macio = macio_find(node, 0);
742 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET);
743 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE;
744 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA;
748 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
750 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
755 MACIO_BIC(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
757 (void)MACIO_IN32(KEYLARGO_FCR2);
760 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
765 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
766 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
767 UNLOCK(flags); mdelay(250); LOCK(flags);
768 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
769 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
770 UNLOCK(flags); mdelay(250); LOCK(flags);
771 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
772 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
773 UNLOCK(flags); mdelay(250);
779 pangea_modem_enable(struct device_node* node, long param, long value)
781 struct macio_chip* macio;
785 /* Hack for internal USB modem */
787 if (macio_chips[0].type != macio_pangea &&
788 macio_chips[0].type != macio_intrepid)
790 node = macio_chips[0].of_node;
792 macio = macio_find(node, 0);
795 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET);
796 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE;
797 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA;
801 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
803 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
808 MACIO_OUT8(KL_GPIO_MODEM_POWER,
809 KEYLARGO_GPIO_OUTPUT_ENABLE);
811 (void)MACIO_IN32(KEYLARGO_FCR2);
814 MACIO_OUT8(KL_GPIO_MODEM_POWER,
815 KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA);
820 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
821 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
822 UNLOCK(flags); mdelay(250); LOCK(flags);
823 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
824 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
825 UNLOCK(flags); mdelay(250); LOCK(flags);
826 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
827 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
828 UNLOCK(flags); mdelay(250);
834 core99_ata100_enable(struct device_node* node, long value)
837 struct pci_dev *pdev = NULL;
840 if (uninorth_rev < 0x24)
845 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100);
847 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100);
848 (void)UN_IN(UNI_N_CLOCK_CNTL);
853 if (pci_device_from_OF_node(node, &pbus, &pid) == 0)
854 pdev = pci_find_slot(pbus, pid);
857 pci_enable_device(pdev);
858 pci_set_master(pdev);
864 core99_ide_enable(struct device_node* node, long param, long value)
866 /* Bus ID 0 to 2 are KeyLargo based IDE, busID 3 is U2
871 return simple_feature_tweak(node, macio_unknown,
872 KEYLARGO_FCR1, KL1_EIDE0_ENABLE, value);
874 return simple_feature_tweak(node, macio_unknown,
875 KEYLARGO_FCR1, KL1_EIDE1_ENABLE, value);
877 return simple_feature_tweak(node, macio_unknown,
878 KEYLARGO_FCR1, KL1_UIDE_ENABLE, value);
880 return core99_ata100_enable(node, value);
887 core99_ide_reset(struct device_node* node, long param, long value)
891 return simple_feature_tweak(node, macio_unknown,
892 KEYLARGO_FCR1, KL1_EIDE0_RESET_N, !value);
894 return simple_feature_tweak(node, macio_unknown,
895 KEYLARGO_FCR1, KL1_EIDE1_RESET_N, !value);
897 return simple_feature_tweak(node, macio_unknown,
898 KEYLARGO_FCR1, KL1_UIDE_RESET_N, !value);
905 core99_gmac_enable(struct device_node* node, long param, long value)
911 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC);
913 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC);
914 (void)UN_IN(UNI_N_CLOCK_CNTL);
922 core99_gmac_phy_reset(struct device_node* node, long param, long value)
925 struct macio_chip* macio;
927 macio = &macio_chips[0];
928 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
929 macio->type != macio_intrepid)
933 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, KEYLARGO_GPIO_OUTPUT_ENABLE);
934 (void)MACIO_IN8(KL_GPIO_ETH_PHY_RESET);
938 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, /*KEYLARGO_GPIO_OUTPUT_ENABLE | */
939 KEYLARGO_GPIO_OUTOUT_DATA);
947 core99_sound_chip_enable(struct device_node* node, long param, long value)
949 struct macio_chip* macio;
952 macio = macio_find(node, 0);
956 /* Do a better probe code, screamer G4 desktops &
957 * iMacs can do that too, add a recalibrate in
960 if (pmac_mb.model_id == PMAC_TYPE_PISMO ||
961 pmac_mb.model_id == PMAC_TYPE_TITANIUM) {
964 MACIO_OUT8(KL_GPIO_SOUND_POWER,
965 KEYLARGO_GPIO_OUTPUT_ENABLE |
966 KEYLARGO_GPIO_OUTOUT_DATA);
968 MACIO_OUT8(KL_GPIO_SOUND_POWER,
969 KEYLARGO_GPIO_OUTPUT_ENABLE);
970 (void)MACIO_IN8(KL_GPIO_SOUND_POWER);
977 core99_airport_enable(struct device_node* node, long param, long value)
979 struct macio_chip* macio;
983 macio = macio_find(node, 0);
987 /* Hint: we allow passing of macio itself for the sake of the
990 if (node != macio->of_node &&
991 (!node->parent || node->parent != macio->of_node))
993 state = (macio->flags & MACIO_FLAG_AIRPORT_ON) != 0;
997 /* This code is a reproduction of OF enable-cardslot
998 * and init-wireless methods, slightly hacked until
1002 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 5);
1003 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf);
1007 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 4);
1008 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf);
1014 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16);
1015 (void)MACIO_IN32(KEYLARGO_FCR2);
1017 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xb, 0);
1018 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xb);
1020 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xa, 0x28);
1021 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xa);
1023 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xd, 0x28);
1024 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xd);
1026 MACIO_OUT8(KEYLARGO_GPIO_0+0xd, 0x28);
1027 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xd);
1029 MACIO_OUT8(KEYLARGO_GPIO_0+0xe, 0x28);
1030 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xe);
1033 MACIO_OUT32(0x1c000, 0);
1035 MACIO_OUT8(0x1a3e0, 0x41);
1036 (void)MACIO_IN8(0x1a3e0);
1039 MACIO_BIS(KEYLARGO_FCR2, KL2_CARDSEL_16);
1040 (void)MACIO_IN32(KEYLARGO_FCR2);
1044 macio->flags |= MACIO_FLAG_AIRPORT_ON;
1047 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16);
1048 (void)MACIO_IN32(KEYLARGO_FCR2);
1049 MACIO_OUT8(KL_GPIO_AIRPORT_0, 0);
1050 MACIO_OUT8(KL_GPIO_AIRPORT_1, 0);
1051 MACIO_OUT8(KL_GPIO_AIRPORT_2, 0);
1052 MACIO_OUT8(KL_GPIO_AIRPORT_3, 0);
1053 MACIO_OUT8(KL_GPIO_AIRPORT_4, 0);
1054 (void)MACIO_IN8(KL_GPIO_AIRPORT_4);
1057 macio->flags &= ~MACIO_FLAG_AIRPORT_ON;
1064 core99_reset_cpu(struct device_node* node, long param, long value)
1066 unsigned int reset_io = 0;
1067 unsigned long flags;
1068 struct macio_chip* macio;
1069 struct device_node* np;
1070 const int dflt_reset_lines[] = { KL_GPIO_RESET_CPU0,
1073 KL_GPIO_RESET_CPU3 };
1075 macio = &macio_chips[0];
1076 if (macio->type != macio_keylargo)
1079 np = find_path_device("/cpus");
1082 for (np = np->child; np != NULL; np = np->sibling) {
1083 u32* num = (u32 *)get_property(np, "reg", NULL);
1084 u32* rst = (u32 *)get_property(np, "soft-reset", NULL);
1085 if (num == NULL || rst == NULL)
1087 if (param == *num) {
1092 if (np == NULL || reset_io == 0)
1093 reset_io = dflt_reset_lines[param];
1096 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE);
1097 (void)MACIO_IN8(reset_io);
1099 MACIO_OUT8(reset_io, 0);
1100 (void)MACIO_IN8(reset_io);
1105 #endif /* CONFIG_SMP */
1108 core99_usb_enable(struct device_node* node, long param, long value)
1110 struct macio_chip* macio;
1111 unsigned long flags;
1116 macio = &macio_chips[0];
1117 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1118 macio->type != macio_intrepid)
1121 prop = (char *)get_property(node, "AAPL,clock-id", NULL);
1124 if (strncmp(prop, "usb0u048", 8) == 0)
1126 else if (strncmp(prop, "usb1u148", 8) == 0)
1128 else if (strncmp(prop, "usb2u248", 8) == 0)
1133 /* Sorry for the brute-force locking, but this is only used during
1134 * sleep and the timing seem to be critical
1140 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1));
1141 (void)MACIO_IN32(KEYLARGO_FCR0);
1145 MACIO_BIS(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE);
1146 } else if (number == 2) {
1147 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1));
1149 (void)MACIO_IN32(KEYLARGO_FCR0);
1152 MACIO_BIS(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE);
1153 } else if (number == 4) {
1154 MACIO_BIC(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1));
1156 (void)MACIO_IN32(KEYLARGO_FCR1);
1159 MACIO_BIS(KEYLARGO_FCR1, KL1_USB2_CELL_ENABLE);
1162 reg = MACIO_IN32(KEYLARGO_FCR4);
1163 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) |
1164 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number));
1165 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) |
1166 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1));
1167 MACIO_OUT32(KEYLARGO_FCR4, reg);
1168 (void)MACIO_IN32(KEYLARGO_FCR4);
1171 reg = MACIO_IN32(KEYLARGO_FCR3);
1172 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) |
1173 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0));
1174 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) |
1175 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1));
1176 MACIO_OUT32(KEYLARGO_FCR3, reg);
1177 (void)MACIO_IN32(KEYLARGO_FCR3);
1183 reg = MACIO_IN32(KEYLARGO_FCR4);
1184 reg |= KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) |
1185 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number);
1186 reg |= KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) |
1187 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1);
1188 MACIO_OUT32(KEYLARGO_FCR4, reg);
1189 (void)MACIO_IN32(KEYLARGO_FCR4);
1192 reg = MACIO_IN32(KEYLARGO_FCR3);
1193 reg |= KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) |
1194 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0);
1195 reg |= KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) |
1196 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1);
1197 MACIO_OUT32(KEYLARGO_FCR3, reg);
1198 (void)MACIO_IN32(KEYLARGO_FCR3);
1202 MACIO_BIC(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE);
1203 (void)MACIO_IN32(KEYLARGO_FCR0);
1205 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1));
1206 (void)MACIO_IN32(KEYLARGO_FCR0);
1207 } else if (number == 2) {
1208 MACIO_BIC(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE);
1209 (void)MACIO_IN32(KEYLARGO_FCR0);
1211 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1));
1212 (void)MACIO_IN32(KEYLARGO_FCR0);
1213 } else if (number == 4) {
1214 MACIO_BIC(KEYLARGO_FCR1, KL1_USB2_CELL_ENABLE);
1215 (void)MACIO_IN32(KEYLARGO_FCR1);
1217 MACIO_BIS(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1));
1218 (void)MACIO_IN32(KEYLARGO_FCR1);
1228 core99_firewire_enable(struct device_node* node, long param, long value)
1230 unsigned long flags;
1231 struct macio_chip* macio;
1233 macio = &macio_chips[0];
1234 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1235 macio->type != macio_intrepid)
1237 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED))
1242 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW);
1243 (void)UN_IN(UNI_N_CLOCK_CNTL);
1245 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW);
1246 (void)UN_IN(UNI_N_CLOCK_CNTL);
1255 core99_firewire_cable_power(struct device_node* node, long param, long value)
1257 unsigned long flags;
1258 struct macio_chip* macio;
1260 /* Trick: we allow NULL node */
1261 if ((pmac_mb.board_flags & PMAC_MB_HAS_FW_POWER) == 0)
1263 macio = &macio_chips[0];
1264 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1265 macio->type != macio_intrepid)
1267 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED))
1272 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 0);
1273 MACIO_IN8(KL_GPIO_FW_CABLE_POWER);
1276 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 4);
1277 MACIO_IN8(KL_GPIO_FW_CABLE_POWER); udelay(10);
1285 #endif /* CONFIG_POWER4 */
1288 core99_read_gpio(struct device_node* node, long param, long value)
1290 struct macio_chip* macio = &macio_chips[0];
1292 return MACIO_IN8(param);
1297 core99_write_gpio(struct device_node* node, long param, long value)
1299 struct macio_chip* macio = &macio_chips[0];
1301 MACIO_OUT8(param, (u8)(value & 0xff));
1305 #ifdef CONFIG_POWER4
1308 g5_gmac_enable(struct device_node* node, long param, long value)
1310 struct macio_chip* macio = &macio_chips[0];
1311 unsigned long flags;
1312 struct pci_dev *pdev;
1315 /* XXX FIXME: We should fix pci_device_from_OF_node here, and
1316 * get to a real pci_dev or we'll get into trouble with PCI
1317 * domains the day we get overlapping numbers (like if we ever
1318 * decide to show the HT root
1320 if (pci_device_from_OF_node(node, &pbus, &pid) == 0)
1321 pdev = pci_find_slot(pbus, pid);
1325 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE);
1327 k2_skiplist[0] = NULL;
1329 k2_skiplist[0] = pdev;
1331 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE);
1341 g5_fw_enable(struct device_node* node, long param, long value)
1343 struct macio_chip* macio = &macio_chips[0];
1344 unsigned long flags;
1345 struct pci_dev *pdev;
1348 /* XXX FIXME: We should fix pci_device_from_OF_node here, and
1349 * get to a real pci_dev or we'll get into trouble with PCI
1350 * domains the day we get overlapping numbers (like if we ever
1351 * decide to show the HT root
1353 if (pci_device_from_OF_node(node, &pbus, &pid) == 0)
1354 pdev = pci_find_slot(pbus, pid);
1358 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE);
1360 k2_skiplist[1] = NULL;
1362 k2_skiplist[1] = pdev;
1364 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE);
1374 g5_mpic_enable(struct device_node* node, long param, long value)
1376 unsigned long flags;
1378 if (node->parent == NULL || strcmp(node->parent->name, "u3"))
1382 UN_BIS(U3_TOGGLE_REG, U3_MPIC_RESET | U3_MPIC_OUTPUT_ENABLE);
1390 g5_reset_cpu(struct device_node* node, long param, long value)
1392 unsigned int reset_io = 0;
1393 unsigned long flags;
1394 struct macio_chip* macio;
1395 struct device_node* np;
1397 macio = &macio_chips[0];
1398 if (macio->type != macio_keylargo2)
1401 np = find_path_device("/cpus");
1404 for (np = np->child; np != NULL; np = np->sibling) {
1405 u32* num = (u32 *)get_property(np, "reg", NULL);
1406 u32* rst = (u32 *)get_property(np, "soft-reset", NULL);
1407 if (num == NULL || rst == NULL)
1409 if (param == *num) {
1414 if (np == NULL || reset_io == 0)
1418 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE);
1419 (void)MACIO_IN8(reset_io);
1421 MACIO_OUT8(reset_io, 0);
1422 (void)MACIO_IN8(reset_io);
1427 #endif /* CONFIG_SMP */
1430 * This can be called from pmac_smp so isn't static
1432 * This takes the second CPU off the bus on dual CPU machines
1435 void __pmac g5_phy_disable_cpu1(void)
1437 UN_OUT(U3_API_PHY_CONFIG_1, 0);
1440 #endif /* CONFIG_POWER4 */
1442 #ifndef CONFIG_POWER4
1445 keylargo_shutdown(struct macio_chip* macio, int sleep_mode)
1451 MACIO_BIS(KEYLARGO_FCR0, KL0_USB_REF_SUSPEND);
1452 (void)MACIO_IN32(KEYLARGO_FCR0);
1456 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1457 KL0_SCC_CELL_ENABLE |
1458 KL0_IRDA_ENABLE | KL0_IRDA_CLK32_ENABLE |
1459 KL0_IRDA_CLK19_ENABLE);
1461 MACIO_BIC(KEYLARGO_MBCR, KL_MBCR_MB0_DEV_MASK);
1462 MACIO_BIS(KEYLARGO_MBCR, KL_MBCR_MB0_IDE_ENABLE);
1464 MACIO_BIC(KEYLARGO_FCR1,
1465 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT |
1466 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE |
1467 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1468 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1469 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
1470 KL1_EIDE0_ENABLE | KL1_EIDE0_RESET_N |
1471 KL1_EIDE1_ENABLE | KL1_EIDE1_RESET_N |
1474 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
1475 MACIO_BIC(KEYLARGO_FCR2, KL2_IOBUS_ENABLE);
1477 temp = MACIO_IN32(KEYLARGO_FCR3);
1478 if (macio->rev >= 2) {
1479 temp |= KL3_SHUTDOWN_PLL2X;
1481 temp |= KL3_SHUTDOWN_PLL_TOTAL;
1484 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
1485 KL3_SHUTDOWN_PLLKW35;
1487 temp |= KL3_SHUTDOWN_PLLKW12;
1488 temp &= ~(KL3_CLK66_ENABLE | KL3_CLK49_ENABLE | KL3_CLK45_ENABLE
1489 | KL3_CLK31_ENABLE | KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE);
1491 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_VIA_CLK16_ENABLE);
1492 MACIO_OUT32(KEYLARGO_FCR3, temp);
1494 /* Flush posted writes & wait a bit */
1495 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
1499 pangea_shutdown(struct macio_chip* macio, int sleep_mode)
1503 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1504 KL0_SCC_CELL_ENABLE |
1505 KL0_USB0_CELL_ENABLE | KL0_USB1_CELL_ENABLE);
1507 MACIO_BIC(KEYLARGO_FCR1,
1508 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT |
1509 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE |
1510 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1511 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1512 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
1514 if (pmac_mb.board_flags & PMAC_MB_MOBILE)
1515 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);
1517 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
1519 temp = MACIO_IN32(KEYLARGO_FCR3);
1520 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
1521 KL3_SHUTDOWN_PLLKW35;
1522 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE | KL3_CLK31_ENABLE
1523 | KL3_I2S0_CLK18_ENABLE | KL3_I2S1_CLK18_ENABLE);
1525 temp &= ~(KL3_VIA_CLK16_ENABLE | KL3_TIMER_CLK18_ENABLE);
1526 MACIO_OUT32(KEYLARGO_FCR3, temp);
1528 /* Flush posted writes & wait a bit */
1529 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
1533 intrepid_shutdown(struct macio_chip* macio, int sleep_mode)
1537 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1538 KL0_SCC_CELL_ENABLE |
1539 KL0_USB0_CELL_ENABLE | KL0_USB1_CELL_ENABLE);
1541 MACIO_BIC(KEYLARGO_FCR1,
1542 KL1_USB2_CELL_ENABLE |
1543 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1544 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1545 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE);
1546 if (pmac_mb.board_flags & PMAC_MB_MOBILE)
1547 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);
1549 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
1551 temp = MACIO_IN32(KEYLARGO_FCR3);
1552 temp |= KL3_IT_SHUTDOWN_PLL1 | KL3_IT_SHUTDOWN_PLL2 |
1553 KL3_IT_SHUTDOWN_PLL3;
1554 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE |
1555 KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE);
1557 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_IT_VIA_CLK32_ENABLE);
1558 MACIO_OUT32(KEYLARGO_FCR3, temp);
1560 /* Flush posted writes & wait a bit */
1561 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
1567 struct macio_chip* macio;
1570 macio = &macio_chips[0];
1571 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1572 macio->type != macio_intrepid)
1575 /* We power off the wireless slot in case it was not done
1576 * by the driver. We don't power it on automatically however
1578 if (macio->flags & MACIO_FLAG_AIRPORT_ON)
1579 core99_airport_enable(macio->of_node, 0, 0);
1581 /* We power off the FW cable. Should be done by the driver... */
1582 if (macio->flags & MACIO_FLAG_FW_SUPPORTED) {
1583 core99_firewire_enable(NULL, 0, 0);
1584 core99_firewire_cable_power(NULL, 0, 0);
1587 /* We make sure int. modem is off (in case driver lost it) */
1588 if (macio->type == macio_keylargo)
1589 core99_modem_enable(macio->of_node, 0, 0);
1591 pangea_modem_enable(macio->of_node, 0, 0);
1593 /* We make sure the sound is off as well */
1594 core99_sound_chip_enable(macio->of_node, 0, 0);
1597 * Save various bits of KeyLargo
1600 /* Save the state of the various GPIOs */
1601 save_gpio_levels[0] = MACIO_IN32(KEYLARGO_GPIO_LEVELS0);
1602 save_gpio_levels[1] = MACIO_IN32(KEYLARGO_GPIO_LEVELS1);
1603 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++)
1604 save_gpio_extint[i] = MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+i);
1605 for (i=0; i<KEYLARGO_GPIO_CNT; i++)
1606 save_gpio_normal[i] = MACIO_IN8(KEYLARGO_GPIO_0+i);
1609 if (macio->type == macio_keylargo)
1610 save_mbcr = MACIO_IN32(KEYLARGO_MBCR);
1611 save_fcr[0] = MACIO_IN32(KEYLARGO_FCR0);
1612 save_fcr[1] = MACIO_IN32(KEYLARGO_FCR1);
1613 save_fcr[2] = MACIO_IN32(KEYLARGO_FCR2);
1614 save_fcr[3] = MACIO_IN32(KEYLARGO_FCR3);
1615 save_fcr[4] = MACIO_IN32(KEYLARGO_FCR4);
1616 if (macio->type == macio_pangea || macio->type == macio_intrepid)
1617 save_fcr[5] = MACIO_IN32(KEYLARGO_FCR5);
1619 /* Save state & config of DBDMA channels */
1620 dbdma_save(macio, save_dbdma);
1623 * Turn off as much as we can
1625 if (macio->type == macio_pangea)
1626 pangea_shutdown(macio, 1);
1627 else if (macio->type == macio_intrepid)
1628 intrepid_shutdown(macio, 1);
1629 else if (macio->type == macio_keylargo)
1630 keylargo_shutdown(macio, 1);
1633 * Put the host bridge to sleep
1636 save_unin_clock_ctl = UN_IN(UNI_N_CLOCK_CNTL);
1637 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl &
1638 ~(UNI_N_CLOCK_CNTL_GMAC|UNI_N_CLOCK_CNTL_FW/*|UNI_N_CLOCK_CNTL_PCI*/));
1640 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING);
1641 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_SLEEP);
1644 * FIXME: A bit of black magic with OpenPIC (don't ask me why)
1646 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) {
1647 MACIO_BIS(0x506e0, 0x00400000);
1648 MACIO_BIS(0x506e0, 0x80000000);
1654 core99_wake_up(void)
1656 struct macio_chip* macio;
1659 macio = &macio_chips[0];
1660 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1661 macio->type != macio_intrepid)
1665 * Wakeup the host bridge
1667 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL);
1669 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING);
1676 if (macio->type == macio_keylargo) {
1677 MACIO_OUT32(KEYLARGO_MBCR, save_mbcr);
1678 (void)MACIO_IN32(KEYLARGO_MBCR); udelay(10);
1680 MACIO_OUT32(KEYLARGO_FCR0, save_fcr[0]);
1681 (void)MACIO_IN32(KEYLARGO_FCR0); udelay(10);
1682 MACIO_OUT32(KEYLARGO_FCR1, save_fcr[1]);
1683 (void)MACIO_IN32(KEYLARGO_FCR1); udelay(10);
1684 MACIO_OUT32(KEYLARGO_FCR2, save_fcr[2]);
1685 (void)MACIO_IN32(KEYLARGO_FCR2); udelay(10);
1686 MACIO_OUT32(KEYLARGO_FCR3, save_fcr[3]);
1687 (void)MACIO_IN32(KEYLARGO_FCR3); udelay(10);
1688 MACIO_OUT32(KEYLARGO_FCR4, save_fcr[4]);
1689 (void)MACIO_IN32(KEYLARGO_FCR4); udelay(10);
1690 if (macio->type == macio_pangea || macio->type == macio_intrepid) {
1691 MACIO_OUT32(KEYLARGO_FCR5, save_fcr[5]);
1692 (void)MACIO_IN32(KEYLARGO_FCR5); udelay(10);
1695 dbdma_restore(macio, save_dbdma);
1697 MACIO_OUT32(KEYLARGO_GPIO_LEVELS0, save_gpio_levels[0]);
1698 MACIO_OUT32(KEYLARGO_GPIO_LEVELS1, save_gpio_levels[1]);
1699 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++)
1700 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+i, save_gpio_extint[i]);
1701 for (i=0; i<KEYLARGO_GPIO_CNT; i++)
1702 MACIO_OUT8(KEYLARGO_GPIO_0+i, save_gpio_normal[i]);
1704 /* FIXME more black magic with OpenPIC ... */
1705 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) {
1706 MACIO_BIC(0x506e0, 0x00400000);
1707 MACIO_BIC(0x506e0, 0x80000000);
1710 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl);
1717 core99_sleep_state(struct device_node* node, long param, long value)
1719 /* Param == 1 means to enter the "fake sleep" mode that is
1720 * used for CPU speed switch
1724 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING);
1725 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_IDLE2);
1727 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL);
1729 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING);
1734 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
1737 return core99_sleep();
1738 else if (value == 0)
1739 return core99_wake_up();
1743 #endif /* CONFIG_POWER4 */
1746 generic_get_mb_info(struct device_node* node, long param, long value)
1749 case PMAC_MB_INFO_MODEL:
1750 return pmac_mb.model_id;
1751 case PMAC_MB_INFO_FLAGS:
1752 return pmac_mb.board_flags;
1753 case PMAC_MB_INFO_NAME:
1754 /* hack hack hack... but should work */
1755 *((const char **)value) = pmac_mb.model_name;
1766 /* Used on any machine
1768 static struct feature_table_entry any_features[] __pmacdata = {
1769 { PMAC_FTR_GET_MB_INFO, generic_get_mb_info },
1773 #ifndef CONFIG_POWER4
1775 /* OHare based motherboards. Currently, we only use these on the
1776 * 2400,3400 and 3500 series powerbooks. Some older desktops seem
1777 * to have issues with turning on/off those asic cells
1779 static struct feature_table_entry ohare_features[] __pmacdata = {
1780 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
1781 { PMAC_FTR_SWIM3_ENABLE, ohare_floppy_enable },
1782 { PMAC_FTR_MESH_ENABLE, ohare_mesh_enable },
1783 { PMAC_FTR_IDE_ENABLE, ohare_ide_enable},
1784 { PMAC_FTR_IDE_RESET, ohare_ide_reset},
1785 { PMAC_FTR_SLEEP_STATE, ohare_sleep_state },
1789 /* Heathrow desktop machines (Beige G3).
1790 * Separated as some features couldn't be properly tested
1791 * and the serial port control bits appear to confuse it.
1793 static struct feature_table_entry heathrow_desktop_features[] __pmacdata = {
1794 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
1795 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
1796 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
1797 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
1798 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
1802 /* Heathrow based laptop, that is the Wallstreet and mainstreet
1805 static struct feature_table_entry heathrow_laptop_features[] __pmacdata = {
1806 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
1807 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable },
1808 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
1809 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
1810 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
1811 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
1812 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
1813 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable },
1814 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state },
1818 /* Paddington based machines
1819 * The lombard (101) powerbook, first iMac models, B&W G3 and Yikes G4.
1821 static struct feature_table_entry paddington_features[] __pmacdata = {
1822 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
1823 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable },
1824 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
1825 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
1826 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
1827 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
1828 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
1829 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable },
1830 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state },
1834 /* Core99 & MacRISC 2 machines (all machines released since the
1835 * iBook (included), that is all AGP machines, except pangea
1836 * chipset. The pangea chipset is the "combo" UniNorth/KeyLargo
1837 * used on iBook2 & iMac "flow power".
1839 static struct feature_table_entry core99_features[] __pmacdata = {
1840 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
1841 { PMAC_FTR_MODEM_ENABLE, core99_modem_enable },
1842 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
1843 { PMAC_FTR_IDE_RESET, core99_ide_reset },
1844 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
1845 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
1846 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
1847 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
1848 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
1849 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
1850 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
1851 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
1853 { PMAC_FTR_RESET_CPU, core99_reset_cpu },
1854 #endif /* CONFIG_SMP */
1855 { PMAC_FTR_READ_GPIO, core99_read_gpio },
1856 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
1862 static struct feature_table_entry rackmac_features[] __pmacdata = {
1863 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
1864 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
1865 { PMAC_FTR_IDE_RESET, core99_ide_reset },
1866 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
1867 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
1868 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
1869 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
1870 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
1871 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
1873 { PMAC_FTR_RESET_CPU, core99_reset_cpu },
1874 #endif /* CONFIG_SMP */
1875 { PMAC_FTR_READ_GPIO, core99_read_gpio },
1876 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
1882 static struct feature_table_entry pangea_features[] __pmacdata = {
1883 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
1884 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable },
1885 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
1886 { PMAC_FTR_IDE_RESET, core99_ide_reset },
1887 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
1888 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
1889 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
1890 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
1891 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
1892 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
1893 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
1894 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
1895 { PMAC_FTR_READ_GPIO, core99_read_gpio },
1896 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
1900 /* Intrepid features
1902 static struct feature_table_entry intrepid_features[] __pmacdata = {
1903 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
1904 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable },
1905 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
1906 { PMAC_FTR_IDE_RESET, core99_ide_reset },
1907 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
1908 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
1909 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
1910 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
1911 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
1912 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
1913 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
1914 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
1915 { PMAC_FTR_READ_GPIO, core99_read_gpio },
1916 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
1920 #else /* CONFIG_POWER4 */
1924 static struct feature_table_entry g5_features[] __pmacdata = {
1925 { PMAC_FTR_GMAC_ENABLE, g5_gmac_enable },
1926 { PMAC_FTR_1394_ENABLE, g5_fw_enable },
1927 { PMAC_FTR_ENABLE_MPIC, g5_mpic_enable },
1929 { PMAC_FTR_RESET_CPU, g5_reset_cpu },
1930 #endif /* CONFIG_SMP */
1931 { PMAC_FTR_READ_GPIO, core99_read_gpio },
1932 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
1936 #endif /* CONFIG_POWER4 */
1938 static struct pmac_mb_def pmac_mb_defs[] __pmacdata = {
1939 /* Warning: ordering is important as some models may claim
1940 * beeing compatible with several types
1942 #ifndef CONFIG_POWER4
1943 { "AAPL,8500", "PowerMac 8500/8600",
1944 PMAC_TYPE_PSURGE, NULL,
1947 { "AAPL,9500", "PowerMac 9500/9600",
1948 PMAC_TYPE_PSURGE, NULL,
1951 { "AAPL,7200", "PowerMac 7200",
1952 PMAC_TYPE_PSURGE, NULL,
1955 { "AAPL,7300", "PowerMac 7200/7300",
1956 PMAC_TYPE_PSURGE, NULL,
1959 { "AAPL,7500", "PowerMac 7500",
1960 PMAC_TYPE_PSURGE, NULL,
1963 { "AAPL,ShinerESB", "Apple Network Server",
1964 PMAC_TYPE_ANS, NULL,
1967 { "AAPL,e407", "Alchemy",
1968 PMAC_TYPE_ALCHEMY, NULL,
1971 { "AAPL,e411", "Gazelle",
1972 PMAC_TYPE_GAZELLE, NULL,
1975 { "AAPL,3400/2400", "PowerBook 3400",
1976 PMAC_TYPE_HOOPER, ohare_features,
1977 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
1979 { "AAPL,3500", "PowerBook 3500",
1980 PMAC_TYPE_KANGA, ohare_features,
1981 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
1983 { "AAPL,Gossamer", "PowerMac G3 (Gossamer)",
1984 PMAC_TYPE_GOSSAMER, heathrow_desktop_features,
1987 { "AAPL,PowerMac G3", "PowerMac G3 (Silk)",
1988 PMAC_TYPE_SILK, heathrow_desktop_features,
1991 { "AAPL,PowerBook1998", "PowerBook Wallstreet",
1992 PMAC_TYPE_WALLSTREET, heathrow_laptop_features,
1993 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
1995 { "PowerBook1,1", "PowerBook 101 (Lombard)",
1996 PMAC_TYPE_101_PBOOK, paddington_features,
1997 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
1999 { "iMac,1", "iMac (first generation)",
2000 PMAC_TYPE_ORIG_IMAC, paddington_features,
2003 { "PowerMac4,1", "iMac \"Flower Power\"",
2004 PMAC_TYPE_PANGEA_IMAC, pangea_features,
2007 { "PowerBook4,3", "iBook 2 rev. 2",
2008 PMAC_TYPE_IBOOK2, pangea_features,
2009 PMAC_MB_CAN_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2011 { "PowerBook4,2", "iBook 2",
2012 PMAC_TYPE_IBOOK2, pangea_features,
2013 PMAC_MB_CAN_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2015 { "PowerBook4,1", "iBook 2",
2016 PMAC_TYPE_IBOOK2, pangea_features,
2017 PMAC_MB_CAN_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2019 { "PowerMac4,4", "eMac",
2020 PMAC_TYPE_EMAC, core99_features,
2023 { "PowerMac4,2", "Flat panel iMac",
2024 PMAC_TYPE_FLAT_PANEL_IMAC, pangea_features,
2027 { "PowerMac1,1", "Blue&White G3",
2028 PMAC_TYPE_YOSEMITE, paddington_features,
2031 { "PowerMac1,2", "PowerMac G4 PCI Graphics",
2032 PMAC_TYPE_YIKES, paddington_features,
2035 { "PowerBook2,1", "iBook (first generation)",
2036 PMAC_TYPE_ORIG_IBOOK, core99_features,
2037 PMAC_MB_CAN_SLEEP | PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2039 { "PowerMac3,1", "PowerMac G4 AGP Graphics",
2040 PMAC_TYPE_SAWTOOTH, core99_features,
2043 { "PowerMac3,2", "PowerMac G4 AGP Graphics",
2044 PMAC_TYPE_SAWTOOTH, core99_features,
2047 { "PowerMac3,3", "PowerMac G4 AGP Graphics",
2048 PMAC_TYPE_SAWTOOTH, core99_features,
2051 { "PowerMac2,1", "iMac FireWire",
2052 PMAC_TYPE_FW_IMAC, core99_features,
2053 PMAC_MB_CAN_SLEEP | PMAC_MB_OLD_CORE99
2055 { "PowerMac2,2", "iMac FireWire",
2056 PMAC_TYPE_FW_IMAC, core99_features,
2057 PMAC_MB_CAN_SLEEP | PMAC_MB_OLD_CORE99
2059 { "PowerBook2,2", "iBook FireWire",
2060 PMAC_TYPE_FW_IBOOK, core99_features,
2061 PMAC_MB_CAN_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2063 { "PowerMac5,1", "PowerMac G4 Cube",
2064 PMAC_TYPE_CUBE, core99_features,
2067 { "PowerMac3,4", "PowerMac G4 Silver",
2068 PMAC_TYPE_QUICKSILVER, core99_features,
2071 { "PowerMac3,5", "PowerMac G4 Silver",
2072 PMAC_TYPE_QUICKSILVER, core99_features,
2075 { "PowerBook3,1", "PowerBook Pismo",
2076 PMAC_TYPE_PISMO, core99_features,
2077 PMAC_MB_CAN_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2079 { "PowerBook3,2", "PowerBook Titanium",
2080 PMAC_TYPE_TITANIUM, core99_features,
2081 PMAC_MB_CAN_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2083 { "PowerBook3,3", "PowerBook Titanium II",
2084 PMAC_TYPE_TITANIUM2, core99_features,
2085 PMAC_MB_CAN_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2087 { "PowerBook3,4", "PowerBook Titanium III",
2088 PMAC_TYPE_TITANIUM3, core99_features,
2089 PMAC_MB_CAN_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2091 { "PowerBook3,5", "PowerBook Titanium IV",
2092 PMAC_TYPE_TITANIUM4, core99_features,
2093 PMAC_MB_CAN_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2095 { "RackMac1,1", "XServe",
2096 PMAC_TYPE_RACKMAC, rackmac_features,
2099 { "RackMac1,2", "XServe rev. 2",
2100 PMAC_TYPE_RACKMAC, rackmac_features,
2103 { "PowerMac3,6", "PowerMac G4 Windtunnel",
2104 PMAC_TYPE_WINDTUNNEL, core99_features,
2107 { "PowerBook5,1", "PowerBook G4 17\"",
2108 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2109 PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2111 { "PowerBook5,2", "PowerBook G4 15\"",
2112 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2113 PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2115 { "PowerBook5,3", "PowerBook G4 17\"",
2116 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2117 PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2119 { "PowerBook6,1", "PowerBook G4 12\"",
2120 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2121 PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2123 { "PowerBook6,2", "PowerBook G4",
2124 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2125 PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2127 { "PowerBook6,3", "iBook G4",
2128 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2129 PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2131 { "PowerBook6,5", "iBook G4",
2132 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2133 PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2135 #else /* CONFIG_POWER4 */
2136 { "PowerMac7,2", "PowerMac G5",
2137 PMAC_TYPE_POWERMAC_G5, g5_features,
2140 #endif /* CONFIG_POWER4 */
2144 * The toplevel feature_call callback
2147 pmac_do_feature_call(unsigned int selector, ...)
2149 struct device_node* node;
2152 feature_call func = NULL;
2155 if (pmac_mb.features)
2156 for (i=0; pmac_mb.features[i].function; i++)
2157 if (pmac_mb.features[i].selector == selector) {
2158 func = pmac_mb.features[i].function;
2162 for (i=0; any_features[i].function; i++)
2163 if (any_features[i].selector == selector) {
2164 func = any_features[i].function;
2170 va_start(args, selector);
2171 node = (struct device_node*)va_arg(args, void*);
2172 param = va_arg(args, long);
2173 value = va_arg(args, long);
2176 return func(node, param, value);
2180 probe_motherboard(void)
2183 struct macio_chip* macio = &macio_chips[0];
2184 const char* model = NULL;
2185 struct device_node *dt;
2187 /* Lookup known motherboard type in device-tree. First try an
2188 * exact match on the "model" property, then try a "compatible"
2189 * match is none is found.
2191 dt = find_devices("device-tree");
2193 model = (const char *) get_property(dt, "model", NULL);
2194 for(i=0; model && i<(sizeof(pmac_mb_defs)/sizeof(struct pmac_mb_def)); i++) {
2195 if (strcmp(model, pmac_mb_defs[i].model_string) == 0) {
2196 pmac_mb = pmac_mb_defs[i];
2200 for(i=0; i<(sizeof(pmac_mb_defs)/sizeof(struct pmac_mb_def)); i++) {
2201 if (machine_is_compatible(pmac_mb_defs[i].model_string)) {
2202 pmac_mb = pmac_mb_defs[i];
2207 /* Fallback to selection depending on mac-io chip type */
2208 switch(macio->type) {
2209 #ifndef CONFIG_POWER4
2210 case macio_grand_central:
2211 pmac_mb.model_id = PMAC_TYPE_PSURGE;
2212 pmac_mb.model_name = "Unknown PowerSurge";
2215 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_OHARE;
2216 pmac_mb.model_name = "Unknown OHare-based";
2218 case macio_heathrow:
2219 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_HEATHROW;
2220 pmac_mb.model_name = "Unknown Heathrow-based";
2221 pmac_mb.features = heathrow_desktop_features;
2223 case macio_paddington:
2224 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PADDINGTON;
2225 pmac_mb.model_name = "Unknown Paddington-based";
2226 pmac_mb.features = paddington_features;
2228 case macio_keylargo:
2229 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_CORE99;
2230 pmac_mb.model_name = "Unknown Keylargo-based";
2231 pmac_mb.features = core99_features;
2234 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PANGEA;
2235 pmac_mb.model_name = "Unknown Pangea-based";
2236 pmac_mb.features = pangea_features;
2238 case macio_intrepid:
2239 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_INTREPID;
2240 pmac_mb.model_name = "Unknown Intrepid-based";
2241 pmac_mb.features = intrepid_features;
2243 #else /* CONFIG_POWER4 */
2244 case macio_keylargo2:
2245 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_K2;
2246 pmac_mb.model_name = "Unknown G5";
2247 pmac_mb.features = g5_features;
2249 #endif /* CONFIG_POWER4 */
2254 #ifndef CONFIG_POWER4
2255 /* Fixup Hooper vs. Comet */
2256 if (pmac_mb.model_id == PMAC_TYPE_HOOPER) {
2257 u32* mach_id_ptr = (u32*)ioremap(0xf3000034, 4);
2260 /* Here, I used to disable the media-bay on comet. It
2261 * appears this is wrong, the floppy connector is actually
2262 * a kind of media-bay and works with the current driver.
2264 if ((*mach_id_ptr) & 0x20000000UL)
2265 pmac_mb.model_id = PMAC_TYPE_COMET;
2266 iounmap(mach_id_ptr);
2268 #endif /* CONFIG_POWER4 */
2271 /* Set default value of powersave_nap on machines that support it.
2272 * It appears that uninorth rev 3 has a problem with it, we don't
2273 * enable it on those. In theory, the flush-on-lock property is
2274 * supposed to be set when not supported, but I'm not very confident
2275 * that all Apple OF revs did it properly, I do it the paranoid way.
2277 while (uninorth_base && uninorth_rev > 3) {
2278 struct device_node* np = find_path_device("/cpus");
2279 if (!np || !np->child) {
2280 printk(KERN_WARNING "Can't find CPU(s) in device tree !\n");
2284 /* Nap mode not supported on SMP */
2287 /* Nap mode not supported if flush-on-lock property is present */
2288 if (get_property(np, "flush-on-lock", NULL))
2291 printk(KERN_INFO "Processor NAP mode on idle enabled.\n");
2295 /* On CPUs that support it (750FX), lowspeed by default during
2298 powersave_lowspeed = 1;
2299 #endif /* CONFIG_6xx */
2300 #ifdef CONFIG_POWER4
2303 /* Check for "mobile" machine */
2304 if (model && (strncmp(model, "PowerBook", 9) == 0
2305 || strncmp(model, "iBook", 5) == 0))
2306 pmac_mb.board_flags |= PMAC_MB_MOBILE;
2309 printk(KERN_INFO "PowerMac motherboard: %s\n", pmac_mb.model_name);
2313 /* Initialize the Core99 UniNorth host bridge and memory controller
2316 probe_uninorth(void)
2318 unsigned long actrl;
2320 /* Locate core99 Uni-N */
2321 uninorth_node = of_find_node_by_name(NULL, "uni-n");
2323 if (uninorth_node == NULL) {
2324 uninorth_node = of_find_node_by_name(NULL, "u3");
2327 if (uninorth_node && uninorth_node->n_addrs > 0) {
2328 unsigned long address = uninorth_node->addrs[0].address;
2329 uninorth_base = ioremap(address, 0x40000);
2330 uninorth_rev = in_be32(UN_REG(UNI_N_VERSION));
2332 u3_ht = ioremap(address + U3_HT_CONFIG_BASE, 0x1000);
2334 uninorth_node = NULL;
2339 printk(KERN_INFO "Found %s memory controller & host bridge, revision: %d\n",
2340 uninorth_u3 ? "U3" : "UniNorth", uninorth_rev);
2341 printk(KERN_INFO "Mapped at 0x%08lx\n", (unsigned long)uninorth_base);
2343 /* Set the arbitrer QAck delay according to what Apple does
2345 if (uninorth_rev < 0x11) {
2346 actrl = UN_IN(UNI_N_ARB_CTRL) & ~UNI_N_ARB_CTRL_QACK_DELAY_MASK;
2347 actrl |= ((uninorth_rev < 3) ? UNI_N_ARB_CTRL_QACK_DELAY105 :
2348 UNI_N_ARB_CTRL_QACK_DELAY) << UNI_N_ARB_CTRL_QACK_DELAY_SHIFT;
2349 UN_OUT(UNI_N_ARB_CTRL, actrl);
2352 /* Some more magic as done by them in recent MacOS X on UniNorth
2353 * revs 1.5 to 2.O and Pangea. Seem to toggle the UniN Maxbus/PCI
2356 if ((uninorth_rev >= 0x11 && uninorth_rev <= 0x24) || uninorth_rev == 0xc0)
2357 UN_OUT(0x2160, UN_IN(0x2160) & 0x00ffffff);
2361 probe_one_macio(const char* name, const char* compat, int type)
2363 struct device_node* node;
2368 node = find_devices(name);
2369 if (!node || !node->n_addrs)
2373 if (device_is_compatible(node, compat))
2379 for(i=0; i<MAX_MACIO_CHIPS; i++) {
2380 if (!macio_chips[i].of_node)
2382 if (macio_chips[i].of_node == node)
2385 if (i >= MAX_MACIO_CHIPS) {
2386 printk(KERN_ERR "pmac_feature: Please increase MAX_MACIO_CHIPS !\n");
2387 printk(KERN_ERR "pmac_feature: %s skipped\n", node->full_name);
2390 base = (volatile u32*)ioremap(node->addrs[0].address, node->addrs[0].size);
2392 printk(KERN_ERR "pmac_feature: Can't map mac-io chip !\n");
2395 if (type == macio_keylargo) {
2396 u32* did = (u32 *)get_property(node, "device-id", NULL);
2397 if (*did == 0x00000025)
2398 type = macio_pangea;
2399 if (*did == 0x0000003e)
2400 type = macio_intrepid;
2402 macio_chips[i].of_node = node;
2403 macio_chips[i].type = type;
2404 macio_chips[i].base = base;
2405 macio_chips[i].flags = MACIO_FLAG_SCCB_ON | MACIO_FLAG_SCCB_ON;
2406 macio_chips[i].name = macio_names[type];
2407 revp = (u32 *)get_property(node, "revision-id", NULL);
2409 macio_chips[i].rev = *revp;
2410 printk(KERN_INFO "Found a %s mac-io controller, rev: %d, mapped at 0x%p\n",
2411 macio_names[type], macio_chips[i].rev, macio_chips[i].base);
2417 /* Warning, ordering is important */
2418 probe_one_macio("gc", NULL, macio_grand_central);
2419 probe_one_macio("ohare", NULL, macio_ohare);
2420 probe_one_macio("pci106b,7", NULL, macio_ohareII);
2421 probe_one_macio("mac-io", "keylargo", macio_keylargo);
2422 probe_one_macio("mac-io", "paddington", macio_paddington);
2423 probe_one_macio("mac-io", "gatwick", macio_gatwick);
2424 probe_one_macio("mac-io", "heathrow", macio_heathrow);
2425 probe_one_macio("mac-io", "K2-Keylargo", macio_keylargo2);
2427 /* Make sure the "main" macio chip appear first */
2428 if (macio_chips[0].type == macio_gatwick
2429 && macio_chips[1].type == macio_heathrow) {
2430 struct macio_chip temp = macio_chips[0];
2431 macio_chips[0] = macio_chips[1];
2432 macio_chips[1] = temp;
2434 if (macio_chips[0].type == macio_ohareII
2435 && macio_chips[1].type == macio_ohare) {
2436 struct macio_chip temp = macio_chips[0];
2437 macio_chips[0] = macio_chips[1];
2438 macio_chips[1] = temp;
2440 macio_chips[0].lbus.index = 0;
2441 macio_chips[1].lbus.index = 1;
2443 return (macio_chips[0].of_node == NULL) ? -ENODEV : 0;
2447 initial_serial_shutdown(struct device_node* np)
2450 struct slot_names_prop {
2455 int port_type = PMAC_SCC_ASYNC;
2458 slots = (struct slot_names_prop *)get_property(np, "slot-names", &len);
2459 conn = get_property(np, "AAPL,connector", &len);
2460 if (conn && (strcmp(conn, "infrared") == 0))
2461 port_type = PMAC_SCC_IRDA;
2462 else if (device_is_compatible(np, "cobalt"))
2464 else if (slots && slots->count > 0) {
2465 if (strcmp(slots->name, "IrDA") == 0)
2466 port_type = PMAC_SCC_IRDA;
2467 else if (strcmp(slots->name, "Modem") == 0)
2471 pmac_call_feature(PMAC_FTR_MODEM_ENABLE, np, 0, 0);
2472 pmac_call_feature(PMAC_FTR_SCC_ENABLE, np, port_type, 0);
2476 set_initial_features(void)
2478 struct device_node* np;
2480 /* That hack appears to be necessary for some StarMax motherboards
2481 * but I'm not too sure it was audited for side-effects on other
2482 * ohare based machines...
2483 * Since I still have difficulties figuring the right way to
2484 * differenciate them all and since that hack was there for a long
2485 * time, I'll keep it around
2487 if (macio_chips[0].type == macio_ohare && !find_devices("via-pmu")) {
2488 struct macio_chip* macio = &macio_chips[0];
2489 MACIO_OUT32(OHARE_FCR, STARMAX_FEATURES);
2490 } else if (macio_chips[0].type == macio_ohare) {
2491 struct macio_chip* macio = &macio_chips[0];
2492 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
2493 } else if (macio_chips[1].type == macio_ohare) {
2494 struct macio_chip* macio = &macio_chips[1];
2495 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
2498 #ifdef CONFIG_POWER4
2499 if (macio_chips[0].type == macio_keylargo2) {
2501 /* On SMP machines running UP, we have the second CPU eating
2502 * bus cycles. We need to take it off the bus. This is done
2503 * from pmac_smp for SMP kernels running on one CPU
2505 np = of_find_node_by_type(NULL, "cpu");
2507 np = of_find_node_by_type(np, "cpu");
2509 g5_phy_disable_cpu1();
2512 #endif /* CONFIG_SMP */
2513 /* Enable GMAC for now for PCI probing. It will be disabled
2514 * later on after PCI probe
2516 np = of_find_node_by_name(NULL, "ethernet");
2518 if (device_is_compatible(np, "K2-GMAC"))
2519 g5_gmac_enable(np, 0, 1);
2520 np = of_find_node_by_name(np, "ethernet");
2523 /* Enable FW before PCI probe. Will be disabled later on
2524 * Note: We should have a batter way to check that we are
2525 * dealing with uninorth internal cell and not a PCI cell
2526 * on the external PCI. The code below works though.
2528 np = of_find_node_by_name(NULL, "firewire");
2530 if (device_is_compatible(np, "pci106b,5811")) {
2531 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED;
2532 g5_fw_enable(np, 0, 1);
2534 np = of_find_node_by_name(np, "firewire");
2537 #else /* CONFIG_POWER4 */
2539 if (macio_chips[0].type == macio_keylargo ||
2540 macio_chips[0].type == macio_pangea ||
2541 macio_chips[0].type == macio_intrepid) {
2542 /* Enable GMAC for now for PCI probing. It will be disabled
2543 * later on after PCI probe
2545 np = of_find_node_by_name(NULL, "ethernet");
2548 && device_is_compatible(np->parent, "uni-north")
2549 && device_is_compatible(np, "gmac"))
2550 core99_gmac_enable(np, 0, 1);
2551 np = of_find_node_by_name(np, "ethernet");
2554 /* Enable FW before PCI probe. Will be disabled later on
2555 * Note: We should have a batter way to check that we are
2556 * dealing with uninorth internal cell and not a PCI cell
2557 * on the external PCI. The code below works though.
2559 np = of_find_node_by_name(NULL, "firewire");
2562 && device_is_compatible(np->parent, "uni-north")
2563 && (device_is_compatible(np, "pci106b,18") ||
2564 device_is_compatible(np, "pci106b,30") ||
2565 device_is_compatible(np, "pci11c1,5811"))) {
2566 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED;
2567 core99_firewire_enable(np, 0, 1);
2569 np = of_find_node_by_name(np, "firewire");
2572 /* Enable ATA-100 before PCI probe. */
2573 np = of_find_node_by_name(NULL, "ata-6");
2576 && device_is_compatible(np->parent, "uni-north")
2577 && device_is_compatible(np, "kauai-ata")) {
2578 core99_ata100_enable(np, 1);
2580 np = of_find_node_by_name(np, "ata-6");
2583 /* Switch airport off */
2584 np = find_devices("radio");
2586 if (np && np->parent == macio_chips[0].of_node) {
2587 macio_chips[0].flags |= MACIO_FLAG_AIRPORT_ON;
2588 core99_airport_enable(np, 0, 0);
2594 /* On all machines that support sound PM, switch sound off */
2595 if (macio_chips[0].of_node)
2596 pmac_do_feature_call(PMAC_FTR_SOUND_CHIP_ENABLE,
2597 macio_chips[0].of_node, 0, 0);
2599 /* While on some desktop G3s, we turn it back on */
2600 if (macio_chips[0].of_node && macio_chips[0].type == macio_heathrow
2601 && (pmac_mb.model_id == PMAC_TYPE_GOSSAMER ||
2602 pmac_mb.model_id == PMAC_TYPE_SILK)) {
2603 struct macio_chip* macio = &macio_chips[0];
2604 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
2605 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N);
2608 /* Hack for bumping clock speed on the new PowerBooks and the
2609 * iBook G4. This implements the "platform-do-clockspreading" OF
2610 * property. For safety, we also check the product ID in the
2611 * device-tree to make reasonably sure we won't set wrong values
2612 * in the clock chip.
2614 * Of course, ultimately, we have to implement a real parser for
2615 * the platform-do-* stuff...
2617 while (machine_is_compatible("PowerBook5,2") ||
2618 machine_is_compatible("PowerBook5,3") ||
2619 machine_is_compatible("PowerBook6,2") ||
2620 machine_is_compatible("PowerBook6,3")) {
2621 struct device_node *ui2c = of_find_node_by_type(NULL, "i2c");
2622 struct device_node *dt = of_find_node_by_name(NULL, "device-tree");
2625 int i, rc, changed = 0;
2629 productID = (u32 *)get_property(dt, "pid#", NULL);
2630 if (productID == NULL)
2633 struct device_node *p = of_get_parent(ui2c);
2634 if (p && !strcmp(p->name, "uni-n"))
2636 ui2c = of_find_node_by_type(np, "i2c");
2640 DBG("Trying to bump clock speed for PID: %08x...\n", *productID);
2641 rc = pmac_low_i2c_open(ui2c, 1);
2644 pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_combined);
2645 rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_read, 0x80, buffer, 9);
2646 DBG("read result: %d,", rc);
2648 pmac_low_i2c_close(ui2c);
2652 DBG(" %02x", buffer[i]);
2655 switch(*productID) {
2656 case 0x1182: /* AlBook 12" rev 2 */
2657 case 0x1183: /* iBook G4 12" */
2658 buffer[0] = (buffer[0] & 0x8f) | 0x70;
2659 buffer[2] = (buffer[2] & 0x7f) | 0x00;
2660 buffer[5] = (buffer[5] & 0x80) | 0x31;
2661 buffer[6] = (buffer[6] & 0x40) | 0xb0;
2662 buffer[7] = (buffer[7] & 0x00) | 0xc0;
2663 buffer[8] = (buffer[8] & 0x00) | 0x30;
2666 case 0x3142: /* AlBook 15" (ATI M10) */
2667 case 0x3143: /* AlBook 17" (ATI M10) */
2668 buffer[0] = (buffer[0] & 0xaf) | 0x50;
2669 buffer[2] = (buffer[2] & 0x7f) | 0x00;
2670 buffer[5] = (buffer[5] & 0x80) | 0x31;
2671 buffer[6] = (buffer[6] & 0x40) | 0xb0;
2672 buffer[7] = (buffer[7] & 0x00) | 0xd0;
2673 buffer[8] = (buffer[8] & 0x00) | 0x30;
2677 DBG("i2c-hwclock: Machine model not handled\n");
2681 pmac_low_i2c_close(ui2c);
2684 pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_stdsub);
2685 rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_write, 0x80, buffer, 9);
2686 DBG("write result: %d,", rc);
2687 pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_combined);
2688 rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_read, 0x80, buffer, 9);
2689 DBG("read result: %d,", rc);
2691 pmac_low_i2c_close(ui2c);
2695 DBG(" %02x", buffer[i]);
2696 pmac_low_i2c_close(ui2c);
2700 #endif /* CONFIG_POWER4 */
2702 /* On all machines, switch modem & serial ports off */
2703 np = find_devices("ch-a");
2705 initial_serial_shutdown(np);
2708 np = find_devices("ch-b");
2710 initial_serial_shutdown(np);
2716 pmac_feature_init(void)
2718 /* Detect the UniNorth memory controller */
2721 /* Probe mac-io controllers */
2722 if (probe_macios()) {
2723 printk(KERN_WARNING "No mac-io chip found\n");
2727 /* Setup low-level i2c stuffs */
2728 pmac_init_low_i2c();
2730 /* Probe machine type */
2731 if (probe_motherboard())
2732 printk(KERN_WARNING "Unknown PowerMac !\n");
2734 /* Set some initial features (turn off some chips that will
2735 * be later turned on)
2737 set_initial_features();
2741 pmac_feature_late_init(void)
2743 struct device_node* np;
2745 /* Request some resources late */
2747 request_OF_resource(uninorth_node, 0, NULL);
2748 np = find_devices("hammerhead");
2750 request_OF_resource(np, 0, NULL);
2751 np = find_devices("interrupt-controller");
2753 request_OF_resource(np, 0, NULL);
2757 device_initcall(pmac_feature_late_init);
2759 #ifdef CONFIG_POWER4
2761 static void dump_HT_speeds(char *name, u32 cfg, u32 frq)
2763 int freqs[16] = { 200,300,400,500,600,800,1000,0,0,0,0,0,0,0,0,0 };
2764 int bits[8] = { 8,16,0,32,2,4,0,0 };
2765 int freq = (frq >> 8) & 0xf;
2767 if (freqs[freq] == 0)
2768 printk("%s: Unknown HT link frequency %x\n", name, freq);
2770 printk("%s: %d MHz on main link, (%d in / %d out) bits width\n",
2772 bits[(cfg >> 28) & 0x7], bits[(cfg >> 24) & 0x7]);
2775 void __init pmac_check_ht_link(void)
2777 u32 ufreq, freq, ucfg, cfg;
2778 struct device_node *pcix_node;
2779 u8 px_bus, px_devfn;
2780 struct pci_controller *px_hose;
2782 (void)in_be32(u3_ht + U3_HT_LINK_COMMAND);
2783 ucfg = cfg = in_be32(u3_ht + U3_HT_LINK_CONFIG);
2784 ufreq = freq = in_be32(u3_ht + U3_HT_LINK_FREQ);
2785 dump_HT_speeds("U3 HyperTransport", cfg, freq);
2787 pcix_node = of_find_compatible_node(NULL, "pci", "pci-x");
2788 if (pcix_node == NULL) {
2789 printk("No PCI-X bridge found\n");
2792 if (pci_device_from_OF_node(pcix_node, &px_bus, &px_devfn) != 0) {
2793 printk("PCI-X bridge found but not matched to pci\n");
2796 px_hose = pci_find_hose_for_OF_device(pcix_node);
2797 if (px_hose == NULL) {
2798 printk("PCI-X bridge found but not matched to host\n");
2801 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc4, &cfg);
2802 early_read_config_dword(px_hose, px_bus, px_devfn, 0xcc, &freq);
2803 dump_HT_speeds("PCI-X HT Uplink", cfg, freq);
2804 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc8, &cfg);
2805 early_read_config_dword(px_hose, px_bus, px_devfn, 0xd0, &freq);
2806 dump_HT_speeds("PCI-X HT Downlink", cfg, freq);
2809 #endif /* CONFIG_POWER4 */