2 * Support for PCI bridges found on Power Macintoshes.
3 * At present the "bandit" and "chaos" bridges are supported.
4 * Fortunately you access configuration space in the same
5 * way with either bridge.
7 * Copyright (C) 1997 Paul Mackerras (paulus@cs.anu.edu.au)
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/delay.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
22 #include <asm/sections.h>
25 #include <asm/pci-bridge.h>
26 #include <asm/machdep.h>
27 #include <asm/pmac_feature.h>
33 extern void xmon_printf(const char *fmt, ...);
34 #define DBG(x...) xmon_printf(x)
36 #define DBG(x...) printk(x)
42 static int add_bridge(struct device_node *dev);
43 extern void pmac_check_ht_link(void);
45 /* XXX Could be per-controller, but I don't think we risk anything by
46 * assuming we won't have both UniNorth and Bandit */
47 static int has_uninorth;
49 static struct pci_controller *u3_agp;
50 #endif /* CONFIG_POWER4 */
52 extern u8 pci_cache_line_size;
54 struct pci_dev *k2_skiplist[2];
57 * Magic constants for enabling cache coherency in the bandit/PSX bridge.
59 #define BANDIT_DEVID_2 8
60 #define BANDIT_REVID 3
62 #define BANDIT_DEVNUM 11
63 #define BANDIT_MAGIC 0x50
64 #define BANDIT_COHERENT 0x40
67 fixup_one_level_bus_range(struct device_node *node, int higher)
69 for (; node != 0;node = node->sibling) {
71 unsigned int *class_code;
74 /* For PCI<->PCI bridges or CardBus bridges, we go down */
75 class_code = (unsigned int *) get_property(node, "class-code", 0);
76 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
77 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
79 bus_range = (int *) get_property(node, "bus-range", &len);
80 if (bus_range != NULL && len > 2 * sizeof(int)) {
81 if (bus_range[1] > higher)
82 higher = bus_range[1];
84 higher = fixup_one_level_bus_range(node->child, higher);
89 /* This routine fixes the "bus-range" property of all bridges in the
90 * system since they tend to have their "last" member wrong on macs
92 * Note that the bus numbers manipulated here are OF bus numbers, they
93 * are not Linux bus numbers.
96 fixup_bus_range(struct device_node *bridge)
101 /* Lookup the "bus-range" property for the hose */
102 bus_range = (int *) get_property(bridge, "bus-range", &len);
103 if (bus_range == NULL || len < 2 * sizeof(int)) {
104 printk(KERN_WARNING "Can't get bus-range for %s\n",
108 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
112 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers.
114 * The "Bandit" version is present in all early PCI PowerMacs,
115 * and up to the first ones using Grackle. Some machines may
116 * have 2 bandit controllers (2 PCI busses).
118 * "Chaos" is used in some "Bandit"-type machines as a bridge
119 * for the separate display bus. It is accessed the same
120 * way as bandit, but cannot be probed for devices. It therefore
121 * has its own config access functions.
123 * The "UniNorth" version is present in all Core99 machines
124 * (iBook, G4, new IMacs, and all the recent Apple machines).
125 * It contains 3 controllers in one ASIC.
127 * The U3 is the bridge used on G5 machines. It contains on
128 * AGP bus which is dealt with the old UniNorth access routines
129 * and an HyperTransport bus which uses its own set of access
133 #define MACRISC_CFA0(devfn, off) \
134 ((1 << (unsigned long)PCI_SLOT(dev_fn)) \
135 | (((unsigned long)PCI_FUNC(dev_fn)) << 8) \
136 | (((unsigned long)(off)) & 0xFCUL))
138 #define MACRISC_CFA1(bus, devfn, off) \
139 ((((unsigned long)(bus)) << 16) \
140 |(((unsigned long)(devfn)) << 8) \
141 |(((unsigned long)(off)) & 0xFCUL) \
144 static unsigned int __pmac
145 macrisc_cfg_access(struct pci_controller* hose, u8 bus, u8 dev_fn, u8 offset)
149 if (bus == hose->first_busno) {
150 if (dev_fn < (11 << 3))
152 caddr = MACRISC_CFA0(dev_fn, offset);
154 caddr = MACRISC_CFA1(bus, dev_fn, offset);
156 /* Uninorth will return garbage if we don't read back the value ! */
158 out_le32(hose->cfg_addr, caddr);
159 } while (in_le32(hose->cfg_addr) != caddr);
161 offset &= has_uninorth ? 0x07 : 0x03;
162 return (unsigned int)(hose->cfg_data) + (unsigned int)offset;
166 macrisc_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
169 struct pci_controller *hose = bus->sysdata;
172 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
174 return PCIBIOS_DEVICE_NOT_FOUND;
176 * Note: the caller has already checked that offset is
177 * suitably aligned and that len is 1, 2 or 4.
181 *val = in_8((u8 *)addr);
184 *val = in_le16((u16 *)addr);
187 *val = in_le32((u32 *)addr);
190 return PCIBIOS_SUCCESSFUL;
194 macrisc_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
197 struct pci_controller *hose = bus->sysdata;
200 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
202 return PCIBIOS_DEVICE_NOT_FOUND;
204 * Note: the caller has already checked that offset is
205 * suitably aligned and that len is 1, 2 or 4.
209 out_8((u8 *)addr, val);
210 (void) in_8((u8 *)addr);
213 out_le16((u16 *)addr, val);
214 (void) in_le16((u16 *)addr);
217 out_le32((u32 *)addr, val);
218 (void) in_le32((u32 *)addr);
221 return PCIBIOS_SUCCESSFUL;
224 static struct pci_ops macrisc_pci_ops =
231 * Verifiy that a specific (bus, dev_fn) exists on chaos
234 chaos_validate_dev(struct pci_bus *bus, int devfn, int offset)
236 struct device_node *np;
237 u32 *vendor, *device;
239 np = pci_busdev_to_OF_node(bus, devfn);
241 return PCIBIOS_DEVICE_NOT_FOUND;
243 vendor = (u32 *)get_property(np, "vendor-id", NULL);
244 device = (u32 *)get_property(np, "device-id", NULL);
245 if (vendor == NULL || device == NULL)
246 return PCIBIOS_DEVICE_NOT_FOUND;
248 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10)
249 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24))
250 return PCIBIOS_BAD_REGISTER_NUMBER;
252 return PCIBIOS_SUCCESSFUL;
256 chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
259 int result = chaos_validate_dev(bus, devfn, offset);
260 if (result == PCIBIOS_BAD_REGISTER_NUMBER)
262 if (result != PCIBIOS_SUCCESSFUL)
264 return macrisc_read_config(bus, devfn, offset, len, val);
268 chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
271 int result = chaos_validate_dev(bus, devfn, offset);
272 if (result != PCIBIOS_SUCCESSFUL)
274 return macrisc_write_config(bus, devfn, offset, len, val);
277 static struct pci_ops chaos_pci_ops =
286 * These versions of U3 HyperTransport config space access ops do not
287 * implement self-view of the HT host yet
290 #define U3_HT_CFA0(devfn, off) \
291 ((((unsigned long)devfn) << 8) | offset)
292 #define U3_HT_CFA1(bus, devfn, off) \
293 (U3_HT_CFA0(devfn, off) \
294 + (((unsigned long)bus) << 16) \
297 static unsigned long __pmac
298 u3_ht_cfg_access(struct pci_controller* hose, u8 bus, u8 devfn, u8 offset)
300 if (bus == hose->first_busno) {
301 /* For now, we don't self probe U3 HT bridge */
302 if (PCI_FUNC(devfn) != 0 || PCI_SLOT(devfn) > 7 ||
305 return ((unsigned long)hose->cfg_data) + U3_HT_CFA0(devfn, offset);
307 return ((unsigned long)hose->cfg_data) + U3_HT_CFA1(bus, devfn, offset);
311 u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
314 struct pci_controller *hose = bus->sysdata;
319 * When a device in K2 is powered down, we die on config
320 * cycle accesses. Fix that here.
323 if (k2_skiplist[i] && k2_skiplist[i]->bus == bus &&
324 k2_skiplist[i]->devfn == devfn) {
329 *val = 0xffff; break;
331 *val = 0xfffffffful; break;
333 return PCIBIOS_SUCCESSFUL;
336 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
338 return PCIBIOS_DEVICE_NOT_FOUND;
340 * Note: the caller has already checked that offset is
341 * suitably aligned and that len is 1, 2 or 4.
345 *val = in_8((u8 *)addr);
348 *val = in_le16((u16 *)addr);
351 *val = in_le32((u32 *)addr);
354 return PCIBIOS_SUCCESSFUL;
358 u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
361 struct pci_controller *hose = bus->sysdata;
366 * When a device in K2 is powered down, we die on config
367 * cycle accesses. Fix that here.
370 if (k2_skiplist[i] && k2_skiplist[i]->bus == bus &&
371 k2_skiplist[i]->devfn == devfn)
372 return PCIBIOS_SUCCESSFUL;
374 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
376 return PCIBIOS_DEVICE_NOT_FOUND;
378 * Note: the caller has already checked that offset is
379 * suitably aligned and that len is 1, 2 or 4.
383 out_8((u8 *)addr, val);
384 (void) in_8((u8 *)addr);
387 out_le16((u16 *)addr, val);
388 (void) in_le16((u16 *)addr);
391 out_le32((u32 *)addr, val);
392 (void) in_le32((u32 *)addr);
395 return PCIBIOS_SUCCESSFUL;
398 static struct pci_ops u3_ht_pci_ops =
404 #endif /* CONFIG_POWER4 */
407 * For a bandit bridge, turn on cache coherency if necessary.
408 * N.B. we could clean this up using the hose ops directly.
411 init_bandit(struct pci_controller *bp)
413 unsigned int vendev, magic;
416 /* read the word at offset 0 in config space for device 11 */
417 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID);
419 vendev = in_le32((volatile unsigned int *)bp->cfg_data);
420 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) +
421 PCI_VENDOR_ID_APPLE) {
422 /* read the revision id */
423 out_le32(bp->cfg_addr,
424 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID);
426 rev = in_8(bp->cfg_data);
427 if (rev != BANDIT_REVID)
429 "Unknown revision %d for bandit\n", rev);
430 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) {
431 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev);
435 /* read the word at offset 0x50 */
436 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC);
438 magic = in_le32((volatile unsigned int *)bp->cfg_data);
439 if ((magic & BANDIT_COHERENT) != 0)
441 magic |= BANDIT_COHERENT;
443 out_le32((volatile unsigned int *)bp->cfg_data, magic);
444 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n");
449 * Tweak the PCI-PCI bridge chip on the blue & white G3s.
454 struct device_node *p2pbridge;
455 struct pci_controller* hose;
459 /* XXX it would be better here to identify the specific
460 PCI-PCI bridge chip we have. */
461 if ((p2pbridge = find_devices("pci-bridge")) == 0
462 || p2pbridge->parent == NULL
463 || strcmp(p2pbridge->parent->name, "pci") != 0)
465 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) {
466 DBG("Can't find PCI infos for PCI<->PCI bridge\n");
469 /* Warning: At this point, we have not yet renumbered all busses.
470 * So we must use OF walking to find out hose
472 hose = pci_find_hose_for_OF_device(p2pbridge);
474 DBG("Can't find hose for PCI<->PCI bridge\n");
477 if (early_read_config_word(hose, bus, devfn,
478 PCI_BRIDGE_CONTROL, &val) < 0) {
479 printk(KERN_ERR "init_p2pbridge: couldn't read bridge control\n");
482 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT;
483 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val);
487 * Some Apple desktop machines have a NEC PD720100A USB2 controller
488 * on the motherboard. Open Firmware, on these, will disable the
489 * EHCI part of it so it behaves like a pair of OHCI's. This fixup
490 * code re-enables it ;)
495 struct device_node *nec;
497 for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) {
498 struct pci_controller *hose;
502 prop = (u32 *)get_property(nec, "vendor-id", NULL);
507 prop = (u32 *)get_property(nec, "device-id", NULL);
512 prop = (u32 *)get_property(nec, "reg", 0);
515 devfn = (prop[0] >> 8) & 0xff;
516 bus = (prop[0] >> 16) & 0xff;
517 if (PCI_FUNC(devfn) != 0)
519 hose = pci_find_hose_for_OF_device(nec);
522 early_read_config_dword(hose, bus, devfn, 0xe4, &data);
524 printk("Found NEC PD720100A USB2 chip with disabled EHCI, fixing up...\n");
526 early_write_config_dword(hose, bus, devfn, 0xe4, data);
527 early_write_config_byte(hose, bus, devfn | 2, PCI_INTERRUPT_LINE,
534 pmac_find_bridges(void)
536 struct device_node *np, *root;
537 struct device_node *ht = NULL;
539 root = of_find_node_by_path("/");
541 printk(KERN_CRIT "pmac_find_bridges: can't find root of device tree\n");
544 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
545 if (np->name == NULL)
547 if (strcmp(np->name, "bandit") == 0
548 || strcmp(np->name, "chaos") == 0
549 || strcmp(np->name, "pci") == 0) {
550 if (add_bridge(np) == 0)
553 if (strcmp(np->name, "ht") == 0) {
560 /* Probe HT last as it relies on the agp resources to be already
563 if (ht && add_bridge(ht) != 0)
569 /* There is something wrong with DMA on U3/HT. I haven't figured out
570 * the details yet, but if I set the cache line size to 128 bytes like
571 * it should, I'm getting memory corruption caused by devices like
572 * sungem (even without the MWI bit set, but maybe sungem doesn't
573 * care). Right now, it appears that setting up a 64 bytes line size
574 * works properly, 64 bytes beeing the max transfer size of HT, I
575 * suppose this is related the way HT/PCI are hooked together. I still
576 * need to dive into more specs though to be really sure of what's
579 * Ok, apparently, it's just that HT can't do more than 64 bytes
580 * transactions. MWI seem to be meaningless there as well, it may
581 * be worth nop'ing out pci_set_mwi too though I haven't done that
584 * Note that it's a bit different for whatever is in the AGP slot.
585 * For now, I don't care, but this can become a real issue, we
586 * should probably hook pci_set_mwi anyway to make sure it sets
587 * the real cache line size in there.
589 if (machine_is_compatible("MacRISC4"))
590 pci_cache_line_size = 16; /* 64 bytes */
592 pmac_check_ht_link();
593 #endif /* CONFIG_POWER4 */
596 #define GRACKLE_CFA(b, d, o) (0x80 | ((b) << 8) | ((d) << 16) \
597 | (((o) & ~3) << 24))
599 #define GRACKLE_PICR1_STG 0x00000040
600 #define GRACKLE_PICR1_LOOPSNOOP 0x00000010
602 /* N.B. this is called before bridges is initialized, so we can't
603 use grackle_pcibios_{read,write}_config_dword. */
604 static inline void grackle_set_stg(struct pci_controller* bp, int enable)
608 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
609 val = in_le32((volatile unsigned int *)bp->cfg_data);
610 val = enable? (val | GRACKLE_PICR1_STG) :
611 (val & ~GRACKLE_PICR1_STG);
612 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
613 out_le32((volatile unsigned int *)bp->cfg_data, val);
614 (void)in_le32((volatile unsigned int *)bp->cfg_data);
617 static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable)
621 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
622 val = in_le32((volatile unsigned int *)bp->cfg_data);
623 val = enable? (val | GRACKLE_PICR1_LOOPSNOOP) :
624 (val & ~GRACKLE_PICR1_LOOPSNOOP);
625 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
626 out_le32((volatile unsigned int *)bp->cfg_data, val);
627 (void)in_le32((volatile unsigned int *)bp->cfg_data);
631 setup_uninorth(struct pci_controller* hose, struct reg_property* addr)
633 pci_assign_all_busses = 1;
635 hose->ops = ¯isc_pci_ops;
636 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000);
637 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000);
638 /* We "know" that the bridge at f2000000 has the PCI slots. */
639 return addr->address == 0xf2000000;
643 setup_bandit(struct pci_controller* hose, struct reg_property* addr)
645 hose->ops = ¯isc_pci_ops;
646 hose->cfg_addr = (volatile unsigned int *)
647 ioremap(addr->address + 0x800000, 0x1000);
648 hose->cfg_data = (volatile unsigned char *)
649 ioremap(addr->address + 0xc00000, 0x1000);
654 setup_chaos(struct pci_controller* hose, struct reg_property* addr)
656 /* assume a `chaos' bridge */
657 hose->ops = &chaos_pci_ops;
658 hose->cfg_addr = (volatile unsigned int *)
659 ioremap(addr->address + 0x800000, 0x1000);
660 hose->cfg_data = (volatile unsigned char *)
661 ioremap(addr->address + 0xc00000, 0x1000);
667 setup_u3_agp(struct pci_controller* hose, struct reg_property* addr)
669 /* On G5, we move AGP up to high bus number so we don't need
670 * to reassign bus numbers for HT. If we ever have P2P bridges
671 * on AGP, we'll have to move pci_assign_all_busses to the
672 * pci_controller structure so we enable it for AGP and not for
674 * We hard code the address because of the different size of
675 * the reg address cell, we shall fix that by killing struct
676 * reg_property and using some accessor functions instead
678 hose->first_busno = 0xf0;
679 hose->last_busno = 0xff;
681 hose->ops = ¯isc_pci_ops;
682 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
683 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
689 setup_u3_ht(struct pci_controller* hose, struct reg_property *addr)
691 struct device_node *np = (struct device_node *)hose->arch_data;
694 hose->ops = &u3_ht_pci_ops;
696 /* We hard code the address because of the different size of
697 * the reg address cell, we shall fix that by killing struct
698 * reg_property and using some accessor functions instead
700 hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000);
703 * /ht node doesn't expose a "ranges" property, so we "remove" regions that
704 * have been allocated to AGP. So far, this version of the code doesn't assign
705 * any of the 0xfxxxxxxx "fine" memory regions to /ht.
706 * We need to fix that sooner or later by either parsing all child "ranges"
707 * properties or figuring out the U3 address space decoding logic and
708 * then read it's configuration register (if any).
710 hose->io_base_phys = 0xf4000000 + 0x00400000;
711 hose->io_base_virt = ioremap(hose->io_base_phys, 0x00400000);
712 isa_io_base = (unsigned long) hose->io_base_virt;
713 hose->io_resource.name = np->full_name;
714 hose->io_resource.start = 0;
715 hose->io_resource.end = 0x003fffff;
716 hose->io_resource.flags = IORESOURCE_IO;
717 hose->pci_mem_offset = 0;
718 hose->first_busno = 0;
719 hose->last_busno = 0xef;
720 hose->mem_resources[0].name = np->full_name;
721 hose->mem_resources[0].start = 0x80000000;
722 hose->mem_resources[0].end = 0xefffffff;
723 hose->mem_resources[0].flags = IORESOURCE_MEM;
725 if (u3_agp == NULL) {
726 DBG("U3 has no AGP, using full resource range\n");
730 /* We "remove" the AGP resources from the resources allocated to HT, that
731 * is we create "holes". However, that code does assumptions that so far
732 * happen to be true (cross fingers...), typically that resources in the
733 * AGP node are properly ordered
736 for (i=0; i<3; i++) {
737 struct resource *res = &u3_agp->mem_resources[i];
738 if (res->flags != IORESOURCE_MEM)
740 /* We don't care about "fine" resources */
741 if (res->start >= 0xf0000000)
743 /* Check if it's just a matter of "shrinking" us in one direction */
744 if (hose->mem_resources[cur].start == res->start) {
745 DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n",
746 cur, hose->mem_resources[cur].start, res->end + 1);
747 hose->mem_resources[cur].start = res->end + 1;
750 if (hose->mem_resources[cur].end == res->end) {
751 DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n",
752 cur, hose->mem_resources[cur].end, res->start - 1);
753 hose->mem_resources[cur].end = res->start - 1;
756 /* No, it's not the case, we need a hole */
758 /* not enough resources to make a hole, we drop part of the range */
759 printk(KERN_WARNING "Running out of resources for /ht host !\n");
760 hose->mem_resources[cur].end = res->start - 1;
764 DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n",
765 cur-1, res->start - 1, cur, res->end + 1);
766 hose->mem_resources[cur].name = np->full_name;
767 hose->mem_resources[cur].flags = IORESOURCE_MEM;
768 hose->mem_resources[cur].start = res->end + 1;
769 hose->mem_resources[cur].end = hose->mem_resources[cur-1].end;
770 hose->mem_resources[cur-1].end = res->start - 1;
774 #endif /* CONFIG_POWER4 */
777 setup_grackle(struct pci_controller *hose)
779 setup_indirect_pci(hose, 0xfec00000, 0xfee00000);
780 if (machine_is_compatible("AAPL,PowerBook1998"))
781 grackle_set_loop_snoop(hose, 1);
782 #if 0 /* Disabled for now, HW problems ??? */
783 grackle_set_stg(hose, 1);
788 * We assume that if we have a G3 powermac, we have one bridge called
789 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise,
790 * if we have one or more bandit or chaos bridges, we don't have a MPC106.
793 add_bridge(struct device_node *dev)
796 struct pci_controller *hose;
797 struct reg_property *addr;
802 DBG("Adding PCI host bridge %s\n", dev->full_name);
804 addr = (struct reg_property *) get_property(dev, "reg", &len);
805 if (addr == NULL || len < sizeof(*addr)) {
806 printk(KERN_WARNING "Can't use %s: no address\n",
810 bus_range = (int *) get_property(dev, "bus-range", &len);
811 if (bus_range == NULL || len < 2 * sizeof(int)) {
812 printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
816 hose = pcibios_alloc_controller();
819 hose->arch_data = dev;
820 hose->first_busno = bus_range ? bus_range[0] : 0;
821 hose->last_busno = bus_range ? bus_range[1] : 0xff;
825 if (device_is_compatible(dev, "u3-agp")) {
826 setup_u3_agp(hose, addr);
827 disp_name = "U3-AGP";
829 } else if (device_is_compatible(dev, "u3-ht")) {
830 setup_u3_ht(hose, addr);
834 #endif /* CONFIG_POWER4 */
835 if (device_is_compatible(dev, "uni-north")) {
836 primary = setup_uninorth(hose, addr);
837 disp_name = "UniNorth";
838 } else if (strcmp(dev->name, "pci") == 0) {
839 /* XXX assume this is a mpc106 (grackle) */
841 disp_name = "Grackle (MPC106)";
842 } else if (strcmp(dev->name, "bandit") == 0) {
843 setup_bandit(hose, addr);
844 disp_name = "Bandit";
845 } else if (strcmp(dev->name, "chaos") == 0) {
846 setup_chaos(hose, addr);
850 printk(KERN_INFO "Found %s PCI host bridge at 0x%08x. Firmware bus number: %d->%d\n",
851 disp_name, addr->address, hose->first_busno, hose->last_busno);
852 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
853 hose, hose->cfg_addr, hose->cfg_data);
855 /* Interpret the "ranges" property */
856 /* This also maps the I/O region and sets isa_io/mem_base */
857 pci_process_bridge_OF_ranges(hose, dev, primary);
859 /* Fixup "bus-range" OF property */
860 fixup_bus_range(dev);
866 pcibios_fixup_OF_interrupts(void)
868 struct pci_dev* dev = NULL;
871 * Open Firmware often doesn't initialize the
872 * PCI_INTERRUPT_LINE config register properly, so we
873 * should find the device node and apply the interrupt
874 * obtained from the OF device-tree
876 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
877 struct device_node *node;
878 node = pci_device_to_OF_node(dev);
879 /* this is the node, see if it has interrupts */
880 if (node && node->n_intrs > 0)
881 dev->irq = node->intrs[0].line;
882 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
887 pmac_pcibios_fixup(void)
889 /* Fixup interrupts according to OF tree */
890 pcibios_fixup_OF_interrupts();
894 pmac_pci_enable_device_hook(struct pci_dev *dev, int initial)
896 struct device_node* node;
900 node = pci_device_to_OF_node(dev);
902 /* We don't want to enable USB controllers absent from the OF tree
903 * (iBook second controller)
905 if (dev->vendor == PCI_VENDOR_ID_APPLE
906 && dev->device == PCI_DEVICE_ID_APPLE_KL_USB && !node)
912 uninorth_child = node->parent &&
913 device_is_compatible(node->parent, "uni-north");
915 /* Firewire & GMAC were disabled after PCI probe, the driver is
916 * claiming them, we must re-enable them now.
918 if (uninorth_child && !strcmp(node->name, "firewire") &&
919 (device_is_compatible(node, "pci106b,18") ||
920 device_is_compatible(node, "pci106b,30") ||
921 device_is_compatible(node, "pci11c1,5811"))) {
922 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1);
923 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1);
926 if (uninorth_child && !strcmp(node->name, "ethernet") &&
927 device_is_compatible(node, "gmac")) {
928 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1);
936 * Make sure PCI is correctly configured
938 * We use old pci_bios versions of the function since, by
939 * default, gmac is not powered up, and so will be absent
940 * from the kernel initial PCI lookup.
942 * Should be replaced by 2.4 new PCI mecanisms and really
943 * regiser the device.
945 pci_read_config_word(dev, PCI_COMMAND, &cmd);
946 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
947 pci_write_config_word(dev, PCI_COMMAND, cmd);
948 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16);
949 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
955 /* We power down some devices after they have been probed. They'll
956 * be powered back on later on
959 pmac_pcibios_after_init(void)
961 struct device_node* nd;
963 #ifdef CONFIG_BLK_DEV_IDE
964 struct pci_dev *dev = NULL;
966 /* OF fails to initialize IDE controllers on macs
967 * (and maybe other machines)
969 * Ideally, this should be moved to the IDE layer, but we need
970 * to check specifically with Andre Hedrick how to do it cleanly
971 * since the common IDE code seem to care about the fact that the
972 * BIOS may have disabled a controller.
976 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
977 if ((dev->class >> 16) == PCI_BASE_CLASS_STORAGE)
978 pci_enable_device(dev);
980 #endif /* CONFIG_BLK_DEV_IDE */
982 nd = find_devices("firewire");
984 if (nd->parent && (device_is_compatible(nd, "pci106b,18") ||
985 device_is_compatible(nd, "pci106b,30") ||
986 device_is_compatible(nd, "pci11c1,5811"))
987 && device_is_compatible(nd->parent, "uni-north")) {
988 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0);
989 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0);
993 nd = find_devices("ethernet");
995 if (nd->parent && device_is_compatible(nd, "gmac")
996 && device_is_compatible(nd->parent, "uni-north"))
997 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0);
1002 void pmac_pci_fixup_cardbus(struct pci_dev* dev)
1004 if (_machine != _MACH_Pmac)
1007 * Fix the interrupt routing on the various cardbus bridges
1008 * used on powerbooks
1010 if (dev->vendor != PCI_VENDOR_ID_TI)
1012 if (dev->device == PCI_DEVICE_ID_TI_1130 ||
1013 dev->device == PCI_DEVICE_ID_TI_1131) {
1015 /* Enable PCI interrupt */
1016 if (pci_read_config_byte(dev, 0x91, &val) == 0)
1017 pci_write_config_byte(dev, 0x91, val | 0x30);
1018 /* Disable ISA interrupt mode */
1019 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1020 pci_write_config_byte(dev, 0x92, val & ~0x06);
1022 if (dev->device == PCI_DEVICE_ID_TI_1210 ||
1023 dev->device == PCI_DEVICE_ID_TI_1211 ||
1024 dev->device == PCI_DEVICE_ID_TI_1410 ||
1025 dev->device == PCI_DEVICE_ID_TI_1510) {
1027 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA
1028 signal out the MFUNC0 pin */
1029 if (pci_read_config_byte(dev, 0x8c, &val) == 0)
1030 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2);
1031 /* Disable ISA interrupt mode */
1032 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1033 pci_write_config_byte(dev, 0x92, val & ~0x06);
1037 void pmac_pci_fixup_pciata(struct pci_dev* dev)
1042 * On PowerMacs, we try to switch any PCI ATA controller to
1045 if (_machine != _MACH_Pmac)
1047 /* Some controllers don't have the class IDE */
1048 if (dev->vendor == PCI_VENDOR_ID_PROMISE)
1049 switch(dev->device) {
1050 case PCI_DEVICE_ID_PROMISE_20246:
1051 case PCI_DEVICE_ID_PROMISE_20262:
1052 case PCI_DEVICE_ID_PROMISE_20263:
1053 case PCI_DEVICE_ID_PROMISE_20265:
1054 case PCI_DEVICE_ID_PROMISE_20267:
1055 case PCI_DEVICE_ID_PROMISE_20268:
1056 case PCI_DEVICE_ID_PROMISE_20269:
1057 case PCI_DEVICE_ID_PROMISE_20270:
1058 case PCI_DEVICE_ID_PROMISE_20271:
1059 case PCI_DEVICE_ID_PROMISE_20275:
1060 case PCI_DEVICE_ID_PROMISE_20276:
1061 case PCI_DEVICE_ID_PROMISE_20277:
1064 /* Others, check PCI class */
1065 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
1068 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1069 if ((progif & 5) != 5) {
1070 printk(KERN_INFO "Forcing PCI IDE into native mode: %s\n", pci_name(dev));
1071 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
1072 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
1074 printk(KERN_ERR "Rewrite of PROGIF failed !\n");
1079 * Disable second function on K2-SATA, it's broken
1080 * and disable IO BARs on first one
1082 void __pmac pmac_pci_fixup_k2_sata(struct pci_dev* dev)
1087 if (PCI_FUNC(dev->devfn) > 0) {
1088 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1089 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1090 pci_write_config_word(dev, PCI_COMMAND, cmd);
1091 for (i = 0; i < 6; i++) {
1092 dev->resource[i].start = dev->resource[i].end = 0;
1093 dev->resource[i].flags = 0;
1094 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0);
1097 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1098 cmd &= ~PCI_COMMAND_IO;
1099 pci_write_config_word(dev, PCI_COMMAND, cmd);
1100 for (i = 0; i < 5; i++) {
1101 dev->resource[i].start = dev->resource[i].end = 0;
1102 dev->resource[i].flags = 0;
1103 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0);