2 * arch/ppc/platforms/pplus.c
4 * Board and PCI setup routines for MCG PowerPlus
6 * Author: Randy Vinson <rvinson@mvista.com>
8 * Derived from original PowerPlus PReP work by
9 * Cort Dougan, Johnnie Peters, Matt Porter, and
12 * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
13 * the terms of the GNU General Public License version 2. This program
14 * is licensed "as is" without any warranty of any kind, whether express
18 #include <linux/config.h>
19 #include <linux/kernel.h>
20 #include <linux/interrupt.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/console.h>
24 #include <linux/pci.h>
25 #include <linux/irq.h>
26 #include <linux/ide.h>
27 #include <linux/seq_file.h>
28 #include <linux/root_dev.h>
30 #include <asm/system.h>
32 #include <asm/pgtable.h>
34 #include <asm/machdep.h>
35 #include <asm/prep_nvram.h>
37 #include <asm/i8259.h>
38 #include <asm/open_pic.h>
41 #include <asm/bootinfo.h>
51 extern char saved_command_line[];
53 extern void pplus_setup_hose(void);
54 extern void pplus_set_VIA_IDE_native(void);
56 extern unsigned long loops_per_jiffy;
57 unsigned char *Motherboard_map_name;
59 /* Tables for known hardware */
61 /* Motorola Mesquite */
63 mesquite_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
65 static char pci_irq_table[][4] =
67 * MPIC interrupts for various IDSEL values (MPIC IRQ0 =
68 * Linux IRQ16 (to leave room for ISA IRQs at 0-15).
69 * PCI IDSEL/INTPIN->INTLINE
73 {18, 0, 0, 0}, /* IDSEL 14 - Enet 0 */
74 { 0, 0, 0, 0}, /* IDSEL 15 - unused */
75 {19, 19, 19, 19}, /* IDSEL 16 - PMC Slot 1 */
76 { 0, 0, 0, 0}, /* IDSEL 17 - unused */
77 { 0, 0, 0, 0}, /* IDSEL 18 - unused */
78 { 0, 0, 0, 0}, /* IDSEL 19 - unused */
79 {24, 25, 26, 27}, /* IDSEL 20 - P2P bridge (to cPCI 1) */
80 { 0, 0, 0, 0}, /* IDSEL 21 - unused */
81 {28, 29, 30, 31} /* IDSEL 22 - P2P bridge (to cPCI 2) */
84 const long min_idsel = 14, max_idsel = 22, irqs_per_slot = 4;
85 return PCI_IRQ_TABLE_LOOKUP;
90 sitka_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
92 static char pci_irq_table[][4] =
94 * MPIC interrupts for various IDSEL values (MPIC IRQ0 =
95 * Linux IRQ16 (to leave room for ISA IRQs at 0-15).
96 * PCI IDSEL/INTPIN->INTLINE
100 {18, 0, 0, 0}, /* IDSEL 14 - Enet 0 */
101 { 0, 0, 0, 0}, /* IDSEL 15 - unused */
102 {25, 26, 27, 28}, /* IDSEL 16 - PMC Slot 1 */
103 {28, 25, 26, 27}, /* IDSEL 17 - PMC Slot 2 */
104 { 0, 0, 0, 0}, /* IDSEL 18 - unused */
105 { 0, 0, 0, 0}, /* IDSEL 19 - unused */
106 {20, 0, 0, 0} /* IDSEL 20 - P2P bridge (to cPCI) */
109 const long min_idsel = 14, max_idsel = 20, irqs_per_slot = 4;
110 return PCI_IRQ_TABLE_LOOKUP;
115 MTX_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
117 static char pci_irq_table[][4] =
119 * MPIC interrupts for various IDSEL values (MPIC IRQ0 =
120 * Linux IRQ16 (to leave room for ISA IRQs at 0-15).
121 * PCI IDSEL/INTPIN->INTLINE
125 {19, 0, 0, 0}, /* IDSEL 12 - SCSI */
126 { 0, 0, 0, 0}, /* IDSEL 13 - unused */
127 {18, 0, 0, 0}, /* IDSEL 14 - Enet */
128 { 0, 0, 0, 0}, /* IDSEL 15 - unused */
129 {25, 26, 27, 28}, /* IDSEL 16 - PMC Slot 1 */
130 {26, 27, 28, 25}, /* IDSEL 17 - PMC Slot 2 */
131 {27, 28, 25, 26} /* IDSEL 18 - PCI Slot 3 */
134 const long min_idsel = 12, max_idsel = 18, irqs_per_slot = 4;
135 return PCI_IRQ_TABLE_LOOKUP;
138 /* Motorola MTX Plus */
139 /* Secondary bus interrupt routing is not supported yet */
141 MTXplus_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
143 static char pci_irq_table[][4] =
145 * MPIC interrupts for various IDSEL values (MPIC IRQ0 =
146 * Linux IRQ16 (to leave room for ISA IRQs at 0-15).
147 * PCI IDSEL/INTPIN->INTLINE
151 {19, 0, 0, 0}, /* IDSEL 12 - SCSI */
152 { 0, 0, 0, 0}, /* IDSEL 13 - unused */
153 {18, 0, 0, 0}, /* IDSEL 14 - Enet 1 */
154 { 0, 0, 0, 0}, /* IDSEL 15 - unused */
155 {25, 26, 27, 28}, /* IDSEL 16 - PCI Slot 1P */
156 {26, 27, 28, 25}, /* IDSEL 17 - PCI Slot 2P */
157 {27, 28, 25, 26}, /* IDSEL 18 - PCI Slot 3P */
158 {26, 0, 0, 0}, /* IDSEL 19 - Enet 2 */
159 { 0, 0, 0, 0} /* IDSEL 20 - P2P Bridge */
162 const long min_idsel = 12, max_idsel = 20, irqs_per_slot = 4;
163 return PCI_IRQ_TABLE_LOOKUP;
167 Genesis2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
176 * PMC1 16 - IRQ9,10,11,12 = PMC1 A-D
177 * PMC2 17 - IRQ12,9,10,11 = A-D
180 * PCIX 20 - IRQ9,10,11,12 = PCI A-D
188 * PMC1 16 - IRQ9,10,11,12 = PMC A-D
189 * PMC2 17 - IRQ12,9,10,11 = PMC A-D
190 * PCIX 20 - IRQ9,10,11,12 = PMC A-D
198 * PMC1 16 - 9,10,11,12 = A-D
199 * PMC2 17 - 9,10,11,12 = B,C,D,A
202 static char pci_irq_table[][4] =
204 * MPIC interrupts for various IDSEL values (MPIC IRQ0 =
205 * Linux IRQ16 (to leave room for ISA IRQs at 0-15).
206 * PCI IDSEL/INTPIN->INTLINE
210 {19, 0, 0, 0}, /* IDSEL 12 - SCSI */
211 { 0, 0, 0, 0}, /* IDSEL 13 - Universe PCI - VME */
212 {18, 0, 0, 0}, /* IDSEL 14 - Enet 1 */
213 { 0, 0, 0, 0}, /* IDSEL 15 - unused */
214 {25, 26, 27, 28}, /* IDSEL 16 - PCI/PMC Slot 1P */
215 {28, 25, 26, 27}, /* IDSEL 17 - PCI/PMC Slot 2P */
216 {27, 28, 25, 26}, /* IDSEL 18 - PCI Slot 3P */
217 {26, 0, 0, 0}, /* IDSEL 19 - Enet 2 */
218 {25, 26, 27, 28} /* IDSEL 20 - P2P Bridge */
221 const long min_idsel = 12, max_idsel = 20, irqs_per_slot = 4;
222 return PCI_IRQ_TABLE_LOOKUP;
225 #define MOTOROLA_CPUTYPE_REG 0x800
226 #define MOTOROLA_BASETYPE_REG 0x803
227 #define MPIC_RAVEN_ID 0x48010000
228 #define MPIC_HAWK_ID 0x48030000
229 #define MOT_PROC2_BIT 0x800
231 static u_char pplus_openpic_initsenses[] __initdata = {
232 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* MVME2600_INT_SIO */
233 (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_FALCN_ECC_ERR */
234 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_PCI_ETHERNET */
235 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_SCSI */
236 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_PCI_GRAPHICS */
237 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME0 */
238 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME1 */
239 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME2 */
240 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME3 */
241 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTA */
242 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTB */
243 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTC */
244 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTD */
245 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG0 */
246 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG1 */
247 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),
251 int prep_keybd_present = 1;
255 /* 0x100 mask assumes for Raven and Hawk boards that the level/edge
258 /* 0x200 if this board has a Hawk chip. */
260 /* or'ed with 0x80 if this board should be checked for multi CPU */
263 int (*map_irq) (struct pci_dev *, unsigned char, unsigned char);
265 struct brd_info mot_info[] = {
266 {0x300, 0x00, 0x00, "MVME 2400", Genesis2_map_irq},
267 {0x1E0, 0xE0, 0x00, "Mesquite cPCI (MCP750)", mesquite_map_irq},
268 {0x1E0, 0xE1, 0x00, "Sitka cPCI (MCPN750)", sitka_map_irq},
269 {0x1E0, 0xE2, 0x00, "Mesquite cPCI (MCP750) w/ HAC", mesquite_map_irq},
270 {0x1E0, 0xF6, 0x80, "MTX Plus", MTXplus_map_irq},
271 {0x1E0, 0xF6, 0x81, "Dual MTX Plus", MTXplus_map_irq},
272 {0x1E0, 0xF7, 0x80, "MTX wo/ Parallel Port", MTX_map_irq},
273 {0x1E0, 0xF7, 0x81, "Dual MTX wo/ Parallel Port", MTX_map_irq},
274 {0x1E0, 0xF8, 0x80, "MTX w/ Parallel Port", MTX_map_irq},
275 {0x1E0, 0xF8, 0x81, "Dual MTX w/ Parallel Port", MTX_map_irq},
276 {0x1E0, 0xF9, 0x00, "MVME 2300", Genesis2_map_irq},
277 {0x1E0, 0xFA, 0x00, "MVME 2300SC/2600", Genesis2_map_irq},
278 {0x1E0, 0xFB, 0x00, "MVME 2600 with MVME712M", Genesis2_map_irq},
279 {0x1E0, 0xFC, 0x00, "MVME 2600/2700 with MVME761", Genesis2_map_irq},
280 {0x1E0, 0xFD, 0x80, "MVME 3600 with MVME712M", Genesis2_map_irq},
281 {0x1E0, 0xFD, 0x81, "MVME 4600 with MVME712M", Genesis2_map_irq},
282 {0x1E0, 0xFE, 0x80, "MVME 3600 with MVME761", Genesis2_map_irq},
283 {0x1E0, 0xFE, 0x81, "MVME 4600 with MVME761", Genesis2_map_irq},
284 {0x000, 0x00, 0x00, "", NULL}
287 void __init pplus_set_board_type(void)
289 unsigned char cpu_type;
290 unsigned char base_mod;
292 unsigned short devid;
293 unsigned long *ProcInfo = NULL;
295 cpu_type = inb(MOTOROLA_CPUTYPE_REG) & 0xF0;
296 base_mod = inb(MOTOROLA_BASETYPE_REG);
297 early_read_config_word(0, 0, 0, PCI_VENDOR_ID, &devid);
299 for (entry = 0; mot_info[entry].cpu_type != 0; entry++) {
300 /* Check for Hawk chip */
301 if (mot_info[entry].cpu_type & 0x200) {
302 if (devid != PCI_DEVICE_ID_MOTOROLA_HAWK)
305 /* store the system config register for later use. */
307 (unsigned long *)ioremap(PPLUS_SYS_CONFIG_REG, 4);
309 /* Check non hawk boards */
310 if ((mot_info[entry].cpu_type & 0xff) != cpu_type)
313 if (mot_info[entry].base_type == 0) {
318 if (mot_info[entry].base_type != base_mod)
322 if (!(mot_info[entry].max_cpu & 0x80)) {
327 /* processor 1 not present and max processor zero indicated */
328 if ((*ProcInfo & MOT_PROC2_BIT)
329 && !(mot_info[entry].max_cpu & 0x7f)) {
334 /* processor 1 present and max processor zero indicated */
335 if (!(*ProcInfo & MOT_PROC2_BIT)
336 && (mot_info[entry].max_cpu & 0x7f)) {
341 /* Indicate to system if this is a multiprocessor board */
342 if (!(*ProcInfo & MOT_PROC2_BIT))
347 /* No particular cpu type found - assume Mesquite (MCP750) */
350 Motherboard_map_name = (unsigned char *)mot_info[mot_entry].name;
351 ppc_md.pci_map_irq = mot_info[mot_entry].map_irq;
353 void __init pplus_pib_init(void)
356 unsigned short short_reg;
358 struct pci_dev *dev = NULL;
361 * Perform specific configuration for the Via Tech or
362 * or Winbond PCI-ISA-Bridge part.
364 if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
365 PCI_DEVICE_ID_VIA_82C586_1, dev))) {
367 * PPCBUG does not set the enable bits
368 * for the IDE device. Force them on here.
370 pci_read_config_byte(dev, 0x40, ®);
372 reg |= 0x03; /* IDE: Chip Enable Bits */
373 pci_write_config_byte(dev, 0x40, reg);
376 if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
377 PCI_DEVICE_ID_VIA_82C586_2,
378 dev)) && (dev->devfn = 0x5a)) {
379 /* Force correct USB interrupt */
381 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
384 if ((dev = pci_find_device(PCI_VENDOR_ID_WINBOND,
385 PCI_DEVICE_ID_WINBOND_83C553, dev))) {
386 /* Clear PCI Interrupt Routing Control Register. */
388 pci_write_config_word(dev, 0x44, short_reg);
389 /* Route IDE interrupts to IRQ 14 */
391 pci_write_config_byte(dev, 0x43, reg);
394 if ((dev = pci_find_device(PCI_VENDOR_ID_WINBOND,
395 PCI_DEVICE_ID_WINBOND_82C105, dev))) {
397 * Disable LEGIRQ mode so PCI INTS are routed
398 * directly to the 8259 and enable both channels
400 pci_write_config_dword(dev, 0x40, 0x10ff0033);
402 /* Force correct IDE interrupt */
404 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
408 void __init pplus_set_VIA_IDE_legacy(void)
410 unsigned short vend, dev;
412 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend);
413 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev);
415 if ((vend == PCI_VENDOR_ID_VIA) &&
416 (dev == PCI_DEVICE_ID_VIA_82C586_1)) {
419 /* put back original "standard" port base addresses */
420 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
421 PCI_BASE_ADDRESS_0, 0x1f1);
422 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
423 PCI_BASE_ADDRESS_1, 0x3f5);
424 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
425 PCI_BASE_ADDRESS_2, 0x171);
426 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
427 PCI_BASE_ADDRESS_3, 0x375);
428 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
429 PCI_BASE_ADDRESS_4, 0xcc01);
431 /* put into legacy mode */
432 early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
435 early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
440 void pplus_set_VIA_IDE_native(void)
442 unsigned short vend, dev;
444 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend);
445 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev);
447 if ((vend == PCI_VENDOR_ID_VIA) &&
448 (dev == PCI_DEVICE_ID_VIA_82C586_1)) {
451 /* put into native mode */
452 early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
455 early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
460 void __init pplus_pcibios_fixup(void)
464 unsigned short devid;
465 unsigned char base_mod;
467 printk(KERN_INFO "Setting PCI interrupts for a \"%s\"\n",
468 Motherboard_map_name);
470 /* Setup the Winbond or Via PIB */
473 /* Set up floppy in PS/2 mode */
474 outb(0x09, SIO_CONFIG_RA);
475 reg = inb(SIO_CONFIG_RD);
476 reg = (reg & 0x3F) | 0x40;
477 outb(reg, SIO_CONFIG_RD);
478 outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
480 /* This is a hack. If this is a 2300 or 2400 mot board then there is
481 * no keyboard controller and we have to indicate that.
484 early_read_config_word(0, 0, 0, PCI_VENDOR_ID, &devid);
485 base_mod = inb(MOTOROLA_BASETYPE_REG);
486 if ((devid == PCI_DEVICE_ID_MOTOROLA_HAWK) ||
487 (base_mod == 0xF9) || (base_mod == 0xFA) || (base_mod == 0xE1))
488 prep_keybd_present = 0;
491 void __init pplus_find_bridges(void)
493 struct pci_controller *hose;
495 hose = pcibios_alloc_controller();
499 hose->first_busno = 0;
500 hose->last_busno = 0xff;
502 hose->pci_mem_offset = PREP_ISA_MEM_BASE;
503 hose->io_base_virt = (void *)PREP_ISA_IO_BASE;
505 pci_init_resource(&hose->io_resource, PPLUS_PCI_IO_START,
506 PPLUS_PCI_IO_END, IORESOURCE_IO, "PCI host bridge");
507 pci_init_resource(&hose->mem_resources[0], PPLUS_PROC_PCI_MEM_START,
508 PPLUS_PROC_PCI_MEM_END, IORESOURCE_MEM,
511 hose->io_space.start = PPLUS_PCI_IO_START;
512 hose->io_space.end = PPLUS_PCI_IO_END;
513 hose->mem_space.start = PPLUS_PCI_MEM_START;
514 hose->mem_space.end = PPLUS_PCI_MEM_END - HAWK_MPIC_SIZE;
516 if (hawk_init(hose, PPLUS_HAWK_PPC_REG_BASE, PPLUS_PROC_PCI_MEM_START,
517 PPLUS_PROC_PCI_MEM_END - HAWK_MPIC_SIZE,
518 PPLUS_PROC_PCI_IO_START, PPLUS_PROC_PCI_IO_END,
519 PPLUS_PROC_PCI_MEM_END - HAWK_MPIC_SIZE + 1)
521 printk(KERN_CRIT "Could not initialize host bridge\n");
525 pplus_set_VIA_IDE_legacy();
527 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
529 ppc_md.pcibios_fixup = pplus_pcibios_fixup;
530 ppc_md.pci_swizzle = common_swizzle;
533 static int pplus_show_cpuinfo(struct seq_file *m)
535 seq_printf(m, "vendor\t\t: Motorola MCG\n");
536 seq_printf(m, "machine\t\t: %s\n", Motherboard_map_name);
541 static void __init pplus_setup_arch(void)
543 struct pci_controller *hose;
546 ppc_md.progress("pplus_setup_arch: enter", 0);
548 /* init to some ~sane value until calibrate_delay() runs */
549 loops_per_jiffy = 50000000;
552 ppc_md.progress("pplus_setup_arch: find_bridges", 0);
554 /* Setup PCI host bridge */
555 pplus_find_bridges();
557 hose = pci_bus_to_hose(0);
558 isa_io_base = (ulong) hose->io_base_virt;
561 ppc_md.progress("pplus_setup_arch: set_board_type", 0);
563 pplus_set_board_type();
565 /* Enable L2. Assume we don't need to flush -- Cort */
566 *(unsigned char *)(PPLUS_L2_CONTROL_REG) |= 3;
568 #ifdef CONFIG_BLK_DEV_INITRD
570 ROOT_DEV = Root_RAM0;
573 #ifdef CONFIG_ROOT_NFS
576 ROOT_DEV = Root_SDA2;
579 printk(KERN_INFO "Motorola PowerPlus Platform\n");
581 "Port by MontaVista Software, Inc. (source@mvista.com)\n");
583 #ifdef CONFIG_VGA_CONSOLE
584 /* remap the VGA memory */
585 vgacon_remap_base = (unsigned long)ioremap(PPLUS_ISA_MEM_BASE,
587 conswitchp = &vga_con;
588 #elif defined(CONFIG_DUMMY_CONSOLE)
589 conswitchp = &dummy_con;
591 #ifdef CONFIG_PPCBUG_NVRAM
592 /* Read in NVRAM data */
595 /* if no bootargs, look in NVRAM */
596 if (cmd_line[0] == '\0') {
598 bootargs = prep_nvram_get_var("bootargs");
599 if (bootargs != NULL) {
600 strcpy(cmd_line, bootargs);
602 strcpy(saved_command_line, cmd_line);
607 ppc_md.progress("pplus_setup_arch: exit", 0);
610 static void pplus_restart(char *cmd)
612 unsigned long i = 10000;
616 /* set VIA IDE controller into native mode */
617 pplus_set_VIA_IDE_native();
619 /* set exception prefix high - to the prom */
620 _nmask_and_or_msr(0, MSR_IP);
622 /* make sure bit 0 (reset) is a 0 */
623 outb(inb(0x92) & ~1L, 0x92);
624 /* signal a reset to system control port A - soft reset */
625 outb(inb(0x92) | 1, 0x92);
629 panic("restart failed\n");
632 static void pplus_halt(void)
634 /* set exception prefix high - to the prom */
635 _nmask_and_or_msr(MSR_EE, MSR_IP);
637 /* make sure bit 0 (reset) is a 0 */
638 outb(inb(0x92) & ~1L, 0x92);
639 /* signal a reset to system control port A - soft reset */
640 outb(inb(0x92) | 1, 0x92);
648 static void pplus_power_off(void)
653 static unsigned int pplus_irq_canonicalize(u_int irq)
661 static void __init pplus_init_IRQ(void)
666 ppc_md.progress("init_irq: enter", 0);
668 OpenPIC_InitSenses = pplus_openpic_initsenses;
669 OpenPIC_NumInitSenses = sizeof(pplus_openpic_initsenses);
671 if (OpenPIC_Addr != NULL) {
673 openpic_set_sources(0, 16, OpenPIC_Addr + 0x10000);
674 openpic_init(NUM_8259_INTERRUPTS);
675 openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
677 ppc_md.get_irq = openpic_get_irq;
680 for (i = 0; i < NUM_8259_INTERRUPTS; i++)
681 irq_desc[i].handler = &i8259_pic;
686 ppc_md.progress("init_irq: exit", 0);
689 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
693 static int pplus_ide_default_irq(unsigned long base)
705 static unsigned long pplus_ide_default_io_base(int index)
718 pplus_ide_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
719 unsigned long ctrl_port, int *irq)
721 unsigned long reg = data_port;
724 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
725 hw->io_ports[i] = reg;
730 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
732 hw->io_ports[IDE_CONTROL_OFFSET] =
733 hw->io_ports[IDE_DATA_OFFSET] + 0x206;
736 *irq = pplus_ide_default_irq(data_port);
741 /* PowerPlus (MTX) support */
742 static int __init smp_pplus_probe(void)
744 extern int mot_multi;
747 openpic_request_IPIs();
755 static void __init smp_pplus_kick_cpu(int nr)
757 *(unsigned long *)KERNELBASE = nr;
758 asm volatile ("dcbf 0,%0"::"r" (KERNELBASE):"memory");
759 printk(KERN_INFO "CPU1 reset, waiting\n");
762 static void __init smp_pplus_setup_cpu(int cpu_nr)
765 do_openpic_setup_cpu();
768 static struct smp_ops_t pplus_smp_ops = {
769 smp_openpic_message_pass,
773 .give_timebase = smp_generic_give_timebase,
774 .take_timebase = smp_generic_take_timebase,
776 #endif /* CONFIG_SMP */
779 static void print_dbat(int idx, u32 bat)
784 sprintf(str, "DBAT%c%c = 0x%08x\n",
785 (char)((idx - DBAT0U) / 2) + '0', (idx & 1) ? 'L' : 'U', bat);
786 ppc_md.progress(str, 0);
789 #define DUMP_DBAT(x) \
791 u32 __temp = mfspr(x);\
792 print_dbat(x, __temp); \
795 static void dump_dbats(void)
797 if (ppc_md.progress) {
810 static unsigned long __init pplus_find_end_of_memory(void)
815 ppc_md.progress("pplus_find_end_of_memory", 0);
821 total = hawk_get_mem_size(PPLUS_HAWK_SMC_BASE);
825 static void __init pplus_map_io(void)
827 io_block_mapping(PPLUS_ISA_IO_BASE, PPLUS_ISA_IO_BASE, 0x10000000,
829 io_block_mapping(0xfef80000, 0xfef80000, 0x00080000, _PAGE_IO);
832 static void __init pplus_init2(void)
835 request_region(PREP_NVRAM_AS0, 0x8, "nvram");
837 request_region(0x20, 0x20, "pic1");
838 request_region(0xa0, 0x20, "pic2");
839 request_region(0x00, 0x20, "dma1");
840 request_region(0x40, 0x20, "timer");
841 request_region(0x80, 0x10, "dma page reg");
842 request_region(0xc0, 0x20, "dma2");
846 * Set BAT 2 to access 0x8000000 so progress messages will work and set BAT 3
847 * to 0xf0000000 to access Falcon/Raven or Hawk registers
849 static __inline__ void pplus_set_bat(void)
851 /* wait for all outstanding memory accesses to complete */
855 mtspr(DBAT2U, 0x80001ffe);
856 mtspr(DBAT2L, 0x8000002a);
857 mtspr(DBAT3U, 0xf0001ffe);
858 mtspr(DBAT3L, 0xf000002a);
860 /* wait for updates */
865 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
866 unsigned long r6, unsigned long r7)
868 parse_bootinfo(find_bootinfo());
870 /* Map in board regs, etc. */
873 isa_io_base = PREP_ISA_IO_BASE;
874 isa_mem_base = PREP_ISA_MEM_BASE;
875 pci_dram_offset = PREP_PCI_DRAM_OFFSET;
876 ISA_DMA_THRESHOLD = 0x00ffffff;
877 DMA_MODE_READ = 0x44;
878 DMA_MODE_WRITE = 0x48;
880 ppc_md.setup_arch = pplus_setup_arch;
881 ppc_md.show_cpuinfo = pplus_show_cpuinfo;
882 ppc_md.irq_canonicalize = pplus_irq_canonicalize;
883 ppc_md.init_IRQ = pplus_init_IRQ;
884 /* this gets changed later on if we have an OpenPIC -- Cort */
885 ppc_md.get_irq = i8259_irq;
886 ppc_md.init = pplus_init2;
888 ppc_md.restart = pplus_restart;
889 ppc_md.power_off = pplus_power_off;
890 ppc_md.halt = pplus_halt;
892 TODC_INIT(TODC_TYPE_MK48T59, PREP_NVRAM_AS0, PREP_NVRAM_AS1,
895 ppc_md.time_init = todc_time_init;
896 ppc_md.set_rtc_time = todc_set_rtc_time;
897 ppc_md.get_rtc_time = todc_get_rtc_time;
898 ppc_md.calibrate_decr = todc_calibrate_decr;
899 ppc_md.nvram_read_val = todc_m48txx_read_val;
900 ppc_md.nvram_write_val = todc_m48txx_write_val;
902 ppc_md.find_end_of_memory = pplus_find_end_of_memory;
903 ppc_md.setup_io_mappings = pplus_map_io;
905 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
906 ppc_ide_md.default_irq = pplus_ide_default_irq;
907 ppc_ide_md.default_io_base = pplus_ide_default_io_base;
908 ppc_ide_md.ide_init_hwif = pplus_ide_init_hwif_ports;
911 #ifdef CONFIG_SERIAL_TEXT_DEBUG
912 ppc_md.progress = gen550_progress;
913 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
915 ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
918 ppc_md.smp_ops = &pplus_smp_ops;
919 #endif /* CONFIG_SMP */