2 * A collection of structures, addresses, and values associated with
3 * the Motorola MPC8260ADS/MPC8266ADS-PCI boards.
4 * Copied from the RPX-Classic and SBS8260 stuff.
6 * Copyright (c) 2001 Dan Malek (dan@mvista.com)
9 #ifndef __MACH_ADS8260_DEFS
10 #define __MACH_ADS8260_DEFS
12 #include <linux/config.h>
14 #include <asm/ppcboot.h>
16 /* Memory map is configured by the PROM startup.
17 * We just map a few things we need. The CSR is actually 4 byte-wide
18 * registers that can be accessed as 8-, 16-, or 32-bit values.
20 #define CPM_MAP_ADDR ((uint)0xf0000000)
21 #define BCSR_ADDR ((uint)0xf4500000)
22 #define BCSR_SIZE ((uint)(32 * 1024))
24 #define BOOTROM_RESTART_ADDR ((uint)0xff000104)
26 /* The ADS8260 has 16, 32-bit wide control/status registers, accessed
27 * only on word boundaries.
28 * Not all are used (yet), or are interesting to us (yet).
31 /* Things of interest in the CSR.
33 #define BCSR0_LED0 ((uint)0x02000000) /* 0 == on */
34 #define BCSR0_LED1 ((uint)0x01000000) /* 0 == on */
35 #define BCSR1_FETHIEN ((uint)0x08000000) /* 0 == enable */
36 #define BCSR1_FETH_RST ((uint)0x04000000) /* 0 == reset */
37 #define BCSR1_RS232_EN1 ((uint)0x02000000) /* 0 == enable */
38 #define BCSR1_RS232_EN2 ((uint)0x01000000) /* 0 == enable */
40 #define PHY_INTERRUPT SIU_INT_IRQ7
43 /* PCI interrupt controller */
44 #define PCI_INT_STAT_REG 0xF8200000
45 #define PCI_INT_MASK_REG 0xF8200004
46 #define PIRQA (NR_SIU_INTS + 0)
47 #define PIRQB (NR_SIU_INTS + 1)
48 #define PIRQC (NR_SIU_INTS + 2)
49 #define PIRQD (NR_SIU_INTS + 3)
52 * PCI memory map definitions for MPC8266ADS-PCI.
55 * local address PCI address target
56 * 0x80000000-0x9FFFFFFF 0x80000000-0x9FFFFFFF PCI mem with prefetch
57 * 0xA0000000-0xBFFFFFFF 0xA0000000-0xBFFFFFFF PCI mem w/o prefetch
58 * 0xF4000000-0xF7FFFFFF 0x00000000-0x03FFFFFF PCI IO
61 * local address PCI address target
62 * 0x00000000-0x1FFFFFFF 0x00000000-0x1FFFFFFF MPC8266 local memory
65 /* window for a PCI master to access MPC8266 memory */
66 #define PCI_SLV_MEM_LOCAL 0x00000000 /* Local base */
67 #define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
69 /* window for the processor to access PCI memory with prefetching */
70 #define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
71 #define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
72 #define PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
74 /* window for the processor to access PCI memory without prefetching */
75 #define PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
76 #define PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
77 #define PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
79 /* window for the processor to access PCI I/O */
80 #define PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */
81 #define PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
82 #define PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */
84 #define _IO_BASE PCI_MSTR_IO_LOCAL
85 #define _ISA_MEM_BASE PCI_MSTR_MEMIO_LOCAL
86 #define PCI_DRAM_OFFSET PCI_SLV_MEM_BUS
87 #endif /* CONFIG_PCI */
89 #endif /* __MACH_ADS8260_DEFS */
90 #endif /* __KERNEL__ */