3 * Originally by Gary Thomas
4 * rewritten and updated by Cort Dougan (cort@cs.nmt.edu)
6 * The motherboard routes/maps will disappear shortly. -- Cort
9 #include <linux/config.h>
10 #include <linux/types.h>
11 #include <linux/pci.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
15 #include <asm/sections.h>
16 #include <asm/byteorder.h>
18 #include <asm/ptrace.h>
20 #include <asm/pci-bridge.h>
21 #include <asm/residual.h>
23 #include <asm/machdep.h>
24 #include <asm/open_pic.h>
26 extern void (*setup_ibm_pci)(char *irq_lo, char *irq_hi);
28 /* Which PCI interrupt line does a given device [slot] use? */
29 /* Note: This really should be two dimensional based in slot/pin used */
30 static unsigned char *Motherboard_map;
31 unsigned char *Motherboard_map_name;
33 /* How is the 82378 PIRQ mapping setup? */
34 static unsigned char *Motherboard_routes;
36 static void (*Motherboard_non0)(struct pci_dev *);
38 static void Powerplus_Map_Non0(struct pci_dev *);
40 /* Used for Motorola to store system config register */
41 static unsigned long *ProcInfo;
43 /* Tables for known hardware */
45 /* Motorola PowerStackII - Utah */
46 static char Utah_pci_IRQ_map[23] __prepdata =
48 0, /* Slot 0 - unused */
49 0, /* Slot 1 - unused */
50 5, /* Slot 2 - SCSI - NCR825A */
51 0, /* Slot 3 - unused */
52 1, /* Slot 4 - Ethernet - DEC2114x */
53 0, /* Slot 5 - unused */
54 3, /* Slot 6 - PCI Card slot #1 */
55 4, /* Slot 7 - PCI Card slot #2 */
56 5, /* Slot 8 - PCI Card slot #3 */
57 5, /* Slot 9 - PCI Bridge */
58 /* added here in case we ever support PCI bridges */
59 /* Secondary PCI bus cards are at slot-9,6 & slot-9,7 */
60 0, /* Slot 10 - unused */
61 0, /* Slot 11 - unused */
62 5, /* Slot 12 - SCSI - NCR825A */
63 0, /* Slot 13 - unused */
64 3, /* Slot 14 - enet */
65 0, /* Slot 15 - unused */
66 2, /* Slot 16 - unused */
67 3, /* Slot 17 - unused */
68 5, /* Slot 18 - unused */
69 0, /* Slot 19 - unused */
70 0, /* Slot 20 - unused */
71 0, /* Slot 21 - unused */
72 0, /* Slot 22 - unused */
75 static char Utah_pci_IRQ_routes[] __prepdata =
77 0, /* Line 0 - Unused */
85 /* Motorola PowerStackII - Omaha */
86 /* no integrated SCSI or ethernet */
87 static char Omaha_pci_IRQ_map[23] __prepdata =
89 0, /* Slot 0 - unused */
90 0, /* Slot 1 - unused */
91 3, /* Slot 2 - Winbond EIDE */
92 0, /* Slot 3 - unused */
93 0, /* Slot 4 - unused */
94 0, /* Slot 5 - unused */
95 1, /* Slot 6 - PCI slot 1 */
96 2, /* Slot 7 - PCI slot 2 */
97 3, /* Slot 8 - PCI slot 3 */
98 4, /* Slot 9 - PCI slot 4 */ /* needs indirect access */
99 0, /* Slot 10 - unused */
100 0, /* Slot 11 - unused */
101 0, /* Slot 12 - unused */
102 0, /* Slot 13 - unused */
103 0, /* Slot 14 - unused */
104 0, /* Slot 15 - unused */
105 1, /* Slot 16 - PCI slot 1 */
106 2, /* Slot 17 - PCI slot 2 */
107 3, /* Slot 18 - PCI slot 3 */
108 4, /* Slot 19 - PCI slot 4 */ /* needs indirect access */
114 static char Omaha_pci_IRQ_routes[] __prepdata =
116 0, /* Line 0 - Unused */
123 /* Motorola PowerStack */
124 static char Blackhawk_pci_IRQ_map[19] __prepdata =
126 0, /* Slot 0 - unused */
127 0, /* Slot 1 - unused */
128 0, /* Slot 2 - unused */
129 0, /* Slot 3 - unused */
130 0, /* Slot 4 - unused */
131 0, /* Slot 5 - unused */
132 0, /* Slot 6 - unused */
133 0, /* Slot 7 - unused */
134 0, /* Slot 8 - unused */
135 0, /* Slot 9 - unused */
136 0, /* Slot 10 - unused */
137 0, /* Slot 11 - unused */
138 3, /* Slot 12 - SCSI */
139 0, /* Slot 13 - unused */
140 1, /* Slot 14 - Ethernet */
141 0, /* Slot 15 - unused */
147 static char Blackhawk_pci_IRQ_routes[] __prepdata =
149 0, /* Line 0 - Unused */
156 /* Motorola Mesquite */
157 static char Mesquite_pci_IRQ_map[23] __prepdata =
159 0, /* Slot 0 - unused */
160 0, /* Slot 1 - unused */
161 0, /* Slot 2 - unused */
162 0, /* Slot 3 - unused */
163 0, /* Slot 4 - unused */
164 0, /* Slot 5 - unused */
165 0, /* Slot 6 - unused */
166 0, /* Slot 7 - unused */
167 0, /* Slot 8 - unused */
168 0, /* Slot 9 - unused */
169 0, /* Slot 10 - unused */
170 0, /* Slot 11 - unused */
171 0, /* Slot 12 - unused */
172 0, /* Slot 13 - unused */
173 2, /* Slot 14 - Ethernet */
174 0, /* Slot 15 - unused */
175 3, /* Slot 16 - PMC */
176 0, /* Slot 17 - unused */
177 0, /* Slot 18 - unused */
178 0, /* Slot 19 - unused */
179 0, /* Slot 20 - unused */
180 0, /* Slot 21 - unused */
181 0, /* Slot 22 - unused */
185 static char Sitka_pci_IRQ_map[21] __prepdata =
187 0, /* Slot 0 - unused */
188 0, /* Slot 1 - unused */
189 0, /* Slot 2 - unused */
190 0, /* Slot 3 - unused */
191 0, /* Slot 4 - unused */
192 0, /* Slot 5 - unused */
193 0, /* Slot 6 - unused */
194 0, /* Slot 7 - unused */
195 0, /* Slot 8 - unused */
196 0, /* Slot 9 - unused */
197 0, /* Slot 10 - unused */
198 0, /* Slot 11 - unused */
199 0, /* Slot 12 - unused */
200 0, /* Slot 13 - unused */
201 2, /* Slot 14 - Ethernet */
202 0, /* Slot 15 - unused */
203 9, /* Slot 16 - PMC 1 */
204 12, /* Slot 17 - PMC 2 */
205 0, /* Slot 18 - unused */
206 0, /* Slot 19 - unused */
207 4, /* Slot 20 - NT P2P bridge */
211 static char MTX_pci_IRQ_map[23] __prepdata =
213 0, /* Slot 0 - unused */
214 0, /* Slot 1 - unused */
215 0, /* Slot 2 - unused */
216 0, /* Slot 3 - unused */
217 0, /* Slot 4 - unused */
218 0, /* Slot 5 - unused */
219 0, /* Slot 6 - unused */
220 0, /* Slot 7 - unused */
221 0, /* Slot 8 - unused */
222 0, /* Slot 9 - unused */
223 0, /* Slot 10 - unused */
224 0, /* Slot 11 - unused */
225 3, /* Slot 12 - SCSI */
226 0, /* Slot 13 - unused */
227 2, /* Slot 14 - Ethernet */
228 0, /* Slot 15 - unused */
229 9, /* Slot 16 - PCI/PMC slot 1 */
230 10, /* Slot 17 - PCI/PMC slot 2 */
231 11, /* Slot 18 - PCI slot 3 */
232 0, /* Slot 19 - unused */
233 0, /* Slot 20 - unused */
234 0, /* Slot 21 - unused */
235 0, /* Slot 22 - unused */
238 /* Motorola MTX Plus */
239 /* Secondary bus interrupt routing is not supported yet */
240 static char MTXplus_pci_IRQ_map[23] __prepdata =
242 0, /* Slot 0 - unused */
243 0, /* Slot 1 - unused */
244 0, /* Slot 2 - unused */
245 0, /* Slot 3 - unused */
246 0, /* Slot 4 - unused */
247 0, /* Slot 5 - unused */
248 0, /* Slot 6 - unused */
249 0, /* Slot 7 - unused */
250 0, /* Slot 8 - unused */
251 0, /* Slot 9 - unused */
252 0, /* Slot 10 - unused */
253 0, /* Slot 11 - unused */
254 3, /* Slot 12 - SCSI */
255 0, /* Slot 13 - unused */
256 2, /* Slot 14 - Ethernet 1 */
257 0, /* Slot 15 - unused */
258 9, /* Slot 16 - PCI slot 1P */
259 10, /* Slot 17 - PCI slot 2P */
260 11, /* Slot 18 - PCI slot 3P */
261 10, /* Slot 19 - Ethernet 2 */
262 0, /* Slot 20 - P2P Bridge */
263 0, /* Slot 21 - unused */
264 0, /* Slot 22 - unused */
267 static char Raven_pci_IRQ_routes[] __prepdata =
269 0, /* This is a dummy structure */
272 /* Motorola MVME16xx */
273 static char Genesis_pci_IRQ_map[16] __prepdata =
275 0, /* Slot 0 - unused */
276 0, /* Slot 1 - unused */
277 0, /* Slot 2 - unused */
278 0, /* Slot 3 - unused */
279 0, /* Slot 4 - unused */
280 0, /* Slot 5 - unused */
281 0, /* Slot 6 - unused */
282 0, /* Slot 7 - unused */
283 0, /* Slot 8 - unused */
284 0, /* Slot 9 - unused */
285 0, /* Slot 10 - unused */
286 0, /* Slot 11 - unused */
287 3, /* Slot 12 - SCSI */
288 0, /* Slot 13 - unused */
289 1, /* Slot 14 - Ethernet */
290 0, /* Slot 15 - unused */
293 static char Genesis_pci_IRQ_routes[] __prepdata =
295 0, /* Line 0 - Unused */
302 static char Genesis2_pci_IRQ_map[23] __prepdata =
304 0, /* Slot 0 - unused */
305 0, /* Slot 1 - unused */
306 0, /* Slot 2 - unused */
307 0, /* Slot 3 - unused */
308 0, /* Slot 4 - unused */
309 0, /* Slot 5 - unused */
310 0, /* Slot 6 - unused */
311 0, /* Slot 7 - unused */
312 0, /* Slot 8 - unused */
313 0, /* Slot 9 - unused */
314 0, /* Slot 10 - unused */
315 0, /* Slot 11 - IDE */
316 3, /* Slot 12 - SCSI */
317 5, /* Slot 13 - Universe PCI - VME Bridge */
318 2, /* Slot 14 - Ethernet */
319 0, /* Slot 15 - unused */
320 9, /* Slot 16 - PMC 1 */
321 12, /* Slot 17 - pci */
322 11, /* Slot 18 - pci */
323 10, /* Slot 19 - pci */
324 0, /* Slot 20 - pci */
325 0, /* Slot 21 - unused */
326 0, /* Slot 22 - unused */
329 /* Motorola Series-E */
330 static char Comet_pci_IRQ_map[23] __prepdata =
332 0, /* Slot 0 - unused */
333 0, /* Slot 1 - unused */
334 0, /* Slot 2 - unused */
335 0, /* Slot 3 - unused */
336 0, /* Slot 4 - unused */
337 0, /* Slot 5 - unused */
338 0, /* Slot 6 - unused */
339 0, /* Slot 7 - unused */
340 0, /* Slot 8 - unused */
341 0, /* Slot 9 - unused */
342 0, /* Slot 10 - unused */
343 0, /* Slot 11 - unused */
344 3, /* Slot 12 - SCSI */
345 0, /* Slot 13 - unused */
346 1, /* Slot 14 - Ethernet */
347 0, /* Slot 15 - unused */
348 1, /* Slot 16 - PCI slot 1 */
349 2, /* Slot 17 - PCI slot 2 */
350 3, /* Slot 18 - PCI slot 3 */
351 4, /* Slot 19 - PCI bridge */
357 static char Comet_pci_IRQ_routes[] __prepdata =
359 0, /* Line 0 - Unused */
366 /* Motorola Series-EX */
367 static char Comet2_pci_IRQ_map[23] __prepdata =
369 0, /* Slot 0 - unused */
370 0, /* Slot 1 - unused */
371 3, /* Slot 2 - SCSI - NCR825A */
372 0, /* Slot 3 - unused */
373 1, /* Slot 4 - Ethernet - DEC2104X */
374 0, /* Slot 5 - unused */
375 1, /* Slot 6 - PCI slot 1 */
376 2, /* Slot 7 - PCI slot 2 */
377 3, /* Slot 8 - PCI slot 3 */
378 4, /* Slot 9 - PCI bridge */
379 0, /* Slot 10 - unused */
380 0, /* Slot 11 - unused */
381 3, /* Slot 12 - SCSI - NCR825A */
382 0, /* Slot 13 - unused */
383 1, /* Slot 14 - Ethernet - DEC2104X */
384 0, /* Slot 15 - unused */
385 1, /* Slot 16 - PCI slot 1 */
386 2, /* Slot 17 - PCI slot 2 */
387 3, /* Slot 18 - PCI slot 3 */
388 4, /* Slot 19 - PCI bridge */
394 static char Comet2_pci_IRQ_routes[] __prepdata =
396 0, /* Line 0 - Unused */
404 * ibm 830 (and 850?).
405 * This is actually based on the Carolina motherboard
408 static char ibm8xx_pci_IRQ_map[23] __prepdata = {
409 0, /* Slot 0 - unused */
410 0, /* Slot 1 - unused */
411 0, /* Slot 2 - unused */
412 0, /* Slot 3 - unused */
413 0, /* Slot 4 - unused */
414 0, /* Slot 5 - unused */
415 0, /* Slot 6 - unused */
416 0, /* Slot 7 - unused */
417 0, /* Slot 8 - unused */
418 0, /* Slot 9 - unused */
419 0, /* Slot 10 - unused */
420 0, /* Slot 11 - FireCoral */
421 4, /* Slot 12 - Ethernet PCIINTD# */
422 2, /* Slot 13 - PCI Slot #2 */
423 2, /* Slot 14 - S3 Video PCIINTD# */
424 0, /* Slot 15 - onboard SCSI (INDI) [1] */
425 3, /* Slot 16 - NCR58C810 RS6000 Only PCIINTC# */
426 0, /* Slot 17 - unused */
427 2, /* Slot 18 - PCI Slot 2 PCIINTx# (See below) */
428 0, /* Slot 19 - unused */
429 0, /* Slot 20 - unused */
430 0, /* Slot 21 - unused */
431 2, /* Slot 22 - PCI slot 1 PCIINTx# (See below) */
434 static char ibm8xx_pci_IRQ_routes[] __prepdata = {
435 0, /* Line 0 - unused */
446 static char ibm6015_pci_IRQ_map[23] __prepdata = {
447 0, /* Slot 0 - unused */
448 0, /* Slot 1 - unused */
449 0, /* Slot 2 - unused */
450 0, /* Slot 3 - unused */
451 0, /* Slot 4 - unused */
452 0, /* Slot 5 - unused */
453 0, /* Slot 6 - unused */
454 0, /* Slot 7 - unused */
455 0, /* Slot 8 - unused */
456 0, /* Slot 9 - unused */
457 0, /* Slot 10 - unused */
459 1, /* Slot 12 - SCSI */
472 static char ibm6015_pci_IRQ_routes[] __prepdata = {
473 0, /* Line 0 - unused */
481 /* IBM Nobis and Thinkpad 850 */
482 static char Nobis_pci_IRQ_map[23] __prepdata ={
483 0, /* Slot 0 - unused */
484 0, /* Slot 1 - unused */
485 0, /* Slot 2 - unused */
486 0, /* Slot 3 - unused */
487 0, /* Slot 4 - unused */
488 0, /* Slot 5 - unused */
489 0, /* Slot 6 - unused */
490 0, /* Slot 7 - unused */
491 0, /* Slot 8 - unused */
492 0, /* Slot 9 - unused */
493 0, /* Slot 10 - unused */
494 0, /* Slot 11 - unused */
495 3, /* Slot 12 - SCSI */
496 0, /* Slot 13 - unused */
497 0, /* Slot 14 - unused */
498 0, /* Slot 15 - unused */
501 static char Nobis_pci_IRQ_routes[] __prepdata = {
502 0, /* Line 0 - Unused */
510 * IBM RS/6000 43p/140 -- paulus
511 * XXX we should get all this from the residual data
513 static char ibm43p_pci_IRQ_map[23] __prepdata = {
514 0, /* Slot 0 - unused */
515 0, /* Slot 1 - unused */
516 0, /* Slot 2 - unused */
517 0, /* Slot 3 - unused */
518 0, /* Slot 4 - unused */
519 0, /* Slot 5 - unused */
520 0, /* Slot 6 - unused */
521 0, /* Slot 7 - unused */
522 0, /* Slot 8 - unused */
523 0, /* Slot 9 - unused */
524 0, /* Slot 10 - unused */
525 0, /* Slot 11 - FireCoral ISA bridge */
526 6, /* Slot 12 - Ethernet */
527 0, /* Slot 13 - openpic */
528 0, /* Slot 14 - unused */
529 0, /* Slot 15 - unused */
530 7, /* Slot 16 - NCR58C825a onboard scsi */
531 0, /* Slot 17 - unused */
532 2, /* Slot 18 - PCI Slot 2 PCIINTx# (See below) */
533 0, /* Slot 19 - unused */
534 0, /* Slot 20 - unused */
535 0, /* Slot 21 - unused */
536 1, /* Slot 22 - PCI slot 1 PCIINTx# (See below) */
539 static char ibm43p_pci_IRQ_routes[] __prepdata = {
540 0, /* Line 0 - unused */
547 /* Motorola PowerPlus architecture PCI IRQ tables */
548 /* Interrupt line values for INTA-D on primary/secondary MPIC inputs */
550 struct powerplus_irq_list
552 unsigned char primary[4]; /* INT A-D */
553 unsigned char secondary[4]; /* INT A-D */
557 * For standard PowerPlus boards, bus 0 PCI INTs A-D are routed to
558 * OpenPIC inputs 9-12. PCI INTs A-D from the on board P2P bridge
559 * are routed to OpenPIC inputs 5-8. These values are offset by
560 * 16 in the table to reflect the Linux kernel interrupt value.
562 struct powerplus_irq_list Powerplus_pci_IRQ_list __prepdata =
569 * For the MCP750 (system slot board), cPCI INTs A-D are routed to
570 * OpenPIC inputs 8-11 and the PMC INTs A-D are routed to OpenPIC
571 * input 3. On a hot swap MCP750, the companion card PCI INTs A-D
572 * are routed to OpenPIC inputs 12-15. These values are offset by
573 * 16 in the table to reflect the Linux kernel interrupt value.
575 struct powerplus_irq_list Mesquite_pci_IRQ_list __prepdata =
582 * This table represents the standard PCI swizzle defined in the
583 * PCI bus specification.
585 static unsigned char prep_pci_intpins[4][4] __prepdata =
587 { 1, 2, 3, 4}, /* Buses 0, 4, 8, ... */
588 { 2, 3, 4, 1}, /* Buses 1, 5, 9, ... */
589 { 3, 4, 1, 2}, /* Buses 2, 6, 10 ... */
590 { 4, 1, 2, 3}, /* Buses 3, 7, 11 ... */
593 /* We have to turn on LEVEL mode for changed IRQ's */
594 /* All PCI IRQ's need to be level mode, so this should be something
595 * other than hard-coded as well... IRQ's are individually mappable
596 * to either edge or level.
600 * 8259 edge/level control definitions
602 #define ISA8259_M_ELCR 0x4d0
603 #define ISA8259_S_ELCR 0x4d1
605 #define ELCRS_INT15_LVL 0x80
606 #define ELCRS_INT14_LVL 0x40
607 #define ELCRS_INT12_LVL 0x10
608 #define ELCRS_INT11_LVL 0x08
609 #define ELCRS_INT10_LVL 0x04
610 #define ELCRS_INT9_LVL 0x02
611 #define ELCRS_INT8_LVL 0x01
612 #define ELCRM_INT7_LVL 0x80
613 #define ELCRM_INT5_LVL 0x20
617 * PCI config space access.
619 #define CFGADDR(dev) ((1<<(dev>>3)) | ((dev&7)<<8))
620 #define DEVNO(dev) (dev>>3)
626 prep_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
629 struct pci_controller *hose = bus->sysdata;
630 volatile unsigned char *cfg_data;
632 if (bus->number != 0 || DEVNO(devfn) < MIN_DEVNR
633 || DEVNO(devfn) > MAX_DEVNR)
634 return PCIBIOS_DEVICE_NOT_FOUND;
637 * Note: the caller has already checked that offset is
638 * suitably aligned and that len is 1, 2 or 4.
640 cfg_data = hose->cfg_data + CFGADDR(devfn) + offset;
643 *val = in_8((u8 *)cfg_data);
646 *val = in_le16((u16 *)cfg_data);
649 *val = in_le32((u32 *)cfg_data);
652 return PCIBIOS_SUCCESSFUL;
656 prep_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
659 struct pci_controller *hose = bus->sysdata;
660 volatile unsigned char *cfg_data;
662 if (bus->number != 0 || DEVNO(devfn) < MIN_DEVNR
663 || DEVNO(devfn) > MAX_DEVNR)
664 return PCIBIOS_DEVICE_NOT_FOUND;
667 * Note: the caller has already checked that offset is
668 * suitably aligned and that len is 1, 2 or 4.
670 cfg_data = hose->cfg_data + CFGADDR(devfn) + offset;
673 out_8((u8 *)cfg_data, val);
676 out_le16((u16 *)cfg_data, val);
679 out_le32((u32 *)cfg_data, val);
682 return PCIBIOS_SUCCESSFUL;
685 static struct pci_ops prep_pci_ops =
692 #define MOTOROLA_CPUTYPE_REG 0x800
693 #define MOTOROLA_BASETYPE_REG 0x803
694 #define MPIC_RAVEN_ID 0x48010000
695 #define MPIC_HAWK_ID 0x48030000
696 #define MOT_PROC2_BIT 0x800
698 static u_char prep_openpic_initsenses[] __initdata = {
699 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* MVME2600_INT_SIO */
700 (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_FALCN_ECC_ERR */
701 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_ETHERNET */
702 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_SCSI */
703 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_GRAPHICS */
704 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME0 */
705 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME1 */
706 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME2 */
707 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME3 */
708 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTA */
709 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTB */
710 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTC */
711 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTD */
712 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG0 */
713 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG1 */
716 #define MOT_RAVEN_PRESENT 0x1
717 #define MOT_HAWK_PRESENT 0x2
720 int prep_keybd_present = 1;
728 unsigned int pci_membase;
729 unsigned char base_mod;
731 /* Check to see if the Raven chip exists. */
732 if ( _prep_type != _PREP_Motorola) {
737 /* Check to see if this board is a type that might have a Raven. */
738 if ((inb(MOTOROLA_CPUTYPE_REG) & 0xF0) != 0xE0) {
743 /* Check the first PCI device to see if it is a Raven. */
744 early_read_config_dword(NULL, 0, 0, PCI_VENDOR_ID, &devid);
746 switch (devid & 0xffff0000) {
748 MotMPIC = MOT_RAVEN_PRESENT;
751 MotMPIC = MOT_HAWK_PRESENT;
759 /* Read the memory base register. */
760 early_read_config_dword(NULL, 0, 0, PCI_BASE_ADDRESS_1, &pci_membase);
762 if (pci_membase == 0) {
767 /* Map the Raven MPIC registers to virtual memory. */
768 OpenPIC_Addr = ioremap(pci_membase+0xC0000000, 0x22000);
770 OpenPIC_InitSenses = prep_openpic_initsenses;
771 OpenPIC_NumInitSenses = sizeof(prep_openpic_initsenses);
773 ppc_md.get_irq = openpic_get_irq;
775 /* If raven is present on Motorola store the system config register
778 ProcInfo = (unsigned long *)ioremap(0xfef80400, 4);
780 /* Indicate to system if this is a multiprocessor board */
781 if (!(*ProcInfo & MOT_PROC2_BIT)) {
785 /* This is a hack. If this is a 2300 or 2400 mot board then there is
786 * no keyboard controller and we have to indicate that.
788 base_mod = inb(MOTOROLA_BASETYPE_REG);
789 if ((MotMPIC == MOT_HAWK_PRESENT) || (base_mod == 0xF9) ||
790 (base_mod == 0xFA) || (base_mod == 0xE1))
791 prep_keybd_present = 0;
797 int cpu_type; /* 0x100 mask assumes for Raven and Hawk boards that the level/edge are set */
798 /* 0x200 if this board has a Hawk chip. */
800 int max_cpu; /* ored with 0x80 if this board should be checked for multi CPU */
803 unsigned char *routes;
804 void (*map_non0_bus)(struct pci_dev *); /* For boards with more than bus 0 devices. */
805 struct powerplus_irq_list *pci_irq_list; /* List of PCI MPIC inputs */
806 unsigned char secondary_bridge_devfn; /* devfn of secondary bus transparent bridge */
807 } mot_info[] __prepdata = {
808 {0x300, 0x00, 0x00, "MVME 2400", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
809 {0x010, 0x00, 0x00, "Genesis", Genesis_pci_IRQ_map, Genesis_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
810 {0x020, 0x00, 0x00, "Powerstack (Series E)", Comet_pci_IRQ_map, Comet_pci_IRQ_routes, NULL, NULL, 0x00},
811 {0x040, 0x00, 0x00, "Blackhawk (Powerstack)", Blackhawk_pci_IRQ_map, Blackhawk_pci_IRQ_routes, NULL, NULL, 0x00},
812 {0x050, 0x00, 0x00, "Omaha (PowerStack II Pro3000)", Omaha_pci_IRQ_map, Omaha_pci_IRQ_routes, NULL, NULL, 0x00},
813 {0x060, 0x00, 0x00, "Utah (Powerstack II Pro4000)", Utah_pci_IRQ_map, Utah_pci_IRQ_routes, NULL, NULL, 0x00},
814 {0x0A0, 0x00, 0x00, "Powerstack (Series EX)", Comet2_pci_IRQ_map, Comet2_pci_IRQ_routes, NULL, NULL, 0x00},
815 {0x1E0, 0xE0, 0x00, "Mesquite cPCI (MCP750)", Mesquite_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Mesquite_pci_IRQ_list, 0xFF},
816 {0x1E0, 0xE1, 0x00, "Sitka cPCI (MCPN750)", Sitka_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
817 {0x1E0, 0xE2, 0x00, "Mesquite cPCI (MCP750) w/ HAC", Mesquite_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Mesquite_pci_IRQ_list, 0xC0},
818 {0x1E0, 0xF6, 0x80, "MTX Plus", MTXplus_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xA0},
819 {0x1E0, 0xF6, 0x81, "Dual MTX Plus", MTXplus_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xA0},
820 {0x1E0, 0xF7, 0x80, "MTX wo/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
821 {0x1E0, 0xF7, 0x81, "Dual MTX wo/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
822 {0x1E0, 0xF8, 0x80, "MTX w/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
823 {0x1E0, 0xF8, 0x81, "Dual MTX w/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
824 {0x1E0, 0xF9, 0x00, "MVME 2300", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
825 {0x1E0, 0xFA, 0x00, "MVME 2300SC/2600", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
826 {0x1E0, 0xFB, 0x00, "MVME 2600 with MVME712M", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
827 {0x1E0, 0xFC, 0x00, "MVME 2600/2700 with MVME761", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
828 {0x1E0, 0xFD, 0x80, "MVME 3600 with MVME712M", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
829 {0x1E0, 0xFD, 0x81, "MVME 4600 with MVME712M", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
830 {0x1E0, 0xFE, 0x80, "MVME 3600 with MVME761", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
831 {0x1E0, 0xFE, 0x81, "MVME 4600 with MVME761", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
832 {0x1E0, 0xFF, 0x00, "MVME 1600-001 or 1600-011", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
833 {0x000, 0x00, 0x00, "", NULL, NULL, NULL, NULL, 0x00}
839 #ifdef CONFIG_PREP_RESIDUAL
840 u32 addr, real_addr, len;
844 /* Use the PReP residual data to determine if an OpenPIC is
845 * present. If so, get the large vendor packet which will
846 * tell us the base address and length in memory.
847 * If we are successful, ioremap the memory area and set
848 * OpenPIC_Addr (this indicates that the OpenPIC was found).
850 mpic = residual_find_device(-1, NULL, SystemPeripheral,
851 ProgrammableInterruptController, MPIC, 0);
855 pkt = PnP_find_large_vendor_packet(res->DevicePnPHeap +
856 mpic->AllocatedOffset, 9, 0);
861 #define p pkt->L4_Pack.L4_Data.L4_PPCPack
862 if (!((p.PPCData[0] == 2) && (p.PPCData[1] == 32)))
863 return; /* not a 32-bit memory address */
865 real_addr = ld_le32((unsigned int *) (p.PPCData + 4));
866 if (real_addr == 0xffffffff)
869 /* Adjust address to be as seen by CPU */
870 addr = real_addr + PREP_ISA_MEM_BASE;
872 len = ld_le32((unsigned int *) (p.PPCData + 12));
876 OpenPIC_Addr = ioremap(addr, len);
877 ppc_md.get_irq = openpic_get_irq;
879 OpenPIC_InitSenses = prep_openpic_initsenses;
880 OpenPIC_NumInitSenses = sizeof(prep_openpic_initsenses);
882 printk(KERN_INFO "MPIC at 0x%08x (0x%08x), length 0x%08x "
883 "mapped to 0x%p\n", addr, real_addr, len, OpenPIC_Addr);
888 ibm43p_pci_map_non0(struct pci_dev *dev)
890 unsigned char intpin;
891 static unsigned char bridge_intrs[4] = { 3, 4, 5, 8 };
895 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &intpin);
896 if (intpin < 1 || intpin > 4)
898 intpin = (PCI_SLOT(dev->devfn) + intpin - 1) & 3;
899 dev->irq = openpic_to_irq(bridge_intrs[intpin]);
900 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
904 prep_sandalfoot_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi)
906 Motherboard_map_name = "IBM 6015/7020 (Sandalfoot/Sandalbow)";
907 Motherboard_map = ibm6015_pci_IRQ_map;
908 Motherboard_routes = ibm6015_pci_IRQ_routes;
909 *irq_edge_mask_lo = 0x00; /* irq's 0-7 all edge-triggered */
910 *irq_edge_mask_hi = 0xA0; /* irq's 13, 15 level-triggered */
914 prep_thinkpad_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi)
916 Motherboard_map_name = "IBM Thinkpad 850/860";
917 Motherboard_map = Nobis_pci_IRQ_map;
918 Motherboard_routes = Nobis_pci_IRQ_routes;
919 *irq_edge_mask_lo = 0x00; /* irq's 0-7 all edge-triggered */
920 *irq_edge_mask_hi = 0xA0; /* irq's 13, 15 level-triggered */
924 prep_carolina_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi)
926 Motherboard_map_name = "IBM 7248, PowerSeries 830/850 (Carolina)";
927 Motherboard_map = ibm8xx_pci_IRQ_map;
928 Motherboard_routes = ibm8xx_pci_IRQ_routes;
929 *irq_edge_mask_lo = 0x00; /* irq's 0-7 all edge-triggered */
930 *irq_edge_mask_hi = 0xA4; /* irq's 10, 13, 15 level-triggered */
934 prep_tiger1_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi)
936 Motherboard_map_name = "IBM 43P-140 (Tiger1)";
937 Motherboard_map = ibm43p_pci_IRQ_map;
938 Motherboard_routes = ibm43p_pci_IRQ_routes;
939 Motherboard_non0 = ibm43p_pci_map_non0;
940 *irq_edge_mask_lo = 0x00; /* irq's 0-7 all edge-triggered */
941 *irq_edge_mask_hi = 0xA0; /* irq's 13, 15 level-triggered */
945 prep_route_pci_interrupts(void)
947 unsigned char *ibc_pirq = (unsigned char *)0x80800860;
948 unsigned char *ibc_pcicon = (unsigned char *)0x80800840;
951 if ( _prep_type == _PREP_Motorola)
953 unsigned short irq_mode;
954 unsigned char cpu_type;
955 unsigned char base_mod;
958 cpu_type = inb(MOTOROLA_CPUTYPE_REG) & 0xF0;
959 base_mod = inb(MOTOROLA_BASETYPE_REG);
961 for (entry = 0; mot_info[entry].cpu_type != 0; entry++) {
962 if (mot_info[entry].cpu_type & 0x200) { /* Check for Hawk chip */
963 if (!(MotMPIC & MOT_HAWK_PRESENT))
965 } else { /* Check non hawk boards */
966 if ((mot_info[entry].cpu_type & 0xff) != cpu_type)
969 if (mot_info[entry].base_type == 0) {
974 if (mot_info[entry].base_type != base_mod)
978 if (!(mot_info[entry].max_cpu & 0x80)) {
983 /* processor 1 not present and max processor zero indicated */
984 if ((*ProcInfo & MOT_PROC2_BIT) && !(mot_info[entry].max_cpu & 0x7f)) {
989 /* processor 1 present and max processor zero indicated */
990 if (!(*ProcInfo & MOT_PROC2_BIT) && (mot_info[entry].max_cpu & 0x7f)) {
996 if (mot_entry == -1) /* No particular cpu type found - assume Blackhawk */
999 Motherboard_map_name = (unsigned char *)mot_info[mot_entry].name;
1000 Motherboard_map = mot_info[mot_entry].map;
1001 Motherboard_routes = mot_info[mot_entry].routes;
1002 Motherboard_non0 = mot_info[mot_entry].map_non0_bus;
1004 if (!(mot_info[entry].cpu_type & 0x100)) {
1005 /* AJF adjust level/edge control according to routes */
1007 for (i = 1; i <= 4; i++)
1008 irq_mode |= ( 1 << Motherboard_routes[i] );
1009 outb( irq_mode & 0xff, 0x4d0 );
1010 outb( (irq_mode >> 8) & 0xff, 0x4d1 );
1012 } else if ( _prep_type == _PREP_IBM ) {
1013 unsigned char irq_edge_mask_lo, irq_edge_mask_hi;
1015 setup_ibm_pci(&irq_edge_mask_lo, &irq_edge_mask_hi);
1017 outb(inb(0x04d0)|irq_edge_mask_lo, 0x4d0); /* primary 8259 */
1018 outb(inb(0x04d1)|irq_edge_mask_hi, 0x4d1); /* cascaded 8259 */
1020 printk("No known machine pci routing!\n");
1024 /* Set up mapping from slots */
1025 for (i = 1; i <= 4; i++)
1026 ibc_pirq[i-1] = Motherboard_routes[i];
1027 /* Enable PCI interrupts */
1028 *ibc_pcicon |= 0x20;
1035 unsigned short short_reg;
1037 struct pci_dev *dev = NULL;
1039 if (( _prep_type == _PREP_Motorola) && (OpenPIC_Addr)) {
1041 * Perform specific configuration for the Via Tech or
1042 * or Winbond PCI-ISA-Bridge part.
1044 if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
1045 PCI_DEVICE_ID_VIA_82C586_1, dev))) {
1047 * PPCBUG does not set the enable bits
1048 * for the IDE device. Force them on here.
1050 pci_read_config_byte(dev, 0x40, ®);
1052 reg |= 0x03; /* IDE: Chip Enable Bits */
1053 pci_write_config_byte(dev, 0x40, reg);
1055 if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
1056 PCI_DEVICE_ID_VIA_82C586_2,
1057 dev)) && (dev->devfn = 0x5a)) {
1058 /* Force correct USB interrupt */
1060 pci_write_config_byte(dev,
1064 if ((dev = pci_find_device(PCI_VENDOR_ID_WINBOND,
1065 PCI_DEVICE_ID_WINBOND_83C553, dev))) {
1066 /* Clear PCI Interrupt Routing Control Register. */
1068 pci_write_config_word(dev, 0x44, short_reg);
1070 /* Route IDE interrupts to IRQ 14 */
1072 pci_write_config_byte(dev, 0x43, reg);
1077 if ((dev = pci_find_device(PCI_VENDOR_ID_WINBOND,
1078 PCI_DEVICE_ID_WINBOND_82C105, dev))){
1081 * Disable LEGIRQ mode so PCI INTS are routed
1082 * directly to the 8259 and enable both channels
1084 pci_write_config_dword(dev, 0x40, 0x10ff0033);
1086 /* Force correct IDE interrupt */
1088 pci_write_config_byte(dev,
1092 /* Enable LEGIRQ for PCI INT -> 8259 IRQ routing */
1093 pci_write_config_dword(dev, 0x40, 0x10ff08a1);
1099 Powerplus_Map_Non0(struct pci_dev *dev)
1101 struct pci_bus *pbus; /* Parent bus structure pointer */
1102 struct pci_dev *tdev = dev; /* Temporary device structure */
1103 unsigned int devnum; /* Accumulated device number */
1104 unsigned char intline; /* Linux interrupt value */
1105 unsigned char intpin; /* PCI interrupt pin */
1107 /* Check for valid PCI dev pointer */
1108 if (dev == NULL) return;
1110 /* Initialize bridge IDSEL variable */
1111 devnum = PCI_SLOT(tdev->devfn);
1113 /* Read the interrupt pin of the device and adjust for indexing */
1114 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &intpin);
1116 /* If device doesn't request an interrupt, return */
1117 if ( (intpin < 1) || (intpin > 4) )
1123 * Walk up to bus 0, adjusting the interrupt pin for the standard
1127 intpin = (prep_pci_intpins[devnum % 4][intpin]) - 1;
1128 pbus = tdev->bus; /* up one level */
1130 devnum = PCI_SLOT(tdev->devfn);
1131 } while(tdev->bus->number);
1133 /* Use the primary interrupt inputs by default */
1134 intline = mot_info[mot_entry].pci_irq_list->primary[intpin];
1137 * If the board has secondary interrupt inputs, walk the bus and
1138 * note the devfn of the bridge from bus 0. If it is the same as
1139 * the devfn of the bus bridge with secondary inputs, use those.
1140 * Otherwise, assume it's a PMC site and get the interrupt line
1141 * value from the interrupt routing table.
1143 if (mot_info[mot_entry].secondary_bridge_devfn) {
1146 while (pbus->primary != 0)
1147 pbus = pbus->parent;
1149 if ((pbus->self)->devfn != 0xA0) {
1150 if ((pbus->self)->devfn == mot_info[mot_entry].secondary_bridge_devfn)
1151 intline = mot_info[mot_entry].pci_irq_list->secondary[intpin];
1153 if ((char *)(mot_info[mot_entry].map) == (char *)Mesquite_pci_IRQ_map)
1154 intline = mot_info[mot_entry].map[((pbus->self)->devfn)/8] + 16;
1158 intpin = (prep_pci_intpins[devnum % 4][intpin]) - 1;
1159 intline = mot_info[mot_entry].pci_irq_list->primary[intpin];
1165 /* Write calculated interrupt value to header and device list */
1167 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, (u8)dev->irq);
1171 prep_pcibios_fixup(void)
1173 struct pci_dev *dev = NULL;
1175 prep_route_pci_interrupts();
1177 printk("Setting PCI interrupts for a \"%s\"\n", Motherboard_map_name);
1179 /* PCI interrupts are controlled by the OpenPIC */
1180 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1181 if (dev->bus->number == 0) {
1182 dev->irq = openpic_to_irq(Motherboard_map[PCI_SLOT(dev->devfn)]);
1183 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
1185 if (Motherboard_non0 != NULL)
1186 Motherboard_non0(dev);
1190 /* Setup the Winbond or Via PIB */
1197 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1199 * Use our old hard-coded kludge to figure out what
1200 * irq this device uses. This is necessary on things
1201 * without residual data. -- Cort
1203 unsigned char d = PCI_SLOT(dev->devfn);
1204 dev->irq = Motherboard_routes[Motherboard_map[d]];
1209 prep_pcibios_after_init(void)
1212 struct pci_dev *dev;
1214 /* If there is a WD 90C, reset the IO BAR to 0x0 (it started that
1215 * way, but the PCI layer relocated it because it thought 0x0 was
1216 * invalid for a BAR).
1217 * If you don't do this, the card's VGA base will be <IO BAR>+0xc0000
1218 * instead of 0xc0000. vgacon.c (for example) is completely unaware of
1219 * this little quirk.
1221 dev = pci_find_device(PCI_VENDOR_ID_WD, PCI_DEVICE_ID_WD_90C, NULL);
1223 dev->resource[1].end -= dev->resource[1].start;
1224 dev->resource[1].start = 0;
1225 /* tell the hardware */
1226 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0x0);
1232 prep_init_resource(struct resource *res, unsigned long start,
1233 unsigned long end, int flags)
1238 res->name = "PCI host bridge";
1240 res->sibling = NULL;
1245 prep_find_bridges(void)
1247 struct pci_controller* hose;
1249 hose = pcibios_alloc_controller();
1253 hose->first_busno = 0;
1254 hose->last_busno = 0xff;
1255 hose->pci_mem_offset = PREP_ISA_MEM_BASE;
1256 hose->io_base_phys = PREP_ISA_IO_BASE;
1257 hose->io_base_virt = ioremap(PREP_ISA_IO_BASE, 0x800000);
1258 prep_init_resource(&hose->io_resource, 0, 0x007fffff, IORESOURCE_IO);
1259 prep_init_resource(&hose->mem_resources[0], 0xc0000000, 0xfeffffff,
1261 setup_indirect_pci(hose, PREP_ISA_IO_BASE + 0xcf8,
1262 PREP_ISA_IO_BASE + 0xcfc);
1264 printk("PReP architecture\n");
1265 #ifdef CONFIG_PREP_RESIDUAL
1267 PPC_DEVICE *hostbridge;
1269 hostbridge = residual_find_device(PROCESSORDEVICE, NULL,
1270 BridgeController, PCIBridge, -1, 0);
1272 hostbridge->DeviceId.Interface == PCIBridgeIndirect) {
1273 PnP_TAG_PACKET * pkt;
1274 pkt = PnP_find_large_vendor_packet(
1275 res->DevicePnPHeap+hostbridge->AllocatedOffset,
1278 #define p pkt->L4_Pack.L4_Data.L4_PPCPack
1279 setup_indirect_pci(hose,
1280 ld_le32((unsigned *) (p.PPCData)),
1281 ld_le32((unsigned *) (p.PPCData+8)));
1284 setup_indirect_pci(hose, 0x80000cf8, 0x80000cfc);
1287 #endif /* CONFIG_PREP_RESIDUAL */
1289 ppc_md.pcibios_fixup = prep_pcibios_fixup;
1290 ppc_md.pcibios_after_init = prep_pcibios_after_init;