2 * arch/ppc/platforms/sandpoint_setup.c
4 * Board setup routines for the Motorola SPS Sandpoint Test Platform.
6 * Author: Mark A. Greer
9 * 2000-2003 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
16 * This file adds support for the Motorola SPS Sandpoint Test Platform.
17 * These boards have a PPMC slot for the processor so any combination
18 * of cpu and host bridge can be attached. This port is for an 8240 PPMC
19 * module from Motorola SPS and other closely related cpu/host bridge
20 * combinations (e.g., 750/755/7400 with MPC107 host bridge).
21 * The sandpoint itself has a Windbond 83c553 (PCI-ISA bridge, 2 DMA ctlrs, 2
22 * cascaded 8259 interrupt ctlrs, 8254 Timer/Counter, and an IDE ctlr), a
23 * National 87308 (RTC, 2 UARTs, Keyboard & mouse ctlrs, and a floppy ctlr),
24 * and 4 PCI slots (only 2 of which are usable; the other 2 are keyed for 3.3V
27 * The firmware on the sandpoint is called DINK (not my acronym :). This port
28 * depends on DINK to do some basic initialization (e.g., initialize the memory
29 * ctlr) and to ensure that the processor is using MAP B (CHRP map).
31 * The switch settings for the Sandpoint board MUST be as follows:
37 * 'down' is in the direction from the PCI slots towards the PPMC slot;
38 * 'up' is in the direction from the PPMC slot towards the PCI slots.
39 * Be careful, the way the sandpoint board is installed in XT chasses will
40 * make the directions reversed.
42 * Since Motorola listened to our suggestions for improvement, we now have
43 * the Sandpoint X3 board. All of the PCI slots are available, it uses
44 * the serial interrupt interface (just a hardware thing we need to
45 * configure properly).
47 * Use the default X3 switch settings. The interrupts are then:
49 * 0 SIOINT (8259, active low)
54 * 7 Winbond INTC (IDE interrupt)
55 * 8 Winbond INTD (IDE interrupt)
58 * Motorola has finally released a version of DINK32 that correctly
59 * (seemingly) initalizes the memory controller correctly, regardless
60 * of the amount of memory in the system. Once a method of determining
61 * what version of DINK initializes the system for us, if applicable, is
62 * found, we can hopefully stop hardcoding 32MB of RAM.
65 #include <linux/config.h>
66 #include <linux/stddef.h>
67 #include <linux/kernel.h>
68 #include <linux/init.h>
69 #include <linux/errno.h>
70 #include <linux/reboot.h>
71 #include <linux/pci.h>
72 #include <linux/kdev_t.h>
73 #include <linux/major.h>
74 #include <linux/initrd.h>
75 #include <linux/console.h>
76 #include <linux/delay.h>
77 #include <linux/irq.h>
78 #include <linux/ide.h>
79 #include <linux/seq_file.h>
80 #include <linux/root_dev.h>
81 #include <linux/serial.h>
82 #include <linux/tty.h> /* for linux/serial_core.h */
83 #include <linux/serial_core.h>
85 #include <asm/system.h>
86 #include <asm/pgtable.h>
91 #include <asm/machdep.h>
95 #include <asm/open_pic.h>
96 #include <asm/i8259.h>
98 #include <asm/bootinfo.h>
99 #include <asm/mpc10x.h>
100 #include <asm/pci-bridge.h>
101 #include <asm/kgdb.h>
103 #include "sandpoint.h"
105 /* Set non-zero if an X2 Sandpoint detected. */
106 static int sandpoint_is_x2;
108 unsigned char __res[sizeof(bd_t)];
110 static void sandpoint_halt(void);
111 static void sandpoint_probe_type(void);
114 * Define all of the IRQ senses and polarities. Taken from the
115 * Sandpoint X3 User's manual.
117 static u_char sandpoint_openpic_initsenses[] __initdata = {
118 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 0: SIOINT */
119 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 2: PCI Slot 1 */
120 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 3: PCI Slot 2 */
121 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 4: PCI Slot 3 */
122 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 5: PCI Slot 4 */
123 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 8: IDE (INT C) */
124 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE) /* 9: IDE (INT D) */
128 * Motorola SPS Sandpoint interrupt routing.
131 x3_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
133 static char pci_irq_table[][4] =
135 * PCI IDSEL/INTPIN->INTLINE
139 { 16, 0, 0, 0 }, /* IDSEL 11 - i8259 on Winbond */
140 { 0, 0, 0, 0 }, /* IDSEL 12 - unused */
141 { 18, 21, 20, 19 }, /* IDSEL 13 - PCI slot 1 */
142 { 19, 18, 21, 20 }, /* IDSEL 14 - PCI slot 2 */
143 { 20, 19, 18, 21 }, /* IDSEL 15 - PCI slot 3 */
144 { 21, 20, 19, 18 }, /* IDSEL 16 - PCI slot 4 */
147 const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
148 return PCI_IRQ_TABLE_LOOKUP;
152 x2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
154 static char pci_irq_table[][4] =
156 * PCI IDSEL/INTPIN->INTLINE
160 { 18, 0, 0, 0 }, /* IDSEL 11 - i8259 on Windbond */
161 { 0, 0, 0, 0 }, /* IDSEL 12 - unused */
162 { 16, 17, 18, 19 }, /* IDSEL 13 - PCI slot 1 */
163 { 17, 18, 19, 16 }, /* IDSEL 14 - PCI slot 2 */
164 { 18, 19, 16, 17 }, /* IDSEL 15 - PCI slot 3 */
165 { 19, 16, 17, 18 }, /* IDSEL 16 - PCI slot 4 */
168 const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
169 return PCI_IRQ_TABLE_LOOKUP;
173 sandpoint_setup_winbond_83553(struct pci_controller *hose)
178 * Route IDE interrupts directly to the 8259's IRQ 14 & 15.
179 * We can't route the IDE interrupt to PCI INTC# or INTD# because those
180 * woule interfere with the PMC's INTC# and INTD# lines.
185 devfn = PCI_DEVFN(11,0);
187 early_write_config_byte(hose,
190 0x43, /* IDE Interrupt Routing Control */
192 early_write_config_word(hose,
195 0x44, /* PCI Interrupt Routing Control */
198 /* Want ISA memory cycles to be forwarded to PCI bus */
199 early_write_config_byte(hose,
202 0x48, /* ISA-to-PCI Addr Decoder Control */
205 /* Enable RTC and Keyboard address locations. */
206 early_write_config_byte(hose,
209 0x4d, /* Chip Select Control Register */
212 /* Enable Port 92. */
213 early_write_config_byte(hose,
216 0x4e, /* AT System Control Register */
221 devfn = PCI_DEVFN(11,1);
223 /* Put IDE controller into native mode. */
224 early_write_config_byte(hose,
227 0x09, /* Programming interface Register */
230 /* Init IRQ routing, enable both ports, disable fast 16 */
231 early_write_config_dword(hose,
234 0x40, /* IDE Control/Status Register */
239 /* On the sandpoint X2, we must avoid sending configuration cycles to
240 * device #12 (IDSEL addr = AD12).
243 x2_exclude_device(u_char bus, u_char devfn)
245 if ((bus == 0) && (PCI_SLOT(devfn) == SANDPOINT_HOST_BRIDGE_IDSEL))
246 return PCIBIOS_DEVICE_NOT_FOUND;
248 return PCIBIOS_SUCCESSFUL;
252 sandpoint_find_bridges(void)
254 struct pci_controller *hose;
256 hose = pcibios_alloc_controller();
261 hose->first_busno = 0;
262 hose->last_busno = 0xff;
264 if (mpc10x_bridge_init(hose,
267 MPC10X_MAPB_EUMB_BASE) == 0) {
269 /* Do early winbond init, then scan PCI bus */
270 sandpoint_setup_winbond_83553(hose);
271 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
273 ppc_md.pcibios_fixup = NULL;
274 ppc_md.pcibios_fixup_bus = NULL;
275 ppc_md.pci_swizzle = common_swizzle;
276 if (sandpoint_is_x2) {
277 ppc_md.pci_map_irq = x2_map_irq;
278 ppc_md.pci_exclude_device = x2_exclude_device;
280 ppc_md.pci_map_irq = x3_map_irq;
284 ppc_md.progress("Bridge init failed", 0x100);
285 printk("Host bridge init failed\n");
292 sandpoint_setup_arch(void)
294 /* Probe for Sandpoint model */
295 sandpoint_probe_type();
297 epic_serial_mode = 0;
299 loops_per_jiffy = 100000000 / HZ;
301 #ifdef CONFIG_BLK_DEV_INITRD
303 ROOT_DEV = Root_RAM0;
306 #ifdef CONFIG_ROOT_NFS
309 ROOT_DEV = Root_HDA1;
312 /* Lookup PCI host bridges */
313 sandpoint_find_bridges();
315 printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n");
316 printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
318 /* DINK32 12.3 and below do not correctly enable any caches.
319 * We will do this now with good known values. Future versions
320 * of DINK32 are supposed to get this correct.
322 if (cur_cpu_spec[0]->cpu_features & CPU_FTR_SPEC7450)
323 /* 745x is different. We only want to pass along enable. */
325 else if (cur_cpu_spec[0]->cpu_features & CPU_FTR_L2CR)
326 /* All modules have 1MB of L2. We also assume that an
327 * L2 divisor of 3 will work.
329 _set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3
330 | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF);
332 /* Untested right now. */
333 if (cur_cpu_spec[0]->cpu_features & CPU_FTR_L3CR) {
335 _set_L3CR(0x8f032000);
340 #define SANDPOINT_87308_CFG_ADDR 0x15c
341 #define SANDPOINT_87308_CFG_DATA 0x15d
343 #define SANDPOINT_87308_CFG_INB(addr, byte) { \
344 outb((addr), SANDPOINT_87308_CFG_ADDR); \
345 (byte) = inb(SANDPOINT_87308_CFG_DATA); \
348 #define SANDPOINT_87308_CFG_OUTB(addr, byte) { \
349 outb((addr), SANDPOINT_87308_CFG_ADDR); \
350 outb((byte), SANDPOINT_87308_CFG_DATA); \
353 #define SANDPOINT_87308_SELECT_DEV(dev_num) { \
354 SANDPOINT_87308_CFG_OUTB(0x07, (dev_num)); \
357 #define SANDPOINT_87308_DEV_ENABLE(dev_num) { \
358 SANDPOINT_87308_SELECT_DEV(dev_num); \
359 SANDPOINT_87308_CFG_OUTB(0x30, 0x01); \
363 * To probe the Sandpoint type, we need to check for a connection between GPIO
364 * pins 6 and 7 on the NS87308 SuperIO.
366 static void __init sandpoint_probe_type(void)
369 /* First, ensure that the GPIO pins are enabled. */
370 SANDPOINT_87308_SELECT_DEV(0x07); /* Select GPIO logical device */
371 SANDPOINT_87308_CFG_OUTB(0x60, 0x07); /* Base address 0x700 */
372 SANDPOINT_87308_CFG_OUTB(0x61, 0x00);
373 SANDPOINT_87308_CFG_OUTB(0x30, 0x01); /* Enable */
375 /* Now, set pin 7 to output and pin 6 to input. */
376 outb((inb(0x701) | 0x80) & 0xbf, 0x701);
377 /* Set push-pull output */
378 outb(inb(0x702) | 0x80, 0x702);
379 /* Set pull-up on input */
380 outb(inb(0x703) | 0x40, 0x703);
381 /* Set output high and check */
383 outb(x | 0x80, 0x700);
385 sandpoint_is_x2 = ! (x & 0x40);
386 if (ppc_md.progress && sandpoint_is_x2)
387 ppc_md.progress("High output says X2", 0);
388 /* Set output low and check */
389 outb(x & 0x7f, 0x700);
390 sandpoint_is_x2 |= inb(0x700) & 0x40;
391 if (ppc_md.progress && sandpoint_is_x2)
392 ppc_md.progress("Low output says X2", 0);
393 if (ppc_md.progress && ! sandpoint_is_x2)
394 ppc_md.progress("Sandpoint is X3", 0);
398 * Fix IDE interrupts.
401 sandpoint_fix_winbond_83553(void)
403 /* Make some 8259 interrupt level sensitive */
410 arch_initcall(sandpoint_fix_winbond_83553);
413 * Initialize the ISA devices on the Nat'l PC87308VUL SuperIO chip.
416 sandpoint_setup_natl_87308(void)
421 * Enable all the devices on the Super I/O chip.
423 SANDPOINT_87308_SELECT_DEV(0x00); /* Select kbd logical device */
424 SANDPOINT_87308_CFG_OUTB(0xf0, 0x00); /* Set KBC clock to 8 Mhz */
425 SANDPOINT_87308_DEV_ENABLE(0x00); /* Enable keyboard */
426 SANDPOINT_87308_DEV_ENABLE(0x01); /* Enable mouse */
427 SANDPOINT_87308_DEV_ENABLE(0x02); /* Enable rtc */
428 SANDPOINT_87308_DEV_ENABLE(0x03); /* Enable fdc (floppy) */
429 SANDPOINT_87308_DEV_ENABLE(0x04); /* Enable parallel */
430 SANDPOINT_87308_DEV_ENABLE(0x05); /* Enable UART 2 */
431 SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
432 SANDPOINT_87308_DEV_ENABLE(0x06); /* Enable UART 1 */
433 SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
435 /* Set up floppy in PS/2 mode */
436 outb(0x09, SIO_CONFIG_RA);
437 reg = inb(SIO_CONFIG_RD);
438 reg = (reg & 0x3F) | 0x40;
439 outb(reg, SIO_CONFIG_RD);
440 outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
445 arch_initcall(sandpoint_setup_natl_87308);
448 sandpoint_request_io(void)
450 request_region(0x00,0x20,"dma1");
451 request_region(0x20,0x20,"pic1");
452 request_region(0x40,0x20,"timer");
453 request_region(0x80,0x10,"dma page reg");
454 request_region(0xa0,0x20,"pic2");
455 request_region(0xc0,0x20,"dma2");
460 arch_initcall(sandpoint_request_io);
463 * Interrupt setup and service. Interrrupts on the Sandpoint come
464 * from the four PCI slots plus the 8259 in the Winbond Super I/O (SIO).
465 * The 8259 is cascaded from EPIC IRQ0, IRQ1-4 map to PCI slots 1-4,
466 * IDE is on EPIC 7 and 8.
469 sandpoint_init_IRQ(void)
473 OpenPIC_InitSenses = sandpoint_openpic_initsenses;
474 OpenPIC_NumInitSenses = sizeof(sandpoint_openpic_initsenses);
476 mpc10x_set_openpic();
477 openpic_hookup_cascade(sandpoint_is_x2 ? 17 : NUM_8259_INTERRUPTS, "82c59 cascade",
481 * openpic_init() has set up irq_desc[16-31] to be openpic
482 * interrupts. We need to set irq_desc[0-15] to be i8259
485 for(i=0; i < NUM_8259_INTERRUPTS; i++)
486 irq_desc[i].handler = &i8259_pic;
489 * The EPIC allows for a read in the range of 0xFEF00000 ->
490 * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
492 i8259_init(0xfef00000);
496 sandpoint_irq_canonicalize(u32 irq)
504 static unsigned long __init
505 sandpoint_find_end_of_memory(void)
507 bd_t *bp = (bd_t *)__res;
510 return bp->bi_memsize;
512 /* DINK32 13.0 correctly initalizes things, so iff you use
513 * this you _should_ be able to change this instead of a
514 * hardcoded value. */
516 return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
523 sandpoint_map_io(void)
525 io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
529 sandpoint_restart(char *cmd)
533 /* Set exception prefix high - to the firmware */
534 _nmask_and_or_msr(0, MSR_IP);
536 /* Reset system via Port 92 */
539 for(;;); /* Spin until reset happens */
543 sandpoint_power_off(void)
546 for(;;); /* No way to shut power off with software */
553 sandpoint_power_off();
558 sandpoint_show_cpuinfo(struct seq_file *m)
560 seq_printf(m, "vendor\t\t: Motorola SPS\n");
561 seq_printf(m, "machine\t\t: Sandpoint\n");
566 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
570 static int sandpoint_ide_ports_known = 0;
571 static unsigned long sandpoint_ide_regbase[MAX_HWIFS];
572 static unsigned long sandpoint_ide_ctl_regbase[MAX_HWIFS];
573 static unsigned long sandpoint_idedma_regbase;
576 sandpoint_ide_probe(void)
578 struct pci_dev *pdev = pci_get_device(PCI_VENDOR_ID_WINBOND,
579 PCI_DEVICE_ID_WINBOND_82C105, NULL);
582 sandpoint_ide_regbase[0]=pdev->resource[0].start;
583 sandpoint_ide_regbase[1]=pdev->resource[2].start;
584 sandpoint_ide_ctl_regbase[0]=pdev->resource[1].start;
585 sandpoint_ide_ctl_regbase[1]=pdev->resource[3].start;
586 sandpoint_idedma_regbase=pdev->resource[4].start;
590 sandpoint_ide_ports_known = 1;
594 sandpoint_ide_default_irq(unsigned long base)
596 if (sandpoint_ide_ports_known == 0)
597 sandpoint_ide_probe();
599 if (base == sandpoint_ide_regbase[0])
600 return SANDPOINT_IDE_INT0;
601 else if (base == sandpoint_ide_regbase[1])
602 return SANDPOINT_IDE_INT1;
608 sandpoint_ide_default_io_base(int index)
610 if (sandpoint_ide_ports_known == 0)
611 sandpoint_ide_probe();
613 return sandpoint_ide_regbase[index];
617 sandpoint_ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port,
618 unsigned long ctrl_port, int *irq)
620 unsigned long reg = data_port;
621 uint alt_status_base;
624 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
625 hw->io_ports[i] = reg++;
628 if (data_port == sandpoint_ide_regbase[0]) {
629 alt_status_base = sandpoint_ide_ctl_regbase[0] + 2;
632 else if (data_port == sandpoint_ide_regbase[1]) {
633 alt_status_base = sandpoint_ide_ctl_regbase[1] + 2;
642 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
644 hw->io_ports[IDE_CONTROL_OFFSET] = alt_status_base;
654 * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1.
656 static __inline__ void
657 sandpoint_set_bat(void)
659 unsigned long bat3u, bat3l;
661 __asm__ __volatile__(
669 : "=r" (bat3u), "=r" (bat3l));
675 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
676 unsigned long r6, unsigned long r7)
678 parse_bootinfo(find_bootinfo());
680 /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer)
681 * are non-zero, then we should use the board info from the bd_t
682 * structure and the cmdline pointed to by r6 instead of the
683 * information from birecs, if any. Otherwise, use the information
684 * from birecs as discovered by the preceeding call to
685 * parse_bootinfo(). This rule should work with both PPCBoot, which
686 * uses a bd_t board info structure, and the kernel boot wrapper,
690 /* copy board info structure */
691 memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
692 /* copy command line */
693 *(char *)(r7+KERNELBASE) = 0;
694 strcpy(cmd_line, (char *)(r6+KERNELBASE));
697 #ifdef CONFIG_BLK_DEV_INITRD
698 /* take care of initrd if we have one */
700 initrd_start = r4 + KERNELBASE;
701 initrd_end = r5 + KERNELBASE;
703 #endif /* CONFIG_BLK_DEV_INITRD */
705 /* Map in board regs, etc. */
708 isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
709 isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
710 pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
711 ISA_DMA_THRESHOLD = 0x00ffffff;
712 DMA_MODE_READ = 0x44;
713 DMA_MODE_WRITE = 0x48;
715 ppc_md.setup_arch = sandpoint_setup_arch;
716 ppc_md.show_cpuinfo = sandpoint_show_cpuinfo;
717 ppc_md.irq_canonicalize = sandpoint_irq_canonicalize;
718 ppc_md.init_IRQ = sandpoint_init_IRQ;
719 ppc_md.get_irq = openpic_get_irq;
721 ppc_md.restart = sandpoint_restart;
722 ppc_md.power_off = sandpoint_power_off;
723 ppc_md.halt = sandpoint_halt;
725 ppc_md.find_end_of_memory = sandpoint_find_end_of_memory;
726 ppc_md.setup_io_mappings = sandpoint_map_io;
728 TODC_INIT(TODC_TYPE_PC97307, 0x70, 0x00, 0x71, 8);
729 ppc_md.time_init = todc_time_init;
730 ppc_md.set_rtc_time = todc_set_rtc_time;
731 ppc_md.get_rtc_time = todc_get_rtc_time;
732 ppc_md.calibrate_decr = todc_calibrate_decr;
734 ppc_md.nvram_read_val = todc_mc146818_read_val;
735 ppc_md.nvram_write_val = todc_mc146818_write_val;
738 ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
740 #ifdef CONFIG_SERIAL_TEXT_DEBUG
741 ppc_md.progress = gen550_progress;
744 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
745 ppc_ide_md.default_irq = sandpoint_ide_default_irq;
746 ppc_ide_md.default_io_base = sandpoint_ide_default_io_base;
747 ppc_ide_md.ide_init_hwif = sandpoint_ide_init_hwif_ports;