2 * arch/ppc/platforms/sandpoint_setup.c
4 * Board setup routines for the Motorola SPS Sandpoint Test Platform.
6 * Author: Mark A. Greer
9 * 2000-2003 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
16 * This file adds support for the Motorola SPS Sandpoint Test Platform.
17 * These boards have a PPMC slot for the processor so any combination
18 * of cpu and host bridge can be attached. This port is for an 8240 PPMC
19 * module from Motorola SPS and other closely related cpu/host bridge
20 * combinations (e.g., 750/755/7400 with MPC107 host bridge).
21 * The sandpoint itself has a Windbond 83c553 (PCI-ISA bridge, 2 DMA ctlrs, 2
22 * cascaded 8259 interrupt ctlrs, 8254 Timer/Counter, and an IDE ctlr), a
23 * National 87308 (RTC, 2 UARTs, Keyboard & mouse ctlrs, and a floppy ctlr),
24 * and 4 PCI slots (only 2 of which are usable; the other 2 are keyed for 3.3V
27 * The firmware on the sandpoint is called DINK (not my acronym :). This port
28 * depends on DINK to do some basic initialization (e.g., initialize the memory
29 * ctlr) and to ensure that the processor is using MAP B (CHRP map).
31 * The switch settings for the Sandpoint board MUST be as follows:
37 * 'down' is in the direction from the PCI slots towards the PPMC slot;
38 * 'up' is in the direction from the PPMC slot towards the PCI slots.
39 * Be careful, the way the sandpoint board is installed in XT chasses will
40 * make the directions reversed.
42 * Since Motorola listened to our suggestions for improvement, we now have
43 * the Sandpoint X3 board. All of the PCI slots are available, it uses
44 * the serial interrupt interface (just a hardware thing we need to
45 * configure properly).
47 * Use the default X3 switch settings. The interrupts are then:
49 * 0 SIOINT (8259, active low)
54 * 7 Winbond INTC (IDE interrupt)
55 * 8 Winbond INTD (IDE interrupt)
58 * Motorola has finally released a version of DINK32 that correctly
59 * (seemingly) initalizes the memory controller correctly, regardless
60 * of the amount of memory in the system. Once a method of determining
61 * what version of DINK initializes the system for us, if applicable, is
62 * found, we can hopefully stop hardcoding 32MB of RAM.
64 * It is important to note that this code only supports the Sandpoint X3
65 * (all flavors) platform, and it does not support the X2 anymore. Code
66 * that at one time worked on the X2 can be found at:
67 * ftp://source.mvista.com/pub/linuxppc/obsolete/sandpoint/
70 #include <linux/config.h>
71 #include <linux/stddef.h>
72 #include <linux/kernel.h>
73 #include <linux/init.h>
74 #include <linux/errno.h>
75 #include <linux/reboot.h>
76 #include <linux/pci.h>
77 #include <linux/kdev_t.h>
78 #include <linux/major.h>
79 #include <linux/initrd.h>
80 #include <linux/console.h>
81 #include <linux/delay.h>
82 #include <linux/irq.h>
83 #include <linux/ide.h>
84 #include <linux/seq_file.h>
85 #include <linux/root_dev.h>
86 #include <linux/serial.h>
87 #include <linux/tty.h> /* for linux/serial_core.h */
88 #include <linux/serial_core.h>
90 #include <asm/system.h>
91 #include <asm/pgtable.h>
96 #include <asm/machdep.h>
100 #include <asm/open_pic.h>
101 #include <asm/i8259.h>
102 #include <asm/todc.h>
103 #include <asm/bootinfo.h>
104 #include <asm/mpc10x.h>
105 #include <asm/pci-bridge.h>
106 #include <asm/kgdb.h>
108 #include "sandpoint.h"
110 unsigned char __res[sizeof(bd_t)];
112 static void sandpoint_halt(void);
115 * Define all of the IRQ senses and polarities. Taken from the
116 * Sandpoint X3 User's manual.
118 static u_char sandpoint_openpic_initsenses[] __initdata = {
119 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 0: SIOINT */
120 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 2: PCI Slot 1 */
121 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 3: PCI Slot 2 */
122 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 4: PCI Slot 3 */
123 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 5: PCI Slot 4 */
124 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 8: IDE (INT C) */
125 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE) /* 9: IDE (INT D) */
129 * Motorola SPS Sandpoint interrupt routing.
132 sandpoint_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
134 static char pci_irq_table[][4] =
136 * PCI IDSEL/INTPIN->INTLINE
140 { 16, 0, 0, 0 }, /* IDSEL 11 - i8259 on Winbond */
141 { 0, 0, 0, 0 }, /* IDSEL 12 - unused */
142 { 18, 21, 20, 19 }, /* IDSEL 13 - PCI slot 1 */
143 { 19, 18, 21, 20 }, /* IDSEL 14 - PCI slot 2 */
144 { 20, 19, 18, 21 }, /* IDSEL 15 - PCI slot 3 */
145 { 21, 20, 19, 18 }, /* IDSEL 16 - PCI slot 4 */
148 const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
149 return PCI_IRQ_TABLE_LOOKUP;
153 sandpoint_setup_winbond_83553(struct pci_controller *hose)
158 * Route IDE interrupts directly to the 8259's IRQ 14 & 15.
159 * We can't route the IDE interrupt to PCI INTC# or INTD# because those
160 * woule interfere with the PMC's INTC# and INTD# lines.
165 devfn = PCI_DEVFN(11,0);
167 early_write_config_byte(hose,
170 0x43, /* IDE Interrupt Routing Control */
172 early_write_config_word(hose,
175 0x44, /* PCI Interrupt Routing Control */
178 /* Want ISA memory cycles to be forwarded to PCI bus */
179 early_write_config_byte(hose,
182 0x48, /* ISA-to-PCI Addr Decoder Control */
185 /* Enable RTC and Keyboard address locations. */
186 early_write_config_byte(hose,
189 0x4d, /* Chip Select Control Register */
192 /* Enable Port 92. */
193 early_write_config_byte(hose,
196 0x4e, /* AT System Control Register */
201 devfn = PCI_DEVFN(11,1);
203 /* Put IDE controller into native mode. */
204 early_write_config_byte(hose,
207 0x09, /* Programming interface Register */
210 /* Init IRQ routing, enable both ports, disable fast 16 */
211 early_write_config_dword(hose,
214 0x40, /* IDE Control/Status Register */
220 sandpoint_find_bridges(void)
222 struct pci_controller *hose;
224 hose = pcibios_alloc_controller();
229 hose->first_busno = 0;
230 hose->last_busno = 0xff;
232 if (mpc10x_bridge_init(hose,
235 MPC10X_MAPB_EUMB_BASE) == 0) {
237 /* Do early winbond init, then scan PCI bus */
238 sandpoint_setup_winbond_83553(hose);
239 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
241 ppc_md.pcibios_fixup = NULL;
242 ppc_md.pcibios_fixup_bus = NULL;
243 ppc_md.pci_swizzle = common_swizzle;
244 ppc_md.pci_map_irq = sandpoint_map_irq;
248 ppc_md.progress("Bridge init failed", 0x100);
249 printk("Host bridge init failed\n");
255 #if defined(CONFIG_SERIAL_8250) && \
256 (defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG))
258 sandpoint_early_serial_map(void)
260 struct uart_port serial_req;
262 /* Setup serial port access */
263 memset(&serial_req, 0, sizeof(serial_req));
264 serial_req.uartclk = UART_CLK;
266 serial_req.flags = STD_COM_FLAGS;
267 serial_req.iotype = SERIAL_IO_MEM;
268 serial_req.membase = (u_char *)SANDPOINT_SERIAL_0;
270 gen550_init(0, &serial_req);
272 if (early_serial_setup(&serial_req) != 0)
273 printk(KERN_ERR "Early serial init of port 0 failed\n");
275 /* Assume early_serial_setup() doesn't modify serial_req */
277 serial_req.irq = 3; /* XXXX */
278 serial_req.membase = (u_char *)SANDPOINT_SERIAL_1;
280 gen550_init(1, &serial_req);
282 if (early_serial_setup(&serial_req) != 0)
283 printk(KERN_ERR "Early serial init of port 1 failed\n");
288 sandpoint_setup_arch(void)
290 loops_per_jiffy = 100000000 / HZ;
292 #ifdef CONFIG_BLK_DEV_INITRD
294 ROOT_DEV = Root_RAM0;
297 #ifdef CONFIG_ROOT_NFS
300 ROOT_DEV = Root_HDA1;
303 /* Lookup PCI host bridges */
304 sandpoint_find_bridges();
306 #ifdef CONFIG_DUMMY_CONSOLE
307 conswitchp = &dummy_con;
310 printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n");
311 printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
313 /* DINK32 12.3 and below do not correctly enable any caches.
314 * We will do this now with good known values. Future versions
315 * of DINK32 are supposed to get this correct.
317 if (cur_cpu_spec[0]->cpu_features & CPU_FTR_SPEC7450)
318 /* 745x is different. We only want to pass along enable. */
320 else if (cur_cpu_spec[0]->cpu_features & CPU_FTR_L2CR)
321 /* All modules have 1MB of L2. We also assume that an
322 * L2 divisor of 3 will work.
324 _set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3
325 | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF);
327 /* Untested right now. */
328 if (cur_cpu_spec[0]->cpu_features & CPU_FTR_L3CR) {
330 _set_L3CR(0x8f032000);
335 #define SANDPOINT_87308_CFG_ADDR 0x15c
336 #define SANDPOINT_87308_CFG_DATA 0x15d
338 #define SANDPOINT_87308_CFG_INB(addr, byte) { \
339 outb((addr), SANDPOINT_87308_CFG_ADDR); \
340 (byte) = inb(SANDPOINT_87308_CFG_DATA); \
343 #define SANDPOINT_87308_CFG_OUTB(addr, byte) { \
344 outb((addr), SANDPOINT_87308_CFG_ADDR); \
345 outb((byte), SANDPOINT_87308_CFG_DATA); \
348 #define SANDPOINT_87308_SELECT_DEV(dev_num) { \
349 SANDPOINT_87308_CFG_OUTB(0x07, (dev_num)); \
352 #define SANDPOINT_87308_DEV_ENABLE(dev_num) { \
353 SANDPOINT_87308_SELECT_DEV(dev_num); \
354 SANDPOINT_87308_CFG_OUTB(0x30, 0x01); \
358 * Fix IDE interrupts.
361 sandpoint_fix_winbond_83553(void)
363 /* Make all 8259 interrupt level sensitive */
370 arch_initcall(sandpoint_fix_winbond_83553);
373 * Initialize the ISA devices on the Nat'l PC87308VUL SuperIO chip.
376 sandpoint_setup_natl_87308(void)
381 * Enable all the devices on the Super I/O chip.
383 SANDPOINT_87308_SELECT_DEV(0x00); /* Select kbd logical device */
384 SANDPOINT_87308_CFG_OUTB(0xf0, 0x00); /* Set KBC clock to 8 Mhz */
385 SANDPOINT_87308_DEV_ENABLE(0x00); /* Enable keyboard */
386 SANDPOINT_87308_DEV_ENABLE(0x01); /* Enable mouse */
387 SANDPOINT_87308_DEV_ENABLE(0x02); /* Enable rtc */
388 SANDPOINT_87308_DEV_ENABLE(0x03); /* Enable fdc (floppy) */
389 SANDPOINT_87308_DEV_ENABLE(0x04); /* Enable parallel */
390 SANDPOINT_87308_DEV_ENABLE(0x05); /* Enable UART 2 */
391 SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
392 SANDPOINT_87308_DEV_ENABLE(0x06); /* Enable UART 1 */
393 SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
395 /* Set up floppy in PS/2 mode */
396 outb(0x09, SIO_CONFIG_RA);
397 reg = inb(SIO_CONFIG_RD);
398 reg = (reg & 0x3F) | 0x40;
399 outb(reg, SIO_CONFIG_RD);
400 outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
405 arch_initcall(sandpoint_setup_natl_87308);
408 sandpoint_request_io(void)
410 request_region(0x00,0x20,"dma1");
411 request_region(0x20,0x20,"pic1");
412 request_region(0x40,0x20,"timer");
413 request_region(0x80,0x10,"dma page reg");
414 request_region(0xa0,0x20,"pic2");
415 request_region(0xc0,0x20,"dma2");
420 arch_initcall(sandpoint_request_io);
423 * Interrupt setup and service. Interrrupts on the Sandpoint come
424 * from the four PCI slots plus the 8259 in the Winbond Super I/O (SIO).
425 * The 8259 is cascaded from EPIC IRQ0, IRQ1-4 map to PCI slots 1-4,
426 * IDE is on EPIC 7 and 8.
429 sandpoint_init_IRQ(void)
433 OpenPIC_InitSenses = sandpoint_openpic_initsenses;
434 OpenPIC_NumInitSenses = sizeof(sandpoint_openpic_initsenses);
437 * We need to tell openpic_set_sources where things actually are.
438 * mpc10x_common will setup OpenPIC_Addr at ioremap(EUMB phys base +
439 * EPIC offset (0x40000)); The EPIC IRQ Register Address Map -
440 * Interrupt Source Configuration Registers gives these numbers
441 * as offsets starting at 0x50200, we need to adjust occordinly.
443 /* Map serial interrupts 0-15 */
444 openpic_set_sources(0, 16, OpenPIC_Addr + 0x10200);
446 openpic_init(NUM_8259_INTERRUPTS);
447 openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
451 * openpic_init() has set up irq_desc[16-31] to be openpic
452 * interrupts. We need to set irq_desc[0-15] to be i8259
455 for(i=0; i < NUM_8259_INTERRUPTS; i++)
456 irq_desc[i].handler = &i8259_pic;
459 * The EPIC allows for a read in the range of 0xFEF00000 ->
460 * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
462 i8259_init(0xfef00000);
466 sandpoint_irq_canonicalize(u32 irq)
474 static unsigned long __init
475 sandpoint_find_end_of_memory(void)
477 bd_t *bp = (bd_t *)__res;
480 return bp->bi_memsize;
482 /* DINK32 13.0 correctly initalizes things, so iff you use
483 * this you _should_ be able to change this instead of a
484 * hardcoded value. */
486 return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
493 sandpoint_map_io(void)
495 io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
499 sandpoint_restart(char *cmd)
503 /* Set exception prefix high - to the firmware */
504 _nmask_and_or_msr(0, MSR_IP);
506 /* Reset system via Port 92 */
509 for(;;); /* Spin until reset happens */
513 sandpoint_power_off(void)
516 for(;;); /* No way to shut power off with software */
523 sandpoint_power_off();
528 sandpoint_show_cpuinfo(struct seq_file *m)
530 seq_printf(m, "vendor\t\t: Motorola SPS\n");
531 seq_printf(m, "machine\t\t: Sandpoint\n");
536 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
540 static int sandpoint_ide_ports_known = 0;
541 static unsigned long sandpoint_ide_regbase[MAX_HWIFS];
542 static unsigned long sandpoint_ide_ctl_regbase[MAX_HWIFS];
543 static unsigned long sandpoint_idedma_regbase;
546 sandpoint_ide_probe(void)
548 struct pci_dev *pdev = pci_find_device(PCI_VENDOR_ID_WINBOND,
549 PCI_DEVICE_ID_WINBOND_82C105, NULL);
552 sandpoint_ide_regbase[0]=pdev->resource[0].start;
553 sandpoint_ide_regbase[1]=pdev->resource[2].start;
554 sandpoint_ide_ctl_regbase[0]=pdev->resource[1].start;
555 sandpoint_ide_ctl_regbase[1]=pdev->resource[3].start;
556 sandpoint_idedma_regbase=pdev->resource[4].start;
559 sandpoint_ide_ports_known = 1;
563 sandpoint_ide_default_irq(unsigned long base)
565 if (sandpoint_ide_ports_known == 0)
566 sandpoint_ide_probe();
568 if (base == sandpoint_ide_regbase[0])
569 return SANDPOINT_IDE_INT0;
570 else if (base == sandpoint_ide_regbase[1])
571 return SANDPOINT_IDE_INT1;
577 sandpoint_ide_default_io_base(int index)
579 if (sandpoint_ide_ports_known == 0)
580 sandpoint_ide_probe();
582 return sandpoint_ide_regbase[index];
586 sandpoint_ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port,
587 unsigned long ctrl_port, int *irq)
589 unsigned long reg = data_port;
590 uint alt_status_base;
593 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
594 hw->io_ports[i] = reg++;
597 if (data_port == sandpoint_ide_regbase[0]) {
598 alt_status_base = sandpoint_ide_ctl_regbase[0] + 2;
601 else if (data_port == sandpoint_ide_regbase[1]) {
602 alt_status_base = sandpoint_ide_ctl_regbase[1] + 2;
611 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
613 hw->io_ports[IDE_CONTROL_OFFSET] = alt_status_base;
623 * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1.
625 static __inline__ void
626 sandpoint_set_bat(void)
628 unsigned long bat3u, bat3l;
630 __asm__ __volatile__(
638 : "=r" (bat3u), "=r" (bat3l));
644 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
645 unsigned long r6, unsigned long r7)
647 parse_bootinfo(find_bootinfo());
649 /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer)
650 * are non-zero, then we should use the board info from the bd_t
651 * structure and the cmdline pointed to by r6 instead of the
652 * information from birecs, if any. Otherwise, use the information
653 * from birecs as discovered by the preceeding call to
654 * parse_bootinfo(). This rule should work with both PPCBoot, which
655 * uses a bd_t board info structure, and the kernel boot wrapper,
659 /* copy board info structure */
660 memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
661 /* copy command line */
662 *(char *)(r7+KERNELBASE) = 0;
663 strcpy(cmd_line, (char *)(r6+KERNELBASE));
666 #ifdef CONFIG_BLK_DEV_INITRD
667 /* take care of initrd if we have one */
669 initrd_start = r4 + KERNELBASE;
670 initrd_end = r5 + KERNELBASE;
672 #endif /* CONFIG_BLK_DEV_INITRD */
674 /* Map in board regs, etc. */
677 isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
678 isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
679 pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
680 ISA_DMA_THRESHOLD = 0x00ffffff;
681 DMA_MODE_READ = 0x44;
682 DMA_MODE_WRITE = 0x48;
684 ppc_md.setup_arch = sandpoint_setup_arch;
685 ppc_md.show_cpuinfo = sandpoint_show_cpuinfo;
686 ppc_md.irq_canonicalize = sandpoint_irq_canonicalize;
687 ppc_md.init_IRQ = sandpoint_init_IRQ;
688 ppc_md.get_irq = openpic_get_irq;
690 ppc_md.restart = sandpoint_restart;
691 ppc_md.power_off = sandpoint_power_off;
692 ppc_md.halt = sandpoint_halt;
694 ppc_md.find_end_of_memory = sandpoint_find_end_of_memory;
695 ppc_md.setup_io_mappings = sandpoint_map_io;
697 TODC_INIT(TODC_TYPE_PC97307, 0x70, 0x00, 0x71, 8);
698 ppc_md.time_init = todc_time_init;
699 ppc_md.set_rtc_time = todc_set_rtc_time;
700 ppc_md.get_rtc_time = todc_get_rtc_time;
701 ppc_md.calibrate_decr = todc_calibrate_decr;
703 ppc_md.nvram_read_val = todc_mc146818_read_val;
704 ppc_md.nvram_write_val = todc_mc146818_write_val;
706 #if defined(CONFIG_SERIAL_8250) && \
707 (defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG))
708 sandpoint_early_serial_map();
710 ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
712 #ifdef CONFIG_SERIAL_TEXT_DEBUG
713 ppc_md.progress = gen550_progress;
717 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
718 ppc_ide_md.default_irq = sandpoint_ide_default_irq;
719 ppc_ide_md.default_io_base = sandpoint_ide_default_io_base;
720 ppc_ide_md.ide_init_hwif = sandpoint_ide_init_hwif_ports;