2 * Definitions for the IBM CPC710 PCI Host Bridge
4 * Author: Matt Porter <mporter@mvista.com>
6 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
12 #ifndef __PPC_PLATFORMS_CPC710_H
13 #define __PPC_PLATFORMS_CPC710_H
15 /* General bridge and memory controller registers */
16 #define PIDR 0xff000008
17 #define CNFR 0xff00000c
18 #define RSTR 0xff000010
19 #define UCTL 0xff001000
20 #define MPSR 0xff001010
21 #define SIOC 0xff001020
22 #define ABCNTL 0xff001030
23 #define SRST 0xff001040
24 #define ERRC 0xff001050
25 #define SESR 0xff001060
26 #define SEAR 0xff001070
27 #define SIOC1 0xff001090
28 #define PGCHP 0xff001100
29 #define GPDIR 0xff001130
30 #define GPOUT 0xff001150
31 #define ATAS 0xff001160
32 #define AVDG 0xff001170
33 #define MCCR 0xff001200
34 #define MESR 0xff001220
35 #define MEAR 0xff001230
36 #define MCER0 0xff001300
37 #define MCER1 0xff001310
38 #define MCER2 0xff001320
39 #define MCER3 0xff001330
40 #define MCER4 0xff001340
41 #define MCER5 0xff001350
42 #define MCER6 0xff001360
43 #define MCER7 0xff001370
46 * PCI32/64 configuration registers
47 * Given as offsets from their
48 * respective physical segment BAR
50 #define PIBAR 0x000f7800
51 #define PMBAR 0x000f7810
52 #define MSIZE 0x000f7f40
53 #define IOSIZE 0x000f7f60
54 #define SMBAR 0x000f7f80
55 #define SIBAR 0x000f7fc0
56 #define PSSIZE 0x000f8100
57 #define PPSIZE 0x000f8110
58 #define BARPS 0x000f8120
59 #define BARPP 0x000f8130
60 #define PSBAR 0x000f8140
61 #define PPBAR 0x000f8150
62 #define BPMDLK 0x000f8200 /* Bottom of Peripheral Memory Space */
63 #define TPMDLK 0x000f8210 /* Top of Peripheral Memory Space */
64 #define BIODLK 0x000f8220 /* Bottom of Peripheral I/O Space */
65 #define TIODLK 0x000f8230 /* Top of Perioheral I/O Space */
66 #define DLKCTRL 0x000f8240 /* Deadlock control */
67 #define DLKDEV 0x000f8250 /* Deadlock device */
69 /* System standard configuration registers space */
70 #define DCR 0xff200000
71 #define DID 0xff200004
72 #define BAR 0xff200018
74 /* Device specific configuration space */
75 #define PCIENB 0xff201000
77 /* Configuration space registers */
78 #define CPC710_BUS_NUMBER 0x40
79 #define CPC710_SUB_BUS_NUMBER 0x41
81 #endif /* __PPC_PLATFORMS_CPC710_H */