2 * General Purpose functions for the global management of the
3 * 8260 Communication Processor Module.
4 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
5 * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
8 * In addition to the individual control of the communication
9 * channels, there are a few functions that globally affect the
10 * communication processor.
12 * Buffer descriptors must be allocated from the dual ported memory
13 * space. The allocator for that is here. When the communication
14 * process is reset, we reclaim the memory available. There is
15 * currently no deallocator for this memory.
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/param.h>
21 #include <linux/string.h>
23 #include <linux/interrupt.h>
24 #include <linux/bootmem.h>
25 #include <linux/module.h>
27 #include <asm/mpc8260.h>
29 #include <asm/pgtable.h>
30 #include <asm/immap_cpm2.h>
32 #include <asm/rheap.h>
34 static void cpm2_dpinit(void);
35 cpm_cpm2_t *cpmp; /* Pointer to comm processor space */
37 /* We allocate this here because it is used almost exclusively for
38 * the communication processor devices.
40 cpm2_map_t *cpm2_immr;
45 cpm2_immr = (cpm2_map_t *)CPM_MAP_ADDR;
47 /* Reclaim the DP memory for our use.
51 /* Tell everyone where the comm processor resides.
53 cpmp = &cpm2_immr->im_cpm;
56 /* Set a baud rate generator. This needs lots of work. There are
57 * eight BRGs, which can be connected to the CPM channels or output
58 * as clocks. The BRGs are in two different block of internal
59 * memory mapped space.
60 * The baud rate clock is the system clock divided by something.
61 * It was set up long ago during the initial boot phase and is
63 * Baud rate clocks are zero-based in the driver code (as that maps
64 * to port numbers). Documentation uses 1-based numbering.
66 #define BRG_INT_CLK (((bd_t *)__res)->bi_brgfreq)
67 #define BRG_UART_CLK (BRG_INT_CLK/16)
69 /* This function is used by UARTS, or anything else that uses a 16x
73 cpm2_setbrg(uint brg, uint rate)
77 /* This is good enough to get SMCs running.....
80 bp = (uint *)&cpm2_immr->im_brgc1;
83 bp = (uint *)&cpm2_immr->im_brgc5;
87 *bp = ((BRG_UART_CLK / rate) << 1) | CPM_BRG_EN;
90 /* This function is used to set high speed synchronous baud rate
94 cpm2_fastbrg(uint brg, uint rate, int div16)
99 bp = (uint *)&cpm2_immr->im_brgc1;
102 bp = (uint *)&cpm2_immr->im_brgc5;
106 *bp = ((BRG_INT_CLK / rate) << 1) | CPM_BRG_EN;
108 *bp |= CPM_BRG_DIV16;
112 * dpalloc / dpfree bits.
114 static spinlock_t cpm_dpmem_lock;
115 /* 16 blocks should be enough to satisfy all requests
116 * until the memory subsystem goes up... */
117 static rh_block_t cpm_boot_dpmem_rh_block[16];
118 static rh_info_t cpm_dpmem_info;
120 static void cpm2_dpinit(void)
122 void *dprambase = &((cpm2_map_t *)CPM_MAP_ADDR)->im_dprambase;
124 spin_lock_init(&cpm_dpmem_lock);
126 /* initialize the info header */
127 rh_init(&cpm_dpmem_info, 1,
128 sizeof(cpm_boot_dpmem_rh_block) /
129 sizeof(cpm_boot_dpmem_rh_block[0]),
130 cpm_boot_dpmem_rh_block);
132 /* Attach the usable dpmem area */
133 /* XXX: This is actually crap. CPM_DATAONLY_BASE and
134 * CPM_DATAONLY_SIZE is only a subset of the available dpram. It
135 * varies with the processor and the microcode patches activated.
136 * But the following should be at least safe.
138 rh_attach_region(&cpm_dpmem_info, dprambase + CPM_DATAONLY_BASE,
142 /* This function used to return an index into the DPRAM area.
143 * Now it returns the actuall physical address of that area.
144 * use cpm2_dpram_offset() to get the index
146 void *cpm2_dpalloc(uint size, uint align)
151 spin_lock_irqsave(&cpm_dpmem_lock, flags);
152 cpm_dpmem_info.alignment = align;
153 start = rh_alloc(&cpm_dpmem_info, size, "commproc");
154 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
158 EXPORT_SYMBOL(cpm2_dpalloc);
160 int cpm2_dpfree(void *addr)
165 spin_lock_irqsave(&cpm_dpmem_lock, flags);
166 ret = rh_free(&cpm_dpmem_info, addr);
167 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
171 EXPORT_SYMBOL(cpm2_dpfree);
173 /* not sure if this is ever needed */
174 void *cpm2_dpalloc_fixed(void *addr, uint size, uint align)
179 spin_lock_irqsave(&cpm_dpmem_lock, flags);
180 cpm_dpmem_info.alignment = align;
181 start = rh_alloc_fixed(&cpm_dpmem_info, addr, size, "commproc");
182 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
186 EXPORT_SYMBOL(cpm2_dpalloc_fixed);
188 void cpm2_dpdump(void)
190 rh_dump(&cpm_dpmem_info);
192 EXPORT_SYMBOL(cpm2_dpdump);
194 uint cpm2_dpram_offset(void *addr)
196 return (uint)((u_char *)addr -
197 ((uint)((cpm2_map_t *)CPM_MAP_ADDR)->im_dprambase));
199 EXPORT_SYMBOL(cpm2_dpram_offset);
201 void *cpm2_dpram_addr(int offset)
203 return (void *)&((cpm2_map_t *)CPM_MAP_ADDR)->im_dprambase[offset];
205 EXPORT_SYMBOL(cpm2_dpram_addr);