1 /* The CPM2 internal interrupt controller. It is usually
2 * the only interrupt controller.
3 * There are two 32-bit registers (high/low) for up to 64
6 * Now, the fun starts.....Interrupt Numbers DO NOT MAP
7 * in a simple arithmetic fashion to mask or pending registers.
8 * That is, interrupt 4 does not map to bit position 4.
9 * We create two tables, indexed by vector number, to indicate
10 * which register to use and which bit in the register to use.
13 #include <linux/stddef.h>
14 #include <linux/init.h>
15 #include <linux/sched.h>
16 #include <linux/signal.h>
17 #include <linux/irq.h>
19 #include <asm/immap_cpm2.h>
20 #include <asm/mpc8260.h>
24 static u_char irq_to_siureg[] = {
25 1, 1, 1, 1, 1, 1, 1, 1,
26 1, 1, 1, 1, 1, 1, 1, 1,
27 0, 0, 0, 0, 0, 0, 0, 0,
28 0, 0, 0, 0, 0, 0, 0, 0,
29 1, 1, 1, 1, 1, 1, 1, 1,
30 1, 1, 1, 1, 1, 1, 1, 1,
31 0, 0, 0, 0, 0, 0, 0, 0,
32 0, 0, 0, 0, 0, 0, 0, 0
35 static u_char irq_to_siubit[] = {
36 31, 16, 17, 18, 19, 20, 21, 22,
37 23, 24, 25, 26, 27, 28, 29, 30,
38 29, 30, 16, 17, 18, 19, 20, 21,
39 22, 23, 24, 25, 26, 27, 28, 31,
40 0, 1, 2, 3, 4, 5, 6, 7,
41 8, 9, 10, 11, 12, 13, 14, 15,
42 15, 14, 13, 12, 11, 10, 9, 8,
43 7, 6, 5, 4, 3, 2, 1, 0
46 static void cpm2_mask_irq(unsigned int irq_nr)
51 bit = irq_to_siubit[irq_nr];
52 word = irq_to_siureg[irq_nr];
54 simr = &(cpm2_immr->im_intctl.ic_simrh);
55 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
56 simr[word] = ppc_cached_irq_mask[word];
59 static void cpm2_unmask_irq(unsigned int irq_nr)
64 bit = irq_to_siubit[irq_nr];
65 word = irq_to_siureg[irq_nr];
67 simr = &(cpm2_immr->im_intctl.ic_simrh);
68 ppc_cached_irq_mask[word] |= (1 << (31 - bit));
69 simr[word] = ppc_cached_irq_mask[word];
72 static void cpm2_mask_and_ack(unsigned int irq_nr)
75 volatile uint *simr, *sipnr;
77 bit = irq_to_siubit[irq_nr];
78 word = irq_to_siureg[irq_nr];
80 simr = &(cpm2_immr->im_intctl.ic_simrh);
81 sipnr = &(cpm2_immr->im_intctl.ic_sipnrh);
82 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
83 simr[word] = ppc_cached_irq_mask[word];
84 sipnr[word] = 1 << (31 - bit);
87 static void cpm2_end_irq(unsigned int irq_nr)
92 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
93 && irq_desc[irq_nr].action) {
95 bit = irq_to_siubit[irq_nr];
96 word = irq_to_siureg[irq_nr];
98 simr = &(cpm2_immr->im_intctl.ic_simrh);
99 ppc_cached_irq_mask[word] |= (1 << (31 - bit));
100 simr[word] = ppc_cached_irq_mask[word];
104 struct hw_interrupt_type cpm2_pic = {
117 cpm2_get_irq(struct pt_regs *regs)
122 /* For CPM2, read the SIVEC register and shift the bits down
123 * to get the irq number. */
124 bits = cpm2_immr->im_intctl.ic_sivec;