2 * arch/ppc/syslib/gt64260_common.c
4 * Common routines for the Marvell/Galileo GT64260 (Discovery) host bridge,
5 * interrupt controller, memory controller, serial controller, enet controller,
8 * Author: Mark A. Greer <mgreer@mvista.com>
10 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
17 * The GT64260 port is the result of hard work from many people from
18 * many companies. In particular, employees of Marvell/Galileo, Mission
19 * Critical Linux, Xyterra, and MontaVista Software were heavily involved.
23 * At last count, the 64260-B-0 has 65 errata and 24 restrictions. The odds of
24 * you getting it to work well, under stress, for a long period of time are
25 * low. If nothing else, you will likely run into an interrupt controller
28 * The newer 64260A-B-0 is much improved but has its own problems.
29 * Dave Wilhardt <dwilhardt@zyterra.com> has discovered that you must set
30 * up your PCI snoop regions to be prefetchable with 4-word bursts AND set the
31 * "Memory Write and Invalidate bit" (bit 4) in the cmd reg of each PCI device
32 * before coherency works between PCI and other devices. Many thanks to Dave.
34 * So far this code has been tested on Marvell/Galileo EV-64260-BP and
35 * an EV-64260A-BP uni-processor boards with 750 and 7400 processors.
36 * It has not yet been tested with a 7410 or 7450, or on an smp system.
38 * Note: I have not had any luck moving the base register address of the bridge
39 * with the gt64260_set_base() routine. I move it in the bootloader
40 * before starting the kernel. I haven't really looked into it so it
41 * may be an easy fix. -- MAG
43 #include <linux/kernel.h>
44 #include <linux/init.h>
45 #include <linux/pci.h>
46 #include <linux/slab.h>
48 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
52 #include <asm/machdep.h>
53 #include <asm/pci-bridge.h>
54 #include <asm/gt64260.h>
55 #include <asm/delay.h>
58 u32 gt64260_base; /* Virtual base address of 64260's regs */
59 u32 gt64260_revision; /* Revision of the chip */
60 u8 gt64260_pci_exclude_bridge = TRUE;
64 *****************************************************************************
66 * Bridge Initialization Routines
68 *****************************************************************************
70 static void gt64260_check_errata(struct pci_controller *hose_a,
71 struct pci_controller *hose_b);
74 * Typical '_find_bridges()' routine for boards with a GT64260 bridge.
77 gt64260_find_bridges(u32 phys_base_addr, gt64260_bridge_info_t *info,
78 int ((*map_irq)(struct pci_dev *, unsigned char, unsigned char)))
80 struct pci_controller *hose_a, *hose_b;
81 u32 io_base_a, io_base_b;
85 gt64260_base = (u32)ioremap(phys_base_addr,GT64260_INTERNAL_SPACE_SIZE);
87 hose_a = pcibios_alloc_controller();
91 hose_b = pcibios_alloc_controller();
95 info->hose_a = hose_a;
96 info->hose_b = hose_b;
98 /* Ends up mapping PCI Config addr/data pairs twice */
99 setup_indirect_pci(hose_a,
100 phys_base_addr + GT64260_PCI_0_CONFIG_ADDR,
101 phys_base_addr + GT64260_PCI_0_CONFIG_DATA);
103 setup_indirect_pci(hose_b,
104 phys_base_addr + GT64260_PCI_1_CONFIG_ADDR,
105 phys_base_addr + GT64260_PCI_1_CONFIG_DATA);
107 if ((rc = gt64260_bridge_init(info)) != 0) {
108 iounmap((void *)hose_a->cfg_addr);
109 iounmap((void *)hose_a->cfg_data);
110 iounmap((void *)hose_b->cfg_addr);
111 iounmap((void *)hose_b->cfg_data);
112 iounmap((void *)gt64260_base);
116 /* ioremap PCI I/O regions */
117 io_base_b = (u32)ioremap(info->pci_1_io_start_proc,info->pci_1_io_size);
118 io_base_a = (u32)ioremap(info->pci_0_io_start_proc,info->pci_0_io_size);
119 isa_io_base = io_base_a;
121 hose_a->first_busno = 0;
122 hose_a->last_busno = 0xff;
124 pci_init_resource(&hose_a->io_resource,
125 0, /* really: io_base_a - isa_io_base */
126 info->pci_0_io_size - 1,
128 "host bridge PCI bus 0");
129 hose_a->io_space.start = info->pci_0_io_start_pci;
130 hose_a->io_space.end = info->pci_0_io_start_pci +
131 info->pci_0_io_size - 1;
132 hose_a->io_base_virt = (void *)isa_io_base;
134 pci_init_resource(&hose_a->mem_resources[0],
135 info->pci_0_mem_start_proc,
136 info->pci_0_mem_start_proc + info->pci_0_mem_size - 1,
138 "host bridge PCI bus 0");
139 hose_a->mem_space.start = info->pci_0_mem_start_pci_lo;
140 hose_a->mem_space.end = info->pci_0_mem_start_pci_lo +
141 info->pci_0_mem_size - 1;
142 hose_a->pci_mem_offset = (info->pci_0_mem_start_proc -
143 info->pci_0_mem_start_pci_lo);
145 hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
148 hose_b->first_busno = hose_a->last_busno + 1;
149 hose_b->bus_offset = hose_b->first_busno;
150 hose_b->last_busno = 0xff;
152 pci_init_resource(&hose_b->io_resource,
153 io_base_b - isa_io_base,
154 io_base_b - isa_io_base + info->pci_1_io_size - 1,
156 "host bridge PCI bus 1");
157 hose_b->io_space.start = info->pci_1_io_start_pci;
158 hose_b->io_space.end = info->pci_1_io_start_pci +
159 info->pci_1_io_size - 1;
160 hose_b->io_base_virt = (void *)isa_io_base;
162 pci_init_resource(&hose_b->mem_resources[0],
163 info->pci_1_mem_start_proc,
164 info->pci_1_mem_start_proc + info->pci_1_mem_size - 1,
166 "host bridge PCI bus 1");
167 hose_b->mem_space.start = info->pci_1_mem_start_pci_lo;
168 hose_b->mem_space.end = info->pci_1_mem_start_pci_lo +
169 info->pci_1_mem_size - 1;
170 hose_b->pci_mem_offset = (info->pci_1_mem_start_proc -
171 info->pci_1_mem_start_pci_lo);
173 hose_b->last_busno = pciauto_bus_scan(hose_b, hose_b->first_busno);
176 ppc_md.pci_exclude_device = gt64260_pci_exclude_device;
177 ppc_md.pci_swizzle = common_swizzle;
178 ppc_md.pci_map_irq = map_irq;
181 } /* gt64260_find_bridges() */
184 * gt64260_bridge_init()
186 * Perform bridge initialization for a "typical" setup for a PPC system.
189 gt64260_bridge_init(gt64260_bridge_info_t *info)
198 * Count on firmware to set/clear other bits in this register.
200 * Set CPU CONFIG Reg bit:
204 * Clear CPU Config Reg bit:
206 * bit 27 - RemapWrDis
208 u32_val = gt_read(GT64260_CPU_CONFIG);
209 u32_val |= ((1<<13) | (1<<16));
210 u32_val &= ~((1<<8) | (1<<12) | (1<<27));
211 gt_write(GT64260_CPU_CONFIG, u32_val);
213 /* PCI 0/1 Timeout and Retry limits */
214 u32_val = gt_read(GT64260_PCI_0_TO_RETRY);
215 u32_val |= 0x0000ffff;
216 gt_write(GT64260_PCI_0_TO_RETRY, u32_val);
218 u32_val = gt_read(GT64260_PCI_1_TO_RETRY);
219 u32_val |= 0x0000ffff;
220 gt_write(GT64260_PCI_1_TO_RETRY, u32_val);
222 save_exclude = gt64260_pci_exclude_bridge;
223 gt64260_pci_exclude_bridge = FALSE;
225 /* Set class code to indicate host bridge */
226 early_read_config_dword(info->hose_a,
227 info->hose_a->first_busno,
231 u32_val &= 0x000000ff;
232 gt64260_revision = u32_val; /* a 64260 or 64260A? */
233 u32_val |= (PCI_CLASS_BRIDGE_HOST << 16);
234 early_write_config_dword(info->hose_a,
235 info->hose_a->first_busno,
240 early_read_config_dword(info->hose_b,
241 info->hose_b->first_busno,
245 u32_val &= 0x000000ff;
246 u32_val |= (PCI_CLASS_BRIDGE_HOST << 16);
247 early_write_config_dword(info->hose_b,
248 info->hose_b->first_busno,
253 /* Enable 64260 to be PCI master & respond to PCI MEM cycles */
254 early_read_config_word(info->hose_a,
255 info->hose_a->first_busno,
259 u16_val |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
260 early_write_config_word(info->hose_a,
261 info->hose_a->first_busno,
266 early_read_config_word(info->hose_b,
267 info->hose_b->first_busno,
271 u16_val |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
272 early_write_config_word(info->hose_b,
273 info->hose_b->first_busno,
278 gt64260_pci_exclude_bridge = save_exclude;
281 * Disable all CPU windows on the bridge except for SCS 0 which
282 * is covering all of system memory.:
284 gt64260_cpu_disable_all_windows();
287 * Set CPU snoop window to indicate all of system memory
288 * is covered with wirte-back cache.
290 gt64260_cpu_snoop_set_window(0,
293 GT64260_CPU_SNOOP_WB);
296 * Set up CPU->PCI mappings (so CPU can get at PCI dev regs/mem).
297 * Will only use one of the four CPU->PCI MEM windows on each bus.
299 gt64260_cpu_set_pci_io_window(0,
300 info->pci_0_io_start_proc,
301 info->pci_0_io_start_pci,
303 info->pci_0_io_swap);
305 gt64260_cpu_set_pci_mem_window(0,
307 info->pci_0_mem_start_proc,
308 info->pci_0_mem_start_pci_hi,
309 info->pci_0_mem_start_pci_lo,
310 info->pci_0_mem_size,
311 info->pci_0_mem_swap);
313 gt64260_cpu_set_pci_io_window(1,
314 info->pci_1_io_start_proc,
315 info->pci_1_io_start_pci,
317 info->pci_1_io_swap);
319 gt64260_cpu_set_pci_mem_window(1,
321 info->pci_1_mem_start_proc,
322 info->pci_1_mem_start_pci_hi,
323 info->pci_1_mem_start_pci_lo,
324 info->pci_1_mem_size,
325 info->pci_1_mem_swap);
328 * Set up PCI MEM->system memory mapping (bridge slave PCI window).
330 * Set BAR enables to allow only the SCS0 slave window to respond
331 * to PCI read/write cycles.
333 gt64260_pci_bar_enable(0, GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_0);
334 gt64260_pci_bar_enable(1, GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_0);
337 * For virt_to_bus & bus_to_virt to work correctly, this mapping
338 * must be the same on both PCI buses.
340 gt64260_pci_slave_scs_set_window(info->hose_a,
346 gt64260_pci_slave_scs_set_window(info->hose_b,
351 pci_dram_offset = 0; /* System mem at same addr on PCI & cpu bus */
353 /* Disable all the access control windows */
354 for (window=0; window<GT64260_PCI_ACC_CNTL_WINDOWS; window++) {
355 gt64260_pci_acc_cntl_set_window(0, window, 0, 0, 0, 0);
356 gt64260_pci_acc_cntl_set_window(1, window, 0, 0, 0, 0);
359 /* Disable all the PCI snoop regions */
360 for (window=0; window<GT64260_PCI_SNOOP_WINDOWS; window++) {
361 gt64260_pci_snoop_set_window(0, window, 0, 0, 0, 0);
362 gt64260_pci_snoop_set_window(1, window, 0, 0, 0, 0);
365 gt64260_pci_acc_cntl_set_window(0,
370 (GT64260_PCI_ACC_CNTL_PREFETCHEN |
371 GT64260_PCI_ACC_CNTL_MBURST_4_WORDS |
372 GT64260_PCI_ACC_CNTL_SWAP_BYTE));
374 gt64260_pci_acc_cntl_set_window(1,
379 (GT64260_PCI_ACC_CNTL_PREFETCHEN |
380 GT64260_PCI_ACC_CNTL_MBURST_4_WORDS |
381 GT64260_PCI_ACC_CNTL_SWAP_BYTE));
383 gt64260_pci_snoop_set_window(0,
388 GT64260_PCI_SNOOP_WB);
390 gt64260_pci_snoop_set_window(1,
395 GT64260_PCI_SNOOP_WB);
397 gt64260_check_errata(info->hose_a, info->hose_b);
400 /* Set latency timer (to 64) & cacheline size; clear BIST */
401 gt64260_pci_exclude_bridge = FALSE;
402 u32_val = ((0x04 << 8) | (L1_CACHE_LINE_SIZE / 4));
404 early_write_config_dword(info->hose_a,
405 info->hose_a->first_busno,
409 early_write_config_dword(info->hose_b,
410 info->hose_b->first_busno,
414 gt64260_pci_exclude_bridge = TRUE;
417 } /* gt64260_bridge_init() */
420 * gt64260_check_errata()
422 * Apply applicable errata and restrictions from 0.5 of the
423 * Errata and Restrictions document from Marvell/Galileo.
426 gt64260_check_errata(struct pci_controller *hose_a,
427 struct pci_controller *hose_b)
432 /* Currently 2 versions, 64260 and 64260A */
433 if (gt64260_revision == GT64260) {
434 save_exclude = gt64260_pci_exclude_bridge;
435 gt64260_pci_exclude_bridge = FALSE;
438 early_read_config_dword(hose_a,
443 val &= ~(PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY);
444 early_write_config_dword(hose_a,
450 early_read_config_dword(hose_b,
455 val &= ~(PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY);
456 early_write_config_dword(hose_b,
461 gt64260_pci_exclude_bridge = save_exclude;
464 gt_clr_bits(GT64260_PCI_0_CMD, ((1<<4) | (1<<5) | (1<<9)));
465 gt_clr_bits(GT64260_PCI_1_CMD, ((1<<4) | (1<<5) | (1<<9)));
468 gt_clr_bits(GT64260_CPU_SNOOP_BASE_0, 0xfffcf000);
469 gt_clr_bits(GT64260_CPU_SNOOP_BASE_1, 0xfffcf000);
470 gt_clr_bits(GT64260_CPU_SNOOP_BASE_2, 0xfffcf000);
471 gt_clr_bits(GT64260_CPU_SNOOP_BASE_3, 0xfffcf000);
474 gt_set_bits(GT64260_SDRAM_CONFIG, (1<<26));
476 } else if (gt64260_revision == GT64260A) {
478 gt_set_bits(GT64260_SDRAM_CONFIG, (1<<26));
480 /* No longer errata so turn on */
481 gt_set_bits(GT64260_PCI_0_CMD, ((1<<4) | (1<<5) | (1<<9)));
482 gt_set_bits(GT64260_PCI_1_CMD, ((1<<4) | (1<<5) | (1<<9)));
484 } /* gt64260_check_errata() */
488 *****************************************************************************
490 * General Window Setting Routines
492 *****************************************************************************
496 gt64260_set_32bit_window(u32 base_addr,
505 /* Set up the window on the CPU side */
506 gt_write(bot_reg, (base_addr >> 20) | other_bits);
507 gt_write(top_reg, (base_addr + size - 1) >> 20);
508 } else { /* Disable window */
509 gt_write(top_reg, 0x00000000);
510 gt_write(bot_reg, 0x00000fff | other_bits);
513 val = gt_read(bot_reg); /* Flush FIFO */
515 } /* gt64260_set_32bit_window() */
518 gt64260_set_64bit_window(u32 base_addr_hi,
528 if ((rc = gt64260_set_32bit_window(base_addr_lo,
534 gt_write(bot_reg_hi, base_addr_hi);
535 base_addr_hi = gt_read(bot_reg_hi); /* Flush FIFO */
539 } /* gt64260_set_64bit_window() */
543 *****************************************************************************
545 * CPU Configuration Routines
547 *****************************************************************************
551 gt64260_cpu_scs_set_window(u32 window,
556 cpu_scs_windows[GT64260_CPU_SCS_DECODE_WINDOWS][2] = {
557 { GT64260_CPU_SCS_DECODE_0_BOT, GT64260_CPU_SCS_DECODE_0_TOP },
558 { GT64260_CPU_SCS_DECODE_1_BOT, GT64260_CPU_SCS_DECODE_1_TOP },
559 { GT64260_CPU_SCS_DECODE_2_BOT, GT64260_CPU_SCS_DECODE_2_TOP },
560 { GT64260_CPU_SCS_DECODE_3_BOT, GT64260_CPU_SCS_DECODE_3_TOP },
561 }; /* cpu_scs_windows[][] */
564 if (window < GT64260_CPU_SCS_DECODE_WINDOWS) {
565 rc = gt64260_set_32bit_window(base_addr,
568 cpu_scs_windows[window][0],
569 cpu_scs_windows[window][1]);
573 } /* gt64260_cpu_scs_set_window() */
576 gt64260_cpu_cs_set_window(u32 window,
581 cpu_cs_windows[GT64260_CPU_CS_DECODE_WINDOWS][2] = {
582 { GT64260_CPU_CS_DECODE_0_BOT, GT64260_CPU_CS_DECODE_0_TOP },
583 { GT64260_CPU_CS_DECODE_1_BOT, GT64260_CPU_CS_DECODE_1_TOP },
584 { GT64260_CPU_CS_DECODE_2_BOT, GT64260_CPU_CS_DECODE_2_TOP },
585 { GT64260_CPU_CS_DECODE_3_BOT, GT64260_CPU_CS_DECODE_3_TOP },
586 }; /* cpu_cs_windows[][] */
589 if (window < GT64260_CPU_CS_DECODE_WINDOWS) {
590 rc = gt64260_set_32bit_window(base_addr,
593 cpu_cs_windows[window][0],
594 cpu_cs_windows[window][1]);
598 } /* gt64260_cpu_cs_set_window() */
601 gt64260_cpu_boot_set_window(u32 base_addr,
606 rc = gt64260_set_32bit_window(base_addr,
609 GT64260_CPU_BOOT_CS_DECODE_0_BOT,
610 GT64260_CPU_BOOT_CS_DECODE_0_TOP);
613 } /* gt64260_cpu_boot_set_window() */
616 * gt64260_cpu_set_pci_io_window()
618 * Set up a CPU window into PCI I/O or MEM space.
619 * Always do Read/Modify/Write to window regs.
622 gt64260_cpu_pci_set_window(u32 cpu_base_addr,
633 if ((rc = gt64260_set_32bit_window(cpu_base_addr,
639 /* Set up CPU->PCI remapping (on lower 32 bits) */
640 gt_write(remap_reg, pci_base_addr >> 20);
641 val = gt_read(bot_reg); /* Flush FIFO */
645 } /* gt64260_cpu_pci_set_window() */
649 * gt64260_cpu_set_pci_io_window()
651 * Set up a CPU window into PCI I/O space.
652 * Always do Read/Modify/Write to window regs.
655 gt64260_cpu_set_pci_io_window(u32 pci_bus,
661 /* 2 PCI buses with 1 I/O window each (from CPU point of view) */
663 cpu_pci_io_windows[GT64260_PCI_BUSES][3] = {
664 { GT64260_CPU_PCI_0_IO_DECODE_BOT,
665 GT64260_CPU_PCI_0_IO_DECODE_TOP,
666 GT64260_CPU_PCI_0_IO_REMAP },
668 { GT64260_CPU_PCI_1_IO_DECODE_BOT,
669 GT64260_CPU_PCI_1_IO_DECODE_TOP,
670 GT64260_CPU_PCI_1_IO_REMAP },
671 }; /* cpu_pci_io_windows[][] */
674 if (pci_bus < GT64260_PCI_BUSES) {
675 rc = gt64260_cpu_pci_set_window(cpu_base_addr,
679 cpu_pci_io_windows[pci_bus][0],
680 cpu_pci_io_windows[pci_bus][1],
681 cpu_pci_io_windows[pci_bus][2]);
685 } /* gt64260_cpu_set_pci_io_window() */
688 * gt64260_cpu_set_pci_mem_window()
690 * Set up a CPU window into PCI MEM space (4 PCI MEM windows per PCI bus).
691 * Always do Read/Modify/Write to window regs.
694 gt64260_cpu_set_pci_mem_window(u32 pci_bus,
697 u32 pci_base_addr_hi,
698 u32 pci_base_addr_lo,
702 /* 2 PCI buses with 4 memory windows each (from CPU point of view) */
704 cpu_pci_mem_windows[GT64260_PCI_BUSES][GT64260_PCI_MEM_WINDOWS_PER_BUS][4] = {
706 { GT64260_CPU_PCI_0_MEM_0_DECODE_BOT,
707 GT64260_CPU_PCI_0_MEM_0_DECODE_TOP,
708 GT64260_CPU_PCI_0_MEM_0_REMAP_HI,
709 GT64260_CPU_PCI_0_MEM_0_REMAP_LO },
711 { GT64260_CPU_PCI_0_MEM_1_DECODE_BOT,
712 GT64260_CPU_PCI_0_MEM_1_DECODE_TOP,
713 GT64260_CPU_PCI_0_MEM_1_REMAP_HI,
714 GT64260_CPU_PCI_0_MEM_1_REMAP_LO },
716 { GT64260_CPU_PCI_0_MEM_2_DECODE_BOT,
717 GT64260_CPU_PCI_0_MEM_2_DECODE_TOP,
718 GT64260_CPU_PCI_0_MEM_2_REMAP_HI,
719 GT64260_CPU_PCI_0_MEM_2_REMAP_LO },
721 { GT64260_CPU_PCI_0_MEM_3_DECODE_BOT,
722 GT64260_CPU_PCI_0_MEM_3_DECODE_TOP,
723 GT64260_CPU_PCI_0_MEM_3_REMAP_HI,
724 GT64260_CPU_PCI_0_MEM_3_REMAP_LO }
728 { GT64260_CPU_PCI_1_MEM_0_DECODE_BOT,
729 GT64260_CPU_PCI_1_MEM_0_DECODE_TOP,
730 GT64260_CPU_PCI_1_MEM_0_REMAP_HI,
731 GT64260_CPU_PCI_1_MEM_0_REMAP_LO },
733 { GT64260_CPU_PCI_1_MEM_1_DECODE_BOT,
734 GT64260_CPU_PCI_1_MEM_1_DECODE_TOP,
735 GT64260_CPU_PCI_1_MEM_1_REMAP_HI,
736 GT64260_CPU_PCI_1_MEM_1_REMAP_LO },
738 { GT64260_CPU_PCI_1_MEM_2_DECODE_BOT,
739 GT64260_CPU_PCI_1_MEM_2_DECODE_TOP,
740 GT64260_CPU_PCI_1_MEM_2_REMAP_HI,
741 GT64260_CPU_PCI_1_MEM_2_REMAP_LO },
743 { GT64260_CPU_PCI_1_MEM_3_DECODE_BOT,
744 GT64260_CPU_PCI_1_MEM_3_DECODE_TOP,
745 GT64260_CPU_PCI_1_MEM_3_REMAP_HI,
746 GT64260_CPU_PCI_1_MEM_3_REMAP_LO },
748 }; /* cpu_pci_mem_windows[][][] */
749 u32 remap_reg, remap;
752 if ((pci_bus < GT64260_PCI_BUSES) &&
753 (window < GT64260_PCI_MEM_WINDOWS_PER_BUS)) {
755 if (gt64260_cpu_pci_set_window(
760 cpu_pci_mem_windows[pci_bus][window][0],
761 cpu_pci_mem_windows[pci_bus][window][1],
762 cpu_pci_mem_windows[pci_bus][window][3]) == 0) {
764 remap_reg = cpu_pci_mem_windows[pci_bus][window][2];
765 gt_write(remap_reg, pci_base_addr_hi);
767 remap = gt_read(remap_reg); /* Flush FIFO */
774 } /* gt64260_cpu_set_pci_mem_window() */
777 gt64260_cpu_prot_set_window(u32 window,
783 cpu_prot_windows[GT64260_CPU_PROT_WINDOWS][2] = {
784 { GT64260_CPU_PROT_BASE_0, GT64260_CPU_PROT_TOP_0 },
785 { GT64260_CPU_PROT_BASE_1, GT64260_CPU_PROT_TOP_1 },
786 { GT64260_CPU_PROT_BASE_2, GT64260_CPU_PROT_TOP_2 },
787 { GT64260_CPU_PROT_BASE_3, GT64260_CPU_PROT_TOP_3 },
788 { GT64260_CPU_PROT_BASE_4, GT64260_CPU_PROT_TOP_4 },
789 { GT64260_CPU_PROT_BASE_5, GT64260_CPU_PROT_TOP_5 },
790 { GT64260_CPU_PROT_BASE_6, GT64260_CPU_PROT_TOP_6 },
791 { GT64260_CPU_PROT_BASE_7, GT64260_CPU_PROT_TOP_7 },
792 }; /* cpu_prot_windows[][] */
795 if (window < GT64260_CPU_PROT_WINDOWS) {
796 rc = gt64260_set_32bit_window(base_addr,
799 cpu_prot_windows[window][0],
800 cpu_prot_windows[window][1]);
804 } /* gt64260_cpu_prot_set_window() */
807 gt64260_cpu_snoop_set_window(u32 window,
813 cpu_snoop_windows[GT64260_CPU_SNOOP_WINDOWS][2] = {
814 { GT64260_CPU_SNOOP_BASE_0, GT64260_CPU_SNOOP_TOP_0 },
815 { GT64260_CPU_SNOOP_BASE_1, GT64260_CPU_SNOOP_TOP_1 },
816 { GT64260_CPU_SNOOP_BASE_2, GT64260_CPU_SNOOP_TOP_2 },
817 { GT64260_CPU_SNOOP_BASE_3, GT64260_CPU_SNOOP_TOP_3 },
818 }; /* cpu_snoop_windows[][] */
821 if ((window < GT64260_CPU_SNOOP_WINDOWS) &&
822 (snoop_type <= GT64260_CPU_SNOOP_WB)) {
824 rc = gt64260_set_32bit_window(base_addr,
827 cpu_snoop_windows[window][0],
828 cpu_snoop_windows[window][1]);
832 } /* gt64260_cpu_snoop_set_window() */
835 gt64260_cpu_disable_all_windows(void)
839 /* Don't disable SCS windows b/c we need to access system memory */
841 for (window=0; window<GT64260_CPU_CS_DECODE_WINDOWS; window++) {
842 gt64260_cpu_cs_set_window(window, 0, 0);
845 gt64260_cpu_boot_set_window(0, 0);
847 for (pci_bus=0; pci_bus<GT64260_PCI_BUSES; pci_bus++) {
848 gt64260_cpu_set_pci_io_window(pci_bus, 0, 0, 0, 0);
850 for (window=0;window<GT64260_PCI_MEM_WINDOWS_PER_BUS;window++) {
851 gt64260_cpu_set_pci_mem_window(pci_bus,
857 for (window=0; window<GT64260_CPU_PROT_WINDOWS; window++) {
858 gt64260_cpu_prot_set_window(window, 0, 0, 0);
861 for (window=0; window<GT64260_CPU_SNOOP_WINDOWS; window++) {
862 gt64260_cpu_snoop_set_window(window, 0, 0, 0);
866 } /* gt64260_cpu_disable_all_windows() */
870 *****************************************************************************
872 * PCI Slave Window Configuration Routines
874 *****************************************************************************
878 gt64260_pci_bar_enable(u32 pci_bus,
884 if (pci_bus < GT64260_PCI_BUSES) {
885 reg = (pci_bus == 0) ? GT64260_PCI_0_SLAVE_BAR_REG_ENABLES :
886 GT64260_PCI_1_SLAVE_BAR_REG_ENABLES;
889 /* Note: '0' enables, '1' disables */
891 val |= 0xffffffff; /* Disable everything by default */
895 gt_read(reg); /* Flush FIFO */
901 } /* gt64260_pci_bar_enable() */
904 gt64260_pci_slave_set_window(struct pci_controller *hose,
909 u32 pci_cfg_hdr_offset,
917 pci_base_addr &= 0xfffff000;
918 cpu_base_addr &= 0xfffff000;
919 bar_size &= 0xfffff000;
920 devfn = PCI_DEVFN(0, pci_cfg_fcn);
922 gt_write(bar_size_reg, (bar_size - 1) & 0xfffff000);
923 gt_write(remap_reg, cpu_base_addr);
924 gt_read(remap_reg); /* Flush FIFO */
926 save_exclude = gt64260_pci_exclude_bridge;
927 gt64260_pci_exclude_bridge = FALSE;
928 early_read_config_dword(hose,
934 early_write_config_dword(hose,
938 pci_base_addr | val);
939 gt64260_pci_exclude_bridge = save_exclude;
942 } /* gt64260_pci_slave_set_window() */
945 gt64260_pci_slave_scs_set_window(struct pci_controller *hose,
952 pci_scs_windows[GT64260_PCI_BUSES][GT64260_PCI_SCS_WINDOWS][4] = {
955 GT64260_PCI_0_SLAVE_SCS_0_SIZE,
956 GT64260_PCI_0_SLAVE_SCS_0_REMAP },
958 GT64260_PCI_0_SLAVE_SCS_1_SIZE,
959 GT64260_PCI_0_SLAVE_SCS_1_REMAP },
961 GT64260_PCI_0_SLAVE_SCS_2_SIZE,
962 GT64260_PCI_0_SLAVE_SCS_2_REMAP },
964 GT64260_PCI_0_SLAVE_SCS_3_SIZE,
965 GT64260_PCI_0_SLAVE_SCS_3_REMAP },
969 GT64260_PCI_1_SLAVE_SCS_0_SIZE,
970 GT64260_PCI_1_SLAVE_SCS_0_REMAP },
972 GT64260_PCI_1_SLAVE_SCS_1_SIZE,
973 GT64260_PCI_1_SLAVE_SCS_1_REMAP },
975 GT64260_PCI_1_SLAVE_SCS_2_SIZE,
976 GT64260_PCI_1_SLAVE_SCS_2_REMAP },
978 GT64260_PCI_1_SLAVE_SCS_3_SIZE,
979 GT64260_PCI_1_SLAVE_SCS_3_REMAP },
981 }; /* pci_scs_windows[][][] */
985 if (window < GT64260_PCI_SCS_WINDOWS) {
986 pci_bus = (hose->first_busno == 0) ? 0 : 1;
988 rc = gt64260_pci_slave_set_window(
993 pci_scs_windows[pci_bus][window][0],
994 pci_scs_windows[pci_bus][window][1],
995 pci_scs_windows[pci_bus][window][2],
996 pci_scs_windows[pci_bus][window][3]);
1000 } /* gt64260_pci_slave_scs_set_window() */
1003 gt64260_pci_slave_cs_set_window(struct pci_controller *hose,
1010 pci_cs_windows[GT64260_PCI_BUSES][GT64260_PCI_CS_WINDOWS][4] = {
1013 GT64260_PCI_0_SLAVE_CS_0_SIZE,
1014 GT64260_PCI_0_SLAVE_CS_0_REMAP },
1016 GT64260_PCI_0_SLAVE_CS_1_SIZE,
1017 GT64260_PCI_0_SLAVE_CS_1_REMAP },
1019 GT64260_PCI_0_SLAVE_CS_2_SIZE,
1020 GT64260_PCI_0_SLAVE_CS_2_REMAP },
1022 GT64260_PCI_0_SLAVE_CS_3_SIZE,
1023 GT64260_PCI_0_SLAVE_CS_3_REMAP },
1027 GT64260_PCI_1_SLAVE_CS_0_SIZE,
1028 GT64260_PCI_1_SLAVE_CS_0_REMAP },
1030 GT64260_PCI_1_SLAVE_CS_1_SIZE,
1031 GT64260_PCI_1_SLAVE_CS_1_REMAP },
1033 GT64260_PCI_1_SLAVE_CS_2_SIZE,
1034 GT64260_PCI_1_SLAVE_CS_2_REMAP },
1036 GT64260_PCI_1_SLAVE_CS_3_SIZE,
1037 GT64260_PCI_1_SLAVE_CS_3_REMAP },
1039 }; /* pci_cs_windows[][][] */
1043 if (window < GT64260_PCI_CS_WINDOWS) {
1044 pci_bus = (hose->first_busno == 0) ? 0 : 1;
1046 rc = gt64260_pci_slave_set_window(
1051 pci_cs_windows[pci_bus][window][0],
1052 pci_cs_windows[pci_bus][window][1],
1053 pci_cs_windows[pci_bus][window][2],
1054 pci_cs_windows[pci_bus][window][3]);
1058 } /* gt64260_pci_slave_cs_set_window() */
1061 gt64260_pci_slave_boot_set_window(struct pci_controller *hose,
1068 rc = gt64260_pci_slave_set_window(hose,
1074 GT64260_PCI_1_SLAVE_BOOT_SIZE,
1075 GT64260_PCI_1_SLAVE_BOOT_REMAP);
1078 } /* gt64260_pci_slave_boot_set_window() */
1081 gt64260_pci_slave_p2p_mem_set_window(struct pci_controller *hose,
1084 u32 other_bus_base_addr,
1088 pci_p2p_mem_windows[GT64260_PCI_BUSES][GT64260_PCI_P2P_MEM_WINDOWS][4]={
1091 GT64260_PCI_0_SLAVE_P2P_MEM_0_SIZE,
1092 GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_LO },
1094 GT64260_PCI_0_SLAVE_P2P_MEM_1_SIZE,
1095 GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_LO },
1099 GT64260_PCI_1_SLAVE_P2P_MEM_0_SIZE,
1100 GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_LO },
1102 GT64260_PCI_1_SLAVE_P2P_MEM_1_SIZE,
1103 GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_LO },
1105 }; /* pci_p2p_mem_windows[][][] */
1109 if (window < GT64260_PCI_P2P_MEM_WINDOWS) {
1110 pci_bus = (hose->first_busno == 0) ? 0 : 1;
1112 rc = gt64260_pci_slave_set_window(
1115 other_bus_base_addr,
1117 pci_p2p_mem_windows[pci_bus][window][0],
1118 pci_p2p_mem_windows[pci_bus][window][1],
1119 pci_p2p_mem_windows[pci_bus][window][2],
1120 pci_p2p_mem_windows[pci_bus][window][3]);
1124 } /* gt64260_pci_slave_p2p_mem_set_window() */
1127 gt64260_pci_slave_p2p_io_set_window(struct pci_controller *hose,
1129 u32 other_bus_base_addr,
1134 rc = gt64260_pci_slave_set_window(hose,
1136 other_bus_base_addr,
1140 GT64260_PCI_1_SLAVE_P2P_IO_SIZE,
1141 GT64260_PCI_1_SLAVE_P2P_IO_REMAP);
1144 } /* gt64260_pci_slave_p2p_io_set_window() */
1147 gt64260_pci_slave_dac_scs_set_window(struct pci_controller *hose,
1149 u32 pci_base_addr_hi,
1150 u32 pci_base_addr_lo,
1155 pci_dac_scs_windows[GT64260_PCI_BUSES][GT64260_PCI_DAC_SCS_WINDOWS][5]={
1158 GT64260_PCI_0_SLAVE_DAC_SCS_0_SIZE,
1159 GT64260_PCI_0_SLAVE_DAC_SCS_0_REMAP },
1161 GT64260_PCI_0_SLAVE_DAC_SCS_1_SIZE,
1162 GT64260_PCI_0_SLAVE_DAC_SCS_1_REMAP },
1164 GT64260_PCI_0_SLAVE_DAC_SCS_2_SIZE,
1165 GT64260_PCI_0_SLAVE_DAC_SCS_2_REMAP },
1167 GT64260_PCI_0_SLAVE_DAC_SCS_3_SIZE,
1168 GT64260_PCI_0_SLAVE_DAC_SCS_3_REMAP },
1172 GT64260_PCI_1_SLAVE_DAC_SCS_0_SIZE,
1173 GT64260_PCI_1_SLAVE_DAC_SCS_0_REMAP },
1175 GT64260_PCI_1_SLAVE_DAC_SCS_1_SIZE,
1176 GT64260_PCI_1_SLAVE_DAC_SCS_1_REMAP },
1178 GT64260_PCI_1_SLAVE_DAC_SCS_2_SIZE,
1179 GT64260_PCI_1_SLAVE_DAC_SCS_2_REMAP },
1181 GT64260_PCI_1_SLAVE_DAC_SCS_3_SIZE,
1182 GT64260_PCI_1_SLAVE_DAC_SCS_3_REMAP },
1184 }; /* pci_dac_scs_windows[][][] */
1188 if (window < GT64260_PCI_DAC_SCS_WINDOWS) {
1189 pci_bus = (hose->first_busno == 0) ? 0 : 1;
1191 rc = gt64260_pci_slave_set_window(
1196 pci_dac_scs_windows[pci_bus][window][0],
1197 pci_dac_scs_windows[pci_bus][window][1],
1198 pci_dac_scs_windows[pci_bus][window][3],
1199 pci_dac_scs_windows[pci_bus][window][4]);
1201 early_write_config_dword(
1204 PCI_DEVFN(0, pci_dac_scs_windows[pci_bus][window][0]),
1205 pci_dac_scs_windows[pci_bus][window][2],
1210 } /* gt64260_pci_slave_dac_scs_set_window() */
1213 gt64260_pci_slave_dac_cs_set_window(struct pci_controller *hose,
1215 u32 pci_base_addr_hi,
1216 u32 pci_base_addr_lo,
1221 pci_dac_cs_windows[GT64260_PCI_BUSES][GT64260_PCI_DAC_CS_WINDOWS][5] = {
1224 GT64260_PCI_0_SLAVE_DAC_CS_0_SIZE,
1225 GT64260_PCI_0_SLAVE_DAC_CS_0_REMAP },
1227 GT64260_PCI_0_SLAVE_DAC_CS_1_SIZE,
1228 GT64260_PCI_0_SLAVE_DAC_CS_1_REMAP },
1230 GT64260_PCI_0_SLAVE_DAC_CS_2_SIZE,
1231 GT64260_PCI_0_SLAVE_DAC_CS_2_REMAP },
1233 GT64260_PCI_0_SLAVE_DAC_CS_3_SIZE,
1234 GT64260_PCI_0_SLAVE_DAC_CS_3_REMAP },
1238 GT64260_PCI_1_SLAVE_DAC_CS_0_SIZE,
1239 GT64260_PCI_1_SLAVE_DAC_CS_0_REMAP },
1241 GT64260_PCI_1_SLAVE_DAC_CS_1_SIZE,
1242 GT64260_PCI_1_SLAVE_DAC_CS_1_REMAP },
1244 GT64260_PCI_1_SLAVE_DAC_CS_2_SIZE,
1245 GT64260_PCI_1_SLAVE_DAC_CS_2_REMAP },
1247 GT64260_PCI_1_SLAVE_DAC_CS_3_SIZE,
1248 GT64260_PCI_1_SLAVE_DAC_CS_3_REMAP },
1250 }; /* pci_dac_cs_windows[][][] */
1254 if (window < GT64260_PCI_CS_WINDOWS) {
1255 pci_bus = (hose->first_busno == 0) ? 0 : 1;
1257 rc = gt64260_pci_slave_set_window(
1262 pci_dac_cs_windows[pci_bus][window][0],
1263 pci_dac_cs_windows[pci_bus][window][1],
1264 pci_dac_cs_windows[pci_bus][window][3],
1265 pci_dac_cs_windows[pci_bus][window][4]);
1267 early_write_config_dword(
1270 PCI_DEVFN(0, pci_dac_cs_windows[pci_bus][window][0]),
1271 pci_dac_cs_windows[pci_bus][window][2],
1276 } /* gt64260_pci_slave_dac_cs_set_window() */
1279 gt64260_pci_slave_dac_boot_set_window(struct pci_controller *hose,
1280 u32 pci_base_addr_hi,
1281 u32 pci_base_addr_lo,
1287 rc = gt64260_pci_slave_set_window(hose,
1293 GT64260_PCI_1_SLAVE_BOOT_SIZE,
1294 GT64260_PCI_1_SLAVE_BOOT_REMAP);
1296 early_write_config_dword(hose,
1303 } /* gt64260_pci_slave_dac_boot_set_window() */
1306 gt64260_pci_slave_dac_p2p_mem_set_window(struct pci_controller *hose,
1308 u32 pci_base_addr_hi,
1309 u32 pci_base_addr_lo,
1310 u32 other_bus_base_addr,
1314 pci_dac_p2p_mem_windows[GT64260_PCI_BUSES][GT64260_PCI_DAC_P2P_MEM_WINDOWS][5] = {
1317 GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_SIZE,
1318 GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_LO },
1320 GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_SIZE,
1321 GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_LO },
1325 GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_SIZE,
1326 GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_LO },
1328 GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_SIZE,
1329 GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_LO },
1331 }; /* pci_dac_p2p_windows[][][] */
1335 if (window < GT64260_PCI_P2P_MEM_WINDOWS) {
1336 pci_bus = (hose->first_busno == 0) ? 0 : 1;
1338 rc = gt64260_pci_slave_set_window(
1341 other_bus_base_addr,
1343 pci_dac_p2p_mem_windows[pci_bus][window][0],
1344 pci_dac_p2p_mem_windows[pci_bus][window][1],
1345 pci_dac_p2p_mem_windows[pci_bus][window][3],
1346 pci_dac_p2p_mem_windows[pci_bus][window][4]);
1348 early_write_config_dword(
1351 PCI_DEVFN(0, pci_dac_p2p_mem_windows[pci_bus][window][0]),
1352 pci_dac_p2p_mem_windows[pci_bus][window][2],
1357 } /* gt64260_pci_slave_dac_p2p_mem_set_window() */
1361 *****************************************************************************
1363 * PCI Control Configuration Routines
1365 *****************************************************************************
1370 gt64260_pci_acc_cntl_set_window(u32 pci_bus,
1378 pci_acc_cntl_windows[GT64260_PCI_BUSES][GT64260_PCI_ACC_CNTL_WINDOWS][3] = {
1380 { GT64260_PCI_0_ACC_CNTL_0_BASE_HI,
1381 GT64260_PCI_0_ACC_CNTL_0_BASE_LO,
1382 GT64260_PCI_0_ACC_CNTL_0_TOP },
1384 { GT64260_PCI_0_ACC_CNTL_1_BASE_HI,
1385 GT64260_PCI_0_ACC_CNTL_1_BASE_LO,
1386 GT64260_PCI_0_ACC_CNTL_1_TOP },
1388 { GT64260_PCI_0_ACC_CNTL_2_BASE_HI,
1389 GT64260_PCI_0_ACC_CNTL_2_BASE_LO,
1390 GT64260_PCI_0_ACC_CNTL_2_TOP },
1392 { GT64260_PCI_0_ACC_CNTL_3_BASE_HI,
1393 GT64260_PCI_0_ACC_CNTL_3_BASE_LO,
1394 GT64260_PCI_0_ACC_CNTL_3_TOP },
1396 { GT64260_PCI_0_ACC_CNTL_4_BASE_HI,
1397 GT64260_PCI_0_ACC_CNTL_4_BASE_LO,
1398 GT64260_PCI_0_ACC_CNTL_4_TOP },
1400 { GT64260_PCI_0_ACC_CNTL_5_BASE_HI,
1401 GT64260_PCI_0_ACC_CNTL_5_BASE_LO,
1402 GT64260_PCI_0_ACC_CNTL_5_TOP },
1404 { GT64260_PCI_0_ACC_CNTL_6_BASE_HI,
1405 GT64260_PCI_0_ACC_CNTL_6_BASE_LO,
1406 GT64260_PCI_0_ACC_CNTL_6_TOP },
1408 { GT64260_PCI_0_ACC_CNTL_7_BASE_HI,
1409 GT64260_PCI_0_ACC_CNTL_7_BASE_LO,
1410 GT64260_PCI_0_ACC_CNTL_7_TOP },
1413 { GT64260_PCI_1_ACC_CNTL_0_BASE_HI,
1414 GT64260_PCI_1_ACC_CNTL_0_BASE_LO,
1415 GT64260_PCI_1_ACC_CNTL_0_TOP },
1417 { GT64260_PCI_1_ACC_CNTL_1_BASE_HI,
1418 GT64260_PCI_1_ACC_CNTL_1_BASE_LO,
1419 GT64260_PCI_1_ACC_CNTL_1_TOP },
1421 { GT64260_PCI_1_ACC_CNTL_2_BASE_HI,
1422 GT64260_PCI_1_ACC_CNTL_2_BASE_LO,
1423 GT64260_PCI_1_ACC_CNTL_2_TOP },
1425 { GT64260_PCI_1_ACC_CNTL_3_BASE_HI,
1426 GT64260_PCI_1_ACC_CNTL_3_BASE_LO,
1427 GT64260_PCI_1_ACC_CNTL_3_TOP },
1429 { GT64260_PCI_1_ACC_CNTL_4_BASE_HI,
1430 GT64260_PCI_1_ACC_CNTL_4_BASE_LO,
1431 GT64260_PCI_1_ACC_CNTL_4_TOP },
1433 { GT64260_PCI_1_ACC_CNTL_5_BASE_HI,
1434 GT64260_PCI_1_ACC_CNTL_5_BASE_LO,
1435 GT64260_PCI_1_ACC_CNTL_5_TOP },
1437 { GT64260_PCI_1_ACC_CNTL_6_BASE_HI,
1438 GT64260_PCI_1_ACC_CNTL_6_BASE_LO,
1439 GT64260_PCI_1_ACC_CNTL_6_TOP },
1441 { GT64260_PCI_1_ACC_CNTL_7_BASE_HI,
1442 GT64260_PCI_1_ACC_CNTL_7_BASE_LO,
1443 GT64260_PCI_1_ACC_CNTL_7_TOP },
1445 }; /* pci_acc_cntl_windows[][][] */
1448 if ((pci_bus < GT64260_PCI_BUSES) &&
1449 (window < GT64260_PCI_ACC_CNTL_WINDOWS)) {
1451 rc = gt64260_set_64bit_window(
1456 pci_acc_cntl_windows[pci_bus][window][0],
1457 pci_acc_cntl_windows[pci_bus][window][1],
1458 pci_acc_cntl_windows[pci_bus][window][2]);
1462 } /* gt64260_pci_acc_cntl_set_window() */
1465 gt64260_pci_snoop_set_window(u32 pci_bus,
1473 pci_snoop_windows[GT64260_PCI_BUSES][GT64260_PCI_SNOOP_WINDOWS][3] = {
1475 { GT64260_PCI_0_SNOOP_0_BASE_HI,
1476 GT64260_PCI_0_SNOOP_0_BASE_LO,
1477 GT64260_PCI_0_SNOOP_0_TOP },
1479 { GT64260_PCI_0_SNOOP_1_BASE_HI,
1480 GT64260_PCI_0_SNOOP_1_BASE_LO,
1481 GT64260_PCI_0_SNOOP_1_TOP },
1483 { GT64260_PCI_0_SNOOP_2_BASE_HI,
1484 GT64260_PCI_0_SNOOP_2_BASE_LO,
1485 GT64260_PCI_0_SNOOP_2_TOP },
1487 { GT64260_PCI_0_SNOOP_3_BASE_HI,
1488 GT64260_PCI_0_SNOOP_3_BASE_LO,
1489 GT64260_PCI_0_SNOOP_3_TOP },
1492 { GT64260_PCI_1_SNOOP_0_BASE_HI,
1493 GT64260_PCI_1_SNOOP_0_BASE_LO,
1494 GT64260_PCI_1_SNOOP_0_TOP },
1496 { GT64260_PCI_1_SNOOP_1_BASE_HI,
1497 GT64260_PCI_1_SNOOP_1_BASE_LO,
1498 GT64260_PCI_1_SNOOP_1_TOP },
1500 { GT64260_PCI_1_SNOOP_2_BASE_HI,
1501 GT64260_PCI_1_SNOOP_2_BASE_LO,
1502 GT64260_PCI_1_SNOOP_2_TOP },
1504 { GT64260_PCI_1_SNOOP_3_BASE_HI,
1505 GT64260_PCI_1_SNOOP_3_BASE_LO,
1506 GT64260_PCI_1_SNOOP_3_TOP },
1508 }; /* pci_snoop_windows[][][] */
1511 if ((pci_bus < GT64260_PCI_BUSES) &&
1512 (window < GT64260_PCI_SNOOP_WINDOWS)) {
1514 rc = gt64260_set_64bit_window(
1519 pci_snoop_windows[pci_bus][window][0],
1520 pci_snoop_windows[pci_bus][window][1],
1521 pci_snoop_windows[pci_bus][window][2]);
1525 } /* gt64260_pci_snoop_set_window() */
1528 *****************************************************************************
1530 * 64260's Register Base Address Routines
1532 *****************************************************************************
1536 * gt64260_remap_bridge_regs()
1538 * Move the bridge's register to the specified base address.
1539 * Assume that there are no other windows overlapping this area and that
1540 * all but the highest 3 nibbles are 0.
1543 gt64260_set_base(u32 new_base)
1549 val = gt_read(GT64260_INTERNAL_SPACE_DECODE);
1550 val = (new_base >> 20) | (val & 0xffff0000);
1551 gt_write(GT64260_INTERNAL_SPACE_DECODE, val);
1553 iounmap((void *)gt64260_base);
1554 gt64260_base = (u32)ioremap((new_base & 0xfff00000),
1555 GT64260_INTERNAL_SPACE_SIZE);
1557 do { /* Wait for bridge to move its regs */
1558 val = gt_read(GT64260_INTERNAL_SPACE_DECODE);
1559 } while ((val != 0xffffffff) && (limit-- > 0));
1566 } /* gt64260_remap_bridge_regs() */
1569 * gt64260_get_base()
1571 * Return the current virtual base address of the 64260's registers.
1574 gt64260_get_base(u32 *base)
1576 *base = gt64260_base;
1578 } /* gt64260_remap_bridge_regs() */
1581 *****************************************************************************
1583 * Exclude PCI config space access to bridge itself
1585 *****************************************************************************
1589 * gt64260_exclude_pci_device()
1591 * This routine causes the PCI subsystem to skip the PCI device in slot 0
1592 * (which is the 64260 itself) unless explicitly allowed.
1595 gt64260_pci_exclude_device(u8 bus, u8 devfn)
1597 struct pci_controller *hose;
1599 hose = pci_bus_to_hose(bus);
1601 /* Skip slot 0 and 1 on both hoses */
1602 if ((gt64260_pci_exclude_bridge == TRUE) &&
1603 (PCI_SLOT(devfn) == 0) &&
1604 (hose->first_busno == bus)) {
1606 return PCIBIOS_DEVICE_NOT_FOUND;
1609 return PCIBIOS_SUCCESSFUL;
1611 } /* gt64260_pci_exclude_device() */
1613 #if defined(CONFIG_SERIAL_TEXT_DEBUG)
1618 * Dump a character out the MPSC port for gt64260_mpsc_progress
1619 * this assumes the baud rate has already been set up and the
1620 * MPSC initialized by the bootloader or firmware.
1626 gt_write(GT64260_MPSC_0_CHR_1, c);
1628 gt_write(GT64260_MPSC_0_CHR_2, 0x200);
1635 puthex(unsigned long val){
1639 for (i = 7; i >= 0; i--) {
1640 gt_putc("0123456789ABCDEF"[(val>>28) & 0x0f]);
1650 gt64260_mpsc_progress(char *s, unsigned short hex){
1651 /* spit stuff out the 64260 mpsc */
1654 while ((c = *s++) != 0){
1656 if ( c == '\n' ) gt_putc('\r');
1664 #endif /* CONFIG_DEBUG_TEXT */