2 * arch/ppc/syslib/gt64260_pic.c
4 * Interrupt controller support for Galileo's GT64260.
6 * Author: Chris Zankel <chris@mvista.com>
7 * Modified by: Mark A. Greer <mgreer@mvista.com>
9 * Based on sources from Rabeeh Khoury / Galileo Technology
11 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
18 * This file contains the specific functions to support the GT64260
19 * interrupt controller.
21 * The GT64260 has two main interrupt registers (high and low) that
22 * summarizes the interrupts generated by the units of the GT64260.
23 * Each bit is assigned to an interrupt number, where the low register
24 * are assigned from IRQ0 to IRQ31 and the high cause register
26 * The GPP (General Purpose Port) interrupts are assigned from IRQ64 (GPP0)
28 * get_irq() returns the lowest interrupt number that is currently asserted.
31 * - This driver does not initialize the GPP when used as an interrupt
35 #include <linux/stddef.h>
36 #include <linux/init.h>
37 #include <linux/sched.h>
38 #include <linux/signal.h>
39 #include <linux/stddef.h>
40 #include <linux/delay.h>
41 #include <linux/irq.h>
44 #include <asm/system.h>
46 #include <asm/gt64260.h>
49 /* ========================== forward declaration ========================== */
51 static void gt64260_unmask_irq(unsigned int);
52 static void gt64260_mask_irq(unsigned int);
54 /* ========================== local declarations =========================== */
56 struct hw_interrupt_type gt64260_pic = {
57 " GT64260_PIC ", /* typename */
60 gt64260_unmask_irq, /* enable */
61 gt64260_mask_irq, /* disable */
62 gt64260_mask_irq, /* ack */
64 NULL /* set_affinity */
67 u32 gt64260_irq_base = 0; /* GT64260 handles the next 96 IRQs from here */
71 * This function initializes the interrupt controller. It assigns
72 * all interrupts from IRQ0 to IRQ95 to the gt64260 interrupt controller.
84 * We register all GPP inputs as interrupt source, but disable them.
88 gt64260_init_irq(void)
92 if ( ppc_md.progress ) ppc_md.progress("gt64260_init_irq: enter", 0x0);
94 ppc_cached_irq_mask[0] = 0;
95 ppc_cached_irq_mask[1] = 0x0f000000; /* Enable GPP intrs */
96 ppc_cached_irq_mask[2] = 0;
98 /* disable all interrupts and clear current interrupts */
99 gt_write(GT64260_GPP_INTR_MASK, ppc_cached_irq_mask[2]);
100 gt_write(GT64260_GPP_INTR_CAUSE,0);
101 gt_write(GT64260_IC_CPU_INTR_MASK_LO, ppc_cached_irq_mask[0]);
102 gt_write(GT64260_IC_CPU_INTR_MASK_HI, ppc_cached_irq_mask[1]);
104 /* use the gt64260 for all (possible) interrupt sources */
105 for( i = gt64260_irq_base; i < (gt64260_irq_base + 96); i++ ) {
106 irq_desc[i].handler = >64260_pic;
109 if ( ppc_md.progress ) ppc_md.progress("gt64260_init_irq: exit", 0x0);
115 * This function returns the lowest interrupt number of all interrupts that
116 * are currently asserted.
119 * struct pt_regs* not used
121 * Output Variable(s):
125 * int <interrupt number> or -2 (bogus interrupt)
129 gt64260_get_irq(struct pt_regs *regs)
134 irq = gt_read(GT64260_IC_MAIN_CAUSE_LO);
135 irq = __ilog2((irq & 0x3dfffffe) & ppc_cached_irq_mask[0]);
138 irq = gt_read(GT64260_IC_MAIN_CAUSE_HI);
139 irq = __ilog2((irq & 0x0f000db7) & ppc_cached_irq_mask[1]);
142 irq = -2; /* bogus interrupt, should never happen */
145 irq_gpp = gt_read(GT64260_GPP_INTR_CAUSE);
146 irq_gpp = __ilog2(irq_gpp &
147 ppc_cached_irq_mask[2]);
153 gt_write(GT64260_GPP_INTR_CAUSE, ~(1<<(irq-64)));
164 return( gt64260_irq_base + irq );
168 /* gt64260_unmask_irq()
170 * This function enables an interrupt.
173 * unsigned int interrupt number (IRQ0...IRQ95).
175 * Output Variable(s):
183 gt64260_unmask_irq(unsigned int irq)
185 irq -= gt64260_irq_base;
189 gt_write(GT64260_GPP_INTR_MASK,
190 ppc_cached_irq_mask[2] |= (1<<(irq-64)));
192 /* mask high interrupt register */
193 gt_write(GT64260_IC_CPU_INTR_MASK_HI,
194 ppc_cached_irq_mask[1] |= (1<<(irq-32)));
197 /* mask low interrupt register */
198 gt_write(GT64260_IC_CPU_INTR_MASK_LO,
199 ppc_cached_irq_mask[0] |= (1<<irq));
204 /* gt64260_mask_irq()
206 * This funktion disables the requested interrupt.
209 * unsigned int interrupt number (IRQ0...IRQ95).
211 * Output Variable(s):
219 gt64260_mask_irq(unsigned int irq)
221 irq -= gt64260_irq_base;
225 gt_write(GT64260_GPP_INTR_MASK,
226 ppc_cached_irq_mask[2] &= ~(1<<(irq-64)));
228 /* mask high interrupt register */
229 gt_write(GT64260_IC_CPU_INTR_MASK_HI,
230 ppc_cached_irq_mask[1] &= ~(1<<(irq-32)));
233 /* mask low interrupt register */
234 gt_write(GT64260_IC_CPU_INTR_MASK_LO,
235 ppc_cached_irq_mask[0] &= ~(1<<irq));
238 if (irq == 36) { /* Seems necessary for SDMA interrupts */