2 * arch/ppc/kernel/ibm440gx_common.c
4 * PPC440GX system library
6 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
7 * Copyright (c) 2003 Zultys Technologies
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
15 #include <linux/config.h>
16 #include <linux/kernel.h>
17 #include <asm/ibm44x.h>
19 #include <asm/processor.h>
20 #include <syslib/ibm440gx_common.h>
23 * Calculate 440GX clocks
25 static inline u32 __fix_zero(u32 v, u32 def){
29 void __init ibm440gx_get_clocks(struct ibm44x_clocks* p, unsigned int sys_clk,
32 u32 pllc = CPR_READ(DCRN_CPR_PLLC);
33 u32 plld = CPR_READ(DCRN_CPR_PLLD);
34 u32 uart0 = SDR_READ(DCRN_SDR_UART0);
35 u32 uart1 = SDR_READ(DCRN_SDR_UART1);
38 u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32);
39 u32 fwdva = __fix_zero((plld >> 16) & 0xf, 16);
40 u32 fwdvb = __fix_zero((plld >> 8) & 7, 8);
41 u32 lfbdv = __fix_zero(plld & 0x3f, 64);
42 u32 pradv0 = __fix_zero((CPR_READ(DCRN_CPR_PRIMAD) >> 24) & 7, 8);
43 u32 prbdv0 = __fix_zero((CPR_READ(DCRN_CPR_PRIMBD) >> 24) & 7, 8);
44 u32 opbdv0 = __fix_zero((CPR_READ(DCRN_CPR_OPBD) >> 24) & 3, 4);
45 u32 perdv0 = __fix_zero((CPR_READ(DCRN_CPR_PERD) >> 24) & 3, 4);
47 /* Input clocks for primary dividers */
50 if (pllc & 0x40000000){
54 switch ((pllc >> 24) & 7){
57 m = ((pllc & 0x20000000) ? fwdvb : fwdva) * lfbdv;
65 m = fwdvb * prbdv0 * opbdv0 * perdv0;
68 printk(KERN_EMERG "invalid PLL feedback source\n");
73 clk_a = p->vco / fwdva;
74 clk_b = p->vco / fwdvb;
78 /* Bypass system PLL */
80 clk_a = clk_b = sys_clk;
83 p->cpu = clk_a / pradv0;
84 p->plb = clk_b / prbdv0;
85 p->opb = p->plb / opbdv0;
86 p->ebc = p->opb / perdv0;
89 if (uart0 & 0x00800000)
92 p->uart0 = p->plb / __fix_zero(uart0 & 0xff, 256);
94 if (uart1 & 0x00800000)
97 p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256);
100 /* Enable L2 cache (call with IRQs disabled) */
101 void __init ibm440gx_l2c_enable(void){
104 asm volatile ("sync" ::: "memory");
107 mtdcr(DCRN_SRAM0_DPC, mfdcr(DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE);
108 mtdcr(DCRN_SRAM0_SB0CR, mfdcr(DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK);
109 mtdcr(DCRN_SRAM0_SB1CR, mfdcr(DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK);
110 mtdcr(DCRN_SRAM0_SB2CR, mfdcr(DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK);
111 mtdcr(DCRN_SRAM0_SB3CR, mfdcr(DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK);
113 /* Enable L2_MODE without ICU/DCU */
114 r = mfdcr(DCRN_L2C0_CFG) & ~(L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_SS_MASK);
115 r |= L2C_CFG_L2M | L2C_CFG_SS_256;
116 mtdcr(DCRN_L2C0_CFG, r);
118 mtdcr(DCRN_L2C0_ADDR, 0);
120 /* Hardware Clear Command */
121 mtdcr(DCRN_L2C0_CMD, L2C_CMD_HCC);
122 while (!(mfdcr(DCRN_L2C0_SR) & L2C_SR_CC)) ;
124 /* Clear Cache Parity and Tag Errors */
125 mtdcr(DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
127 /* Enable 64G snoop region starting at 0 */
128 r = mfdcr(DCRN_L2C0_SNP0) & ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
129 r |= L2C_SNP_SSR_32G | L2C_SNP_ESR;
130 mtdcr(DCRN_L2C0_SNP0, r);
132 r = mfdcr(DCRN_L2C0_SNP1) & ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
133 r |= 0x80000000 | L2C_SNP_SSR_32G | L2C_SNP_ESR;
134 mtdcr(DCRN_L2C0_SNP1, r);
136 asm volatile ("sync" ::: "memory");
138 /* Enable ICU/DCU ports */
139 r = mfdcr(DCRN_L2C0_CFG);
140 r &= ~(L2C_CFG_DCW_MASK | L2C_CFG_CPIM | L2C_CFG_TPIM | L2C_CFG_LIM
141 | L2C_CFG_PMUX_MASK | L2C_CFG_PMIM | L2C_CFG_TPEI | L2C_CFG_CPEI
142 | L2C_CFG_NAM | L2C_CFG_NBRM);
143 r |= L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_TPC | L2C_CFG_CPC | L2C_CFG_FRAN
145 mtdcr(DCRN_L2C0_CFG, r);
147 asm volatile ("sync; isync" ::: "memory");
150 /* Disable L2 cache (call with IRQs disabled) */
151 void __init ibm440gx_l2c_disable(void){
154 asm volatile ("sync" ::: "memory");
156 /* Disable L2C mode */
157 r = mfdcr(DCRN_L2C0_CFG) & ~(L2C_CFG_L2M | L2C_CFG_ICU | L2C_CFG_DCU);
158 mtdcr(DCRN_L2C0_CFG, r);
161 mtdcr(DCRN_SRAM0_DPC, mfdcr(DCRN_SRAM0_DPC) | SRAM_DPC_ENABLE);
162 mtdcr(DCRN_SRAM0_SB0CR,
163 SRAM_SBCR_BAS0 | SRAM_SBCR_BS_64KB | SRAM_SBCR_BU_RW);
164 mtdcr(DCRN_SRAM0_SB1CR,
165 SRAM_SBCR_BAS1 | SRAM_SBCR_BS_64KB | SRAM_SBCR_BU_RW);
166 mtdcr(DCRN_SRAM0_SB2CR,
167 SRAM_SBCR_BAS2 | SRAM_SBCR_BS_64KB | SRAM_SBCR_BU_RW);
168 mtdcr(DCRN_SRAM0_SB3CR,
169 SRAM_SBCR_BAS3 | SRAM_SBCR_BS_64KB | SRAM_SBCR_BU_RW);
171 asm volatile ("sync; isync" ::: "memory");
174 int __init ibm440gx_get_eth_grp(void)
176 return (SDR_READ(DCRN_SDR_PFC1) & DCRN_SDR_PFC1_EPS) >> DCRN_SDR_PFC1_EPS_SHIFT;
179 void __init ibm440gx_set_eth_grp(int group)
181 SDR_WRITE(DCRN_SDR_PFC1, (SDR_READ(DCRN_SDR_PFC1) & ~DCRN_SDR_PFC1_EPS) | (group << DCRN_SDR_PFC1_EPS_SHIFT));
184 void __init ibm440gx_tah_enable(void)
186 /* Enable TAH0 and TAH1 */
187 SDR_WRITE(DCRN_SDR_MFR,SDR_READ(DCRN_SDR_MFR) &
189 SDR_WRITE(DCRN_SDR_MFR,SDR_READ(DCRN_SDR_MFR) &
193 int ibm440gx_show_cpuinfo(struct seq_file *m){
195 u32 l2c_cfg = mfdcr(DCRN_L2C0_CFG);
197 if (l2c_cfg & L2C_CFG_L2M){
198 switch (l2c_cfg & (L2C_CFG_ICU | L2C_CFG_DCU)){
199 case L2C_CFG_ICU: s = "I-Cache only"; break;
200 case L2C_CFG_DCU: s = "D-Cache only"; break;
201 default: s = "I-Cache/D-Cache"; break;
207 seq_printf(m, "L2-Cache\t: %s (0x%08x 0x%08x)\n", s,
208 l2c_cfg, mfdcr(DCRN_L2C0_SR));