2 * arch/ppc/kernel/setup.c
4 * Copyright (C) 1995 Linus Torvalds
5 * Adapted from 'alpha' version by Gary Thomas
6 * Modified by Cort Dougan (cort@cs.nmt.edu)
7 * Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net)
8 * Further modified for generic 8xx by Dan.
12 * bootup setup stuff..
15 #include <linux/config.h>
16 #include <linux/errno.h>
17 #include <linux/sched.h>
18 #include <linux/kernel.h>
20 #include <linux/stddef.h>
21 #include <linux/unistd.h>
22 #include <linux/ptrace.h>
23 #include <linux/slab.h>
24 #include <linux/user.h>
25 #include <linux/a.out.h>
26 #include <linux/tty.h>
27 #include <linux/major.h>
28 #include <linux/interrupt.h>
29 #include <linux/reboot.h>
30 #include <linux/init.h>
31 #include <linux/initrd.h>
32 #include <linux/ioport.h>
33 #include <linux/bootmem.h>
34 #include <linux/seq_file.h>
35 #include <linux/root_dev.h>
39 #include <asm/residual.h>
41 #include <asm/pgtable.h>
42 #include <asm/mpc8xx.h>
43 #include <asm/8xx_immap.h>
44 #include <asm/machdep.h>
45 #include <asm/bootinfo.h>
49 #include "ppc8xx_pic.h"
51 static int m8xx_set_rtc_time(unsigned long time);
52 static unsigned long m8xx_get_rtc_time(void);
53 void m8xx_calibrate_decr(void);
55 unsigned char __res[sizeof(bd_t)];
57 extern void m8xx_ide_init(void);
59 extern unsigned long find_available_memory(void);
60 extern void m8xx_cpm_reset(uint);
61 extern void rpxfb_alloc_pages(void);
68 cpm_page = (int) alloc_bootmem_pages(PAGE_SIZE);
70 /* Reset the Communication Processor Module.
72 m8xx_cpm_reset(cpm_page);
79 ROOT_DEV = Root_HDA1; /* hda1 */
82 #ifdef CONFIG_BLK_DEV_INITRD
84 ROOT_DEV = Root_FD0; /* floppy */
89 #if 0 /* XXX this may need to be updated for the new bootmem stuff,
90 or possibly just deleted (see set_phys_avail() in init.c).
92 /* initrd_start and size are setup by boot/head.S and kernel/head.S */
95 if (initrd_end > *memory_end_p)
97 printk("initrd extends beyond end of memory "
98 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
99 initrd_end,*memory_end_p);
113 machine_restart(NULL);
119 /* A place holder for time base interrupts, if they are ever enabled. */
120 void timebase_interrupt(int irq, void * dev, struct pt_regs * regs)
122 printk ("timebase_interrupt()\n");
125 /* The decrementer counts at the system (internal) clock frequency divided by
126 * sixteen, or external oscillator divided by four. We force the processor
127 * to use system clock divided by sixteen.
129 void __init m8xx_calibrate_decr(void)
131 bd_t *binfo = (bd_t *)__res;
132 int freq, fp, divisor;
134 /* Unlock the SCCR. */
135 ((volatile immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk = ~KAPWR_KEY;
136 ((volatile immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk = KAPWR_KEY;
138 /* Force all 8xx processors to use divide by 16 processor clock. */
139 ((volatile immap_t *)IMAP_ADDR)->im_clkrst.car_sccr |= 0x02000000;
141 /* Processor frequency is MHz.
142 * The value 'fp' is the number of decrementer ticks per second.
144 fp = binfo->bi_intfreq / 16;
145 freq = fp*60; /* try to make freq/1e6 an integer */
147 printk("Decrementer Frequency = %d/%d\n", freq, divisor);
148 tb_ticks_per_jiffy = freq / HZ / divisor;
149 tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
151 /* Perform some more timer/timebase initialization. This used
152 * to be done elsewhere, but other changes caused it to get
153 * called more than once....that is a bad thing.
155 * First, unlock all of the registers we are going to modify.
156 * To protect them from corruption during power down, registers
157 * that are maintained by keep alive power are "locked". To
158 * modify these registers we have to write the key value to
159 * the key location associated with the register.
160 * Some boards power up with these unlocked, while others
161 * are locked. Writing anything (including the unlock code?)
162 * to the unlocked registers will lock them again. So, here
163 * we guarantee the registers are locked, then we unlock them
166 ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk = ~KAPWR_KEY;
167 ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck = ~KAPWR_KEY;
168 ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk = ~KAPWR_KEY;
169 ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk = KAPWR_KEY;
170 ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck = KAPWR_KEY;
171 ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk = KAPWR_KEY;
173 /* Disable the RTC one second and alarm interrupts. */
174 ((volatile immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc &=
175 ~(RTCSC_SIE | RTCSC_ALE);
177 ((volatile immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc |=
178 (RTCSC_RTF | RTCSC_RTE);
180 /* Enabling the decrementer also enables the timebase interrupts
181 * (or from the other point of view, to get decrementer interrupts
182 * we have to enable the timebase). The decrementer interrupt
183 * is wired into the vector table, nothing to do here for that.
185 ((volatile immap_t *)IMAP_ADDR)->im_sit.sit_tbscr =
186 ((mk_int_int_mask(DEC_INTERRUPT) << 8) |
187 (TBSCR_TBF | TBSCR_TBE));
189 if (request_8xxirq(DEC_INTERRUPT, timebase_interrupt, 0, "tbint", NULL) != 0)
190 panic("Could not allocate timer IRQ!");
193 /* The RTC on the MPC8xx is an internal register.
194 * We want to protect this during power down, so we need to unlock,
195 * modify, and re-lock.
198 m8xx_set_rtc_time(unsigned long time)
200 ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck = KAPWR_KEY;
201 ((volatile immap_t *)IMAP_ADDR)->im_sit.sit_rtc = time;
202 ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck = ~KAPWR_KEY;
207 m8xx_get_rtc_time(void)
209 /* Get time from the RTC. */
210 return((unsigned long)(((immap_t *)IMAP_ADDR)->im_sit.sit_rtc));
214 m8xx_restart(char *cmd)
216 __volatile__ unsigned char dummy;
219 ((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr |= 0x00000080;
221 /* Clear the ME bit in MSR to cause checkstop on machine check
223 mtmsr(mfmsr() & ~0x1000);
225 dummy = ((immap_t *)IMAP_ADDR)->im_clkrst.res[0];
226 printk("Restart failed\n");
244 m8xx_show_percpuinfo(struct seq_file *m, int i)
250 seq_printf(m, "clock\t\t: %ldMHz\n"
251 "bus clock\t: %ldMHz\n",
252 bp->bi_intfreq / 1000000,
253 bp->bi_busfreq / 1000000);
258 /* Initialize the internal interrupt controller. The number of
259 * interrupts supported can vary with the processor type, and the
260 * 82xx family can have up to 64.
261 * External interrupts can be either edge or level triggered, and
262 * need to be initialized by the appropriate driver.
268 void cpm_interrupt_init(void);
270 for ( i = 0 ; i < NR_SIU_INTS ; i++ )
271 irq_desc[i].handler = &ppc8xx_pic;
273 /* We could probably incorporate the CPM into the multilevel
274 * interrupt structure.
276 cpm_interrupt_init();
277 unmask_irq(CPM_INTERRUPT);
279 #if defined(CONFIG_PCI)
280 for ( i = NR_SIU_INTS ; i < (NR_SIU_INTS + NR_8259_INTS) ; i++ )
281 irq_desc[i].handler = &i8259_pic;
282 i8259_pic.irq_offset = NR_SIU_INTS;
284 request_8xxirq(ISA_BRIDGE_INT, mbx_i8259_action, 0, "8259 cascade", NULL);
285 enable_irq(ISA_BRIDGE_INT);
289 /* -------------------------------------------------------------------- */
292 * This is a big hack right now, but it may turn into something real
295 * For the 8xx boards (at this time anyway), there is nothing to initialize
296 * associated the PROM. Rather than include all of the prom.c
297 * functions in the image just to get prom_init, all we really need right
298 * now is the initialization of the physical memory region.
300 static unsigned long __init
301 m8xx_find_end_of_memory(void)
304 extern unsigned char __res[];
306 binfo = (bd_t *)__res;
308 return binfo->bi_memsize;
312 * Now map in some of the I/O space that is generically needed
313 * or shared with multiple devices.
314 * All of this fits into the same 4Mbyte region, so it only
315 * requires one page table page. (or at least it used to -- paulus)
320 io_block_mapping(IMAP_ADDR, IMAP_ADDR, IMAP_SIZE, _PAGE_IO);
322 io_block_mapping(NVRAM_ADDR, NVRAM_ADDR, NVRAM_SIZE, _PAGE_IO);
323 io_block_mapping(MBX_CSR_ADDR, MBX_CSR_ADDR, MBX_CSR_SIZE, _PAGE_IO);
324 io_block_mapping(PCI_CSR_ADDR, PCI_CSR_ADDR, PCI_CSR_SIZE, _PAGE_IO);
326 /* Map some of the PCI/ISA I/O space to get the IDE interface.
328 io_block_mapping(PCI_ISA_IO_ADDR, PCI_ISA_IO_ADDR, 0x4000, _PAGE_IO);
329 io_block_mapping(PCI_IDE_ADDR, PCI_IDE_ADDR, 0x4000, _PAGE_IO);
331 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
332 io_block_mapping(RPX_CSR_ADDR, RPX_CSR_ADDR, RPX_CSR_SIZE, _PAGE_IO);
333 #if !defined(CONFIG_PCI)
334 io_block_mapping(_IO_BASE,_IO_BASE,_IO_BASE_SIZE, _PAGE_IO);
337 #ifdef CONFIG_HTDMSOUND
338 io_block_mapping(HIOX_CSR_ADDR, HIOX_CSR_ADDR, HIOX_CSR_SIZE, _PAGE_IO);
341 io_block_mapping(BCSR_ADDR, BCSR_ADDR, BCSR_SIZE, _PAGE_IO);
344 io_block_mapping(PCI_CSR_ADDR, PCI_CSR_ADDR, PCI_CSR_SIZE, _PAGE_IO);
349 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
350 unsigned long r6, unsigned long r7)
352 parse_bootinfo(find_bootinfo());
355 memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
358 m8xx_setup_pci_ptrs();
361 #ifdef CONFIG_BLK_DEV_INITRD
362 /* take care of initrd if we have one */
365 initrd_start = r4 + KERNELBASE;
366 initrd_end = r5 + KERNELBASE;
368 #endif /* CONFIG_BLK_DEV_INITRD */
369 /* take care of cmd line */
372 *(char *)(r7+KERNELBASE) = 0;
373 strcpy(cmd_line, (char *)(r6+KERNELBASE));
376 ppc_md.setup_arch = m8xx_setup_arch;
377 ppc_md.show_percpuinfo = m8xx_show_percpuinfo;
378 ppc_md.irq_canonicalize = NULL;
379 ppc_md.init_IRQ = m8xx_init_IRQ;
380 ppc_md.get_irq = m8xx_get_irq;
383 ppc_md.restart = m8xx_restart;
384 ppc_md.power_off = m8xx_power_off;
385 ppc_md.halt = m8xx_halt;
387 ppc_md.time_init = NULL;
388 ppc_md.set_rtc_time = m8xx_set_rtc_time;
389 ppc_md.get_rtc_time = m8xx_get_rtc_time;
390 ppc_md.calibrate_decr = m8xx_calibrate_decr;
392 ppc_md.find_end_of_memory = m8xx_find_end_of_memory;
393 ppc_md.setup_io_mappings = m8xx_map_io;
395 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)