2 * arch/ppc/syslib/mpc10x_common.c
4 * Common routines for the Motorola SPS MPC106, MPC107 and MPC8240 Host bridge,
7 * Author: Mark A. Greer
10 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
17 * *** WARNING - A BAT MUST be set to access the PCI config addr/data regs ***
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
23 #include <linux/slab.h>
25 #include <asm/byteorder.h>
28 #include <asm/uaccess.h>
29 #include <asm/machdep.h>
30 #include <asm/pci-bridge.h>
31 #include <asm/open_pic.h>
32 #include <asm/mpc10x.h>
35 /* The OCP structure is fixed by code below, before OCP initialises.
36 paddr depends on where the board places the EUMB.
37 - fixed in mpc10x_bridge_init().
38 irq depends on two things:
39 > does the board use the EPIC at all? (PCORE does not).
40 > is the EPIC in serial or parallel mode?
41 - fixed in mpc10x_set_openpic().
44 #ifdef CONFIG_MPC10X_OPENPIC
45 #ifdef CONFIG_EPIC_SERIAL_MODE
46 #define EPIC_IRQ_BASE (epic_serial_mode ? 16 : 5)
48 #define EPIC_IRQ_BASE 5
50 #define MPC10X_I2C_IRQ (EPIC_IRQ_BASE + NUM_8259_INTERRUPTS)
51 #define MPC10X_DMA0_IRQ (EPIC_IRQ_BASE + 1 + NUM_8259_INTERRUPTS)
52 #define MPC10X_DMA1_IRQ (EPIC_IRQ_BASE + 2 + NUM_8259_INTERRUPTS)
54 #define MPC10X_I2C_IRQ OCP_IRQ_NA
55 #define MPC10X_DMA0_IRQ OCP_IRQ_NA
56 #define MPC10X_DMA1_IRQ OCP_IRQ_NA
60 struct ocp_def core_ocp[] = {
61 { .vendor = OCP_VENDOR_INVALID
65 static struct ocp_fs_i2c_data mpc10x_i2c_data = {
68 static struct ocp_def mpc10x_i2c_ocp = {
69 .vendor = OCP_VENDOR_MOTOROLA,
70 .function = OCP_FUNC_IIC,
72 .additions = &mpc10x_i2c_data
75 static struct ocp_def mpc10x_dma_ocp[2] = {
76 { .vendor = OCP_VENDOR_MOTOROLA,
77 .function = OCP_FUNC_DMA,
79 { .vendor = OCP_VENDOR_MOTOROLA,
80 .function = OCP_FUNC_DMA,
84 /* Set resources to match bridge memory map */
86 mpc10x_bridge_set_resources(int map, struct pci_controller *hose)
90 case MPC10X_MEM_MAP_A:
91 pci_init_resource(&hose->io_resource,
97 pci_init_resource (&hose->mem_resources[0],
103 case MPC10X_MEM_MAP_B:
104 pci_init_resource(&hose->io_resource,
110 pci_init_resource (&hose->mem_resources[0],
117 printk("mpc10x_bridge_set_resources: "
118 "Invalid map specified\n");
120 ppc_md.progress("mpc10x:exit1", 0x100);
124 * Do some initialization and put the EUMB registers at the specified address
125 * (also map the EPIC registers into virtual space--OpenPIC_Addr will be set).
127 * The EPIC is not on the 106, only the 8240 and 107.
130 mpc10x_bridge_init(struct pci_controller *hose,
135 int host_bridge, picr1, picr1_bit;
136 ulong pci_config_addr, pci_config_data;
139 if (ppc_md.progress) ppc_md.progress("mpc10x:enter", 0x100);
141 /* Set up for current map so we can get at config regs */
142 switch (current_map) {
143 case MPC10X_MEM_MAP_A:
144 setup_indirect_pci(hose,
145 MPC10X_MAPA_CNFG_ADDR,
146 MPC10X_MAPA_CNFG_DATA);
148 case MPC10X_MEM_MAP_B:
149 setup_indirect_pci(hose,
150 MPC10X_MAPB_CNFG_ADDR,
151 MPC10X_MAPB_CNFG_DATA);
154 printk("mpc10x_bridge_init: %s\n",
155 "Invalid current map specified");
157 ppc_md.progress("mpc10x:exit1", 0x100);
161 /* Make sure it's a supported bridge */
162 early_read_config_dword(hose,
168 switch (host_bridge) {
169 case MPC10X_BRIDGE_106:
170 case MPC10X_BRIDGE_8240:
171 case MPC10X_BRIDGE_107:
172 case MPC10X_BRIDGE_8245:
176 ppc_md.progress("mpc10x:exit2", 0x100);
181 case MPC10X_MEM_MAP_A:
182 MPC10X_SETUP_HOSE(hose, A);
183 pci_config_addr = MPC10X_MAPA_CNFG_ADDR;
184 pci_config_data = MPC10X_MAPA_CNFG_DATA;
185 picr1_bit = MPC10X_CFG_PICR1_ADDR_MAP_A;
187 case MPC10X_MEM_MAP_B:
188 MPC10X_SETUP_HOSE(hose, B);
189 pci_config_addr = MPC10X_MAPB_CNFG_ADDR;
190 pci_config_data = MPC10X_MAPB_CNFG_DATA;
191 picr1_bit = MPC10X_CFG_PICR1_ADDR_MAP_B;
194 printk("mpc10x_bridge_init: %s\n",
195 "Invalid new map specified");
197 ppc_md.progress("mpc10x:exit3", 0x100);
201 /* Make bridge use the 'new_map', if not already usng it */
202 if (current_map != new_map) {
203 early_read_config_dword(hose,
206 MPC10X_CFG_PICR1_REG,
209 picr1 = (picr1 & ~MPC10X_CFG_PICR1_ADDR_MAP_MASK) |
212 early_write_config_dword(hose,
215 MPC10X_CFG_PICR1_REG,
218 asm volatile("sync");
220 /* Undo old mappings & map in new cfg data/addr regs */
221 iounmap((void *)hose->cfg_addr);
222 iounmap((void *)hose->cfg_data);
224 setup_indirect_pci(hose,
229 /* Setup resources to match map */
230 mpc10x_bridge_set_resources(new_map, hose);
233 * Want processor accesses of 0xFDxxxxxx to be mapped
234 * to PCI memory space at 0x00000000. Do not want
235 * host bridge to respond to PCI memory accesses of
236 * 0xFDxxxxxx. Do not want host bridge to respond
237 * to PCI memory addresses 0xFD000000-0xFDFFFFFF;
238 * want processor accesses from 0x000A0000-0x000BFFFF
239 * to be forwarded to system memory.
241 * Only valid if not in agent mode and using MAP B.
243 if (new_map == MPC10X_MEM_MAP_B) {
244 early_read_config_byte(hose,
247 MPC10X_CFG_MAPB_OPTIONS_REG,
250 byte &= ~(MPC10X_CFG_MAPB_OPTIONS_PFAE |
251 MPC10X_CFG_MAPB_OPTIONS_PCICH |
252 MPC10X_CFG_MAPB_OPTIONS_PROCCH);
254 if (host_bridge != MPC10X_BRIDGE_106) {
255 byte |= MPC10X_CFG_MAPB_OPTIONS_CFAE;
258 early_write_config_byte(hose,
261 MPC10X_CFG_MAPB_OPTIONS_REG,
265 if (host_bridge != MPC10X_BRIDGE_106) {
266 early_read_config_byte(hose,
272 if (pir != MPC10X_CFG_PIR_HOST_BRIDGE) {
273 printk("Host bridge in Agent mode\n");
274 /* Read or Set LMBAR & PCSRBAR? */
277 /* Set base addr of the 8240/107 EUMB. */
278 early_write_config_dword(hose,
283 #ifdef CONFIG_MPC10X_OPENPIC
284 /* Map EPIC register part of EUMB into vitual memory - PCORE
285 uses an i8259 instead of EPIC. */
287 ioremap(phys_eumb_base + MPC10X_EUMB_EPIC_OFFSET,
288 MPC10X_EUMB_EPIC_SIZE);
290 mpc10x_i2c_ocp.paddr = phys_eumb_base + MPC10X_EUMB_I2C_OFFSET;
291 mpc10x_i2c_ocp.irq = MPC10X_I2C_IRQ;
292 ocp_add_one_device(&mpc10x_i2c_ocp);
293 mpc10x_dma_ocp[0].paddr = phys_eumb_base +
294 MPC10X_EUMB_DMA_OFFSET + 0x100;
295 mpc10x_dma_ocp[0].irq = MPC10X_DMA0_IRQ;
296 ocp_add_one_device(&mpc10x_dma_ocp[0]);
297 mpc10x_dma_ocp[1].paddr = phys_eumb_base +
298 MPC10X_EUMB_DMA_OFFSET + 0x200;
299 mpc10x_dma_ocp[1].irq = MPC10X_DMA1_IRQ;
300 ocp_add_one_device(&mpc10x_dma_ocp[1]);
303 #ifdef CONFIG_MPC10X_STORE_GATHERING
304 mpc10x_enable_store_gathering(hose);
306 mpc10x_disable_store_gathering(hose);
309 if (ppc_md.progress) ppc_md.progress("mpc10x:exit", 0x100);
314 * Need to make our own PCI config space access macros because
315 * mpc10x_get_mem_size() is called before the data structures are set up for
316 * the 'early_xxx' and 'indirect_xxx' routines to work.
319 #define MPC10X_CFG_read(val, addr, type, op) *val = op((type)(addr))
320 #define MPC10X_CFG_write(val, addr, type, op) op((type *)(addr), (val))
322 #define MPC10X_PCI_OP(rw, size, type, op, mask) \
324 mpc10x_##rw##_config_##size(uint *cfg_addr, uint *cfg_data, int devfn, int offset, type val) \
327 ((offset & 0xfc) << 24) | (devfn << 16) \
328 | (0 << 8) | 0x80); \
329 MPC10X_CFG_##rw(val, cfg_data + (offset & mask), type, op); \
333 MPC10X_PCI_OP(read, byte, u8 *, in_8, 3)
334 MPC10X_PCI_OP(read, dword, u32 *, in_le32, 0)
336 MPC10X_PCI_OP(write, byte, u8, out_8, 3)
337 MPC10X_PCI_OP(read, word, u16 *, in_le16, 2)
338 MPC10X_PCI_OP(write, word, u16, out_le16, 2)
339 MPC10X_PCI_OP(write, dword, u32, out_le32, 0)
343 * Read the memory controller registers to determine the amount of memory in
344 * the system. This assumes that the firmware has correctly set up the memory
345 * controller registers.
348 mpc10x_get_mem_size(uint mem_map)
350 uint *config_addr, *config_data, val;
351 ulong start, end, total, offset;
356 case MPC10X_MEM_MAP_A:
357 config_addr = (uint *)MPC10X_MAPA_CNFG_ADDR;
358 config_data = (uint *)MPC10X_MAPA_CNFG_DATA;
360 case MPC10X_MEM_MAP_B:
361 config_addr = (uint *)MPC10X_MAPB_CNFG_ADDR;
362 config_data = (uint *)MPC10X_MAPB_CNFG_DATA;
368 mpc10x_read_config_byte(config_addr,
371 MPC10X_MCTLR_MEM_BANK_ENABLES,
376 for (i=0; i<8; i++) {
377 if (bank_enables & (1 << i)) {
378 offset = MPC10X_MCTLR_MEM_START_1 + ((i > 3) ? 4 : 0);
379 mpc10x_read_config_dword(config_addr,
384 start = (val >> ((i & 3) << 3)) & 0xff;
386 offset = MPC10X_MCTLR_EXT_MEM_START_1 + ((i>3) ? 4 : 0);
387 mpc10x_read_config_dword(config_addr,
392 val = (val >> ((i & 3) << 3)) & 0x03;
393 start = (val << 28) | (start << 20);
395 offset = MPC10X_MCTLR_MEM_END_1 + ((i > 3) ? 4 : 0);
396 mpc10x_read_config_dword(config_addr,
401 end = (val >> ((i & 3) << 3)) & 0xff;
403 offset = MPC10X_MCTLR_EXT_MEM_END_1 + ((i > 3) ? 4 : 0);
404 mpc10x_read_config_dword(config_addr,
409 val = (val >> ((i & 3) << 3)) & 0x03;
410 end = (val << 28) | (end << 20) | 0xfffff;
412 total += (end - start + 1);
420 mpc10x_enable_store_gathering(struct pci_controller *hose)
424 early_read_config_dword(hose,
427 MPC10X_CFG_PICR1_REG,
430 picr1 |= MPC10X_CFG_PICR1_ST_GATH_EN;
432 early_write_config_dword(hose,
435 MPC10X_CFG_PICR1_REG,
442 mpc10x_disable_store_gathering(struct pci_controller *hose)
446 early_read_config_dword(hose,
449 MPC10X_CFG_PICR1_REG,
452 picr1 &= ~MPC10X_CFG_PICR1_ST_GATH_EN;
454 early_write_config_dword(hose,
457 MPC10X_CFG_PICR1_REG,
463 #ifdef CONFIG_MPC10X_OPENPIC
464 void __init mpc10x_set_openpic(void)
466 /* Map external IRQs */
467 openpic_set_sources(0, EPIC_IRQ_BASE, OpenPIC_Addr + 0x10200);
468 /* Skip reserved space and map i2c and DMA Ch[01] */
469 openpic_set_sources(EPIC_IRQ_BASE, 3, OpenPIC_Addr + 0x11020);
470 /* Skip reserved space and map Message Unit Interrupt (I2O) */
471 openpic_set_sources(EPIC_IRQ_BASE + 3, 1, OpenPIC_Addr + 0x110C0);
473 openpic_init(NUM_8259_INTERRUPTS);