2 * arch/ppc/syslib/mpc52xx_common.c
4 * Common code for the boards based on Freescale MPC52xx embedded CPU.
7 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
9 * Support for other bootloaders than UBoot by Dale Farnsworth
10 * <dfarnsworth@mvista.com>
12 * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
13 * Copyright (C) 2003 Montavista Software, Inc
15 * This file is licensed under the terms of the GNU General Public License
16 * version 2. This program is licensed "as is" without any warranty of any
17 * kind, whether express or implied.
20 #include <linux/config.h>
23 #include <asm/mpc52xx.h>
24 #include <asm/mpc52xx_psc.h>
26 #include <asm/ppcboot.h>
30 static int core_mult[] = { /* CPU Frequency multiplier, taken */
31 0, 0, 0, 10, 20, 20, 25, 45, /* from the datasheet used to compute */
32 30, 55, 40, 50, 0, 60, 35, 0, /* CPU frequency from XLB freq and */
33 30, 25, 65, 10, 70, 20, 75, 45, /* external jumper config */
34 0, 55, 40, 50, 80, 60, 35, 0
38 mpc52xx_restart(char *cmd)
40 struct mpc52xx_gpt* gpt0 = (struct mpc52xx_gpt*) MPC52xx_GPTx(0);
44 /* Turn on the watchdog and wait for it to expire. It effectively
47 out_be32(&gpt0->count, 0x000000ff);
48 out_be32(&gpt0->mode, 0x00009004);
50 printk(KERN_ERR "mpc52xx_restart: Unable to ioremap GPT0 registers, -> looping ...");
64 mpc52xx_power_off(void)
66 /* By default we don't have any way of shut down.
67 If a specific board wants to, it can set the power down
68 code to any hardware implementation dependent code */
76 /* Set BAT 2 to map the 0xf0000000 area */
77 /* This mapping is used during mpc52xx_progress,
78 * mpc52xx_find_end_of_memory, and UARTs/GPIO access for debug
81 mtspr(DBAT2U, 0xf0001ffe);
82 mtspr(DBAT2L, 0xf000002a);
89 /* Here we only map the MBAR */
91 MPC52xx_MBAR_VIRT, MPC52xx_MBAR, MPC52xx_MBAR_SIZE, _PAGE_IO);
95 #ifdef CONFIG_SERIAL_TEXT_DEBUG
96 #ifdef MPC52xx_PF_CONSOLE_PORT
97 #define MPC52xx_CONSOLE MPC52xx_PSCx(MPC52xx_PF_CONSOLE_PORT)
99 #error "mpc52xx PSC for console not selected"
103 mpc52xx_progress(char *s, unsigned short hex)
105 struct mpc52xx_psc *psc = (struct mpc52xx_psc *)MPC52xx_CONSOLE;
108 /* Don't we need to disable serial interrupts ? */
110 while ((c = *s++) != 0) {
112 while (!(in_be16(&psc->mpc52xx_psc_status) &
113 MPC52xx_PSC_SR_TXRDY)) ;
114 out_8(&psc->mpc52xx_psc_buffer_8, '\r');
116 while (!(in_be16(&psc->mpc52xx_psc_status) &
117 MPC52xx_PSC_SR_TXRDY)) ;
118 out_8(&psc->mpc52xx_psc_buffer_8, c);
122 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
126 mpc52xx_find_end_of_memory(void)
128 u32 ramsize = __res.bi_memsize;
131 * if bootloader passed a memsize, just use it
132 * else get size from sdram config registers
135 struct mpc52xx_mmap_ctl *mmap_ctl;
136 u32 sdram_config_0, sdram_config_1;
138 /* Temp BAT2 mapping active when this is called ! */
139 mmap_ctl = (struct mpc52xx_mmap_ctl*) MPC52xx_MMAP_CTL;
141 sdram_config_0 = in_be32(&mmap_ctl->sdram0);
142 sdram_config_1 = in_be32(&mmap_ctl->sdram1);
144 if ((sdram_config_0 & 0x1f) >= 0x13)
145 ramsize = 1 << ((sdram_config_0 & 0xf) + 17);
147 if (((sdram_config_1 & 0x1f) >= 0x13) &&
148 ((sdram_config_1 & 0xfff00000) == ramsize))
149 ramsize += 1 << ((sdram_config_1 & 0xf) + 17);
158 mpc52xx_calibrate_decr(void)
160 int current_time, previous_time;
161 int tbl_start, tbl_end;
162 unsigned int xlbfreq, cpufreq, ipbfreq, pcifreq, divisor;
164 xlbfreq = __res.bi_busfreq;
165 /* if bootloader didn't pass bus frequencies, calculate them */
167 /* Get RTC & Clock manager modules */
168 struct mpc52xx_rtc *rtc;
169 struct mpc52xx_cdm *cdm;
171 rtc = (struct mpc52xx_rtc*)
172 ioremap(MPC52xx_RTC, sizeof(struct mpc52xx_rtc));
173 cdm = (struct mpc52xx_cdm*)
174 ioremap(MPC52xx_CDM, sizeof(struct mpc52xx_cdm));
176 if ((rtc==NULL) || (cdm==NULL))
177 panic("Can't ioremap RTC/CDM while computing bus freq");
179 /* Count bus clock during 1/64 sec */
180 out_be32(&rtc->dividers, 0x8f1f0000); /* Set RTC 64x faster */
181 previous_time = in_be32(&rtc->time);
182 while ((current_time = in_be32(&rtc->time)) == previous_time) ;
183 tbl_start = get_tbl();
184 previous_time = current_time;
185 while ((current_time = in_be32(&rtc->time)) == previous_time) ;
187 out_be32(&rtc->dividers, 0xffff0000); /* Restore RTC */
189 /* Compute all frequency from that & CDM settings */
190 xlbfreq = (tbl_end - tbl_start) << 8;
191 cpufreq = (xlbfreq * core_mult[in_be32(&cdm->rstcfg)&0x1f])/10;
192 ipbfreq = (in_8(&cdm->ipb_clk_sel) & 1) ?
193 xlbfreq / 2 : xlbfreq;
194 switch (in_8(&cdm->pci_clk_sel) & 3) {
199 pcifreq = ipbfreq / 2;
202 pcifreq = xlbfreq / 4;
205 __res.bi_busfreq = xlbfreq;
206 __res.bi_intfreq = cpufreq;
207 __res.bi_ipbfreq = ipbfreq;
208 __res.bi_pcifreq = pcifreq;
210 /* Release mapping */
217 tb_ticks_per_jiffy = xlbfreq / HZ / divisor;
218 tb_to_us = mulhwu_scale_factor(xlbfreq / divisor, 1000000);
223 mpc52xx_add_board_devices(struct ocp_def board_ocp[]) {
224 while (board_ocp->vendor != OCP_VENDOR_INVALID)
225 if(ocp_add_one_device(board_ocp++))
226 printk("mpc5200-ocp: Failed to add board device !\n");