2 * arch/ppc/kernel/mv64360_pic.c
4 * Interrupt controller support for Marvell's MV64360.
6 * Author: Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Based on MV64360 PIC written by
8 * Chris Zankel <chris@mvista.com>
9 * Mark A. Greer <mgreer@mvista.com>
11 * Copyright 2004 MontaVista Software, Inc.
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
20 * This file contains the specific functions to support the MV64360
21 * interrupt controller.
23 * The MV64360 has two main interrupt registers (high and low) that
24 * summarizes the interrupts generated by the units of the MV64360.
25 * Each bit is assigned to an interrupt number, where the low register
26 * are assigned from IRQ0 to IRQ31 and the high cause register
28 * The GPP (General Purpose Pins) interrupts are assigned from IRQ64 (GPP0)
30 * get_irq() returns the lowest interrupt number that is currently asserted.
33 * - This driver does not initialize the GPP when used as an interrupt
37 #include <linux/stddef.h>
38 #include <linux/init.h>
39 #include <linux/sched.h>
40 #include <linux/signal.h>
41 #include <linux/stddef.h>
42 #include <linux/delay.h>
43 #include <linux/irq.h>
44 #include <linux/interrupt.h>
47 #include <asm/processor.h>
48 #include <asm/system.h>
51 #include <asm/mv64x60.h>
53 #ifdef CONFIG_IRQ_ALL_CPUS
54 #error "The mv64360 does not support yet distribution of IRQs on all CPUs"
56 /* ========================== forward declaration ========================== */
58 static void mv64360_unmask_irq(unsigned int);
59 static void mv64360_mask_irq(unsigned int);
60 static irqreturn_t mv64360_cpu_error_int_handler(int, void *, struct pt_regs *);
61 static irqreturn_t mv64360_sram_error_int_handler(int, void *, struct pt_regs *);
62 static irqreturn_t mv64360_pci_error_int_handler(int, void *, struct pt_regs *);
64 /* ========================== local declarations =========================== */
66 struct hw_interrupt_type mv64360_pic = {
67 .typename = " MV64360_PIC ", /* typename */
68 .enable = mv64360_unmask_irq, /* enable */
69 .disable = mv64360_mask_irq, /* disable */
70 .ack = mv64360_mask_irq, /* ack */
73 #define CPU_INTR_STR "MV64360 CPU interface error"
74 #define SRAM_INTR_STR "MV64360 internal sram error"
75 #define PCI0_INTR_STR "MV64360 PCI 0 error"
76 #define PCI1_INTR_STR "MV64360 PCI 1 error"
78 static mv64x60_handle_t base_bh;
80 u32 mv64360_irq_base = 0; /* MV64360 handles the next 96 IRQs from here */
84 * This function initializes the interrupt controller. It assigns
85 * all interrupts from IRQ0 to IRQ95 to the mv64360 interrupt controller.
97 * We register all GPP inputs as interrupt source, but disable them.
101 mv64360_init_irq(void)
107 ppc_md.progress("mv64360_init_irq: enter", 0x0);
109 if ( ppc_md.progress ) ppc_md.progress("mv64360_init_irq: enter", 0x0);
111 if ((def = ocp_get_one_device(OCP_VENDOR_MARVELL, OCP_FUNC_HB,
112 OCP_ANY_INDEX)) == NULL) {
116 base_bh.v_base = (unsigned long)ioremap(def->paddr, 0x1000);
118 ppc_cached_irq_mask[0] = 0;
119 ppc_cached_irq_mask[1] = 0x0f000000; /* Enable GPP intrs */
120 ppc_cached_irq_mask[2] = 0;
122 /* disable all interrupts and clear current interrupts */
123 mv64x60_write(&base_bh, MV64x60_GPP_INTR_CAUSE, 0);
124 mv64x60_write(&base_bh, MV64x60_GPP_INTR_MASK,
125 ppc_cached_irq_mask[2]);
126 mv64x60_write(&base_bh, MV64360_IC_CPU0_INTR_MASK_LO,
127 ppc_cached_irq_mask[0]);
128 mv64x60_write(&base_bh, MV64360_IC_CPU0_INTR_MASK_HI,
129 ppc_cached_irq_mask[1]);
131 /* use the mv64360 for all (possible) interrupt sources */
132 for (i = mv64360_irq_base; i < (mv64360_irq_base + 96); i++) {
133 /* All interrupts are level interrupts */
134 irq_desc[i].status |= IRQ_LEVEL;
135 irq_desc[i].handler = &mv64360_pic;
138 /* Register CPU interface error interrupt handler */
139 request_irq(MV64x60_IRQ_CPU_ERR, mv64360_cpu_error_int_handler,
140 SA_INTERRUPT, CPU_INTR_STR, 0);
141 mv64x60_write(&base_bh, MV64x60_CPU_ERR_MASK, 0x000000ff);
143 /* Register internal SRAM error interrupt handler */
144 request_irq(MV64360_IRQ_SRAM_PAR_ERR, mv64360_sram_error_int_handler,
145 SA_INTERRUPT, SRAM_INTR_STR, 0);
147 /* Register PCI 0 error interrupt handler */
148 request_irq(MV64360_IRQ_PCI0, mv64360_pci_error_int_handler,
149 SA_INTERRUPT, PCI0_INTR_STR, (void *) 0);
150 mv64x60_write(&base_bh, MV64x60_PCI0_ERR_MASK, 0x00a50c25);
152 /* Register PCI 1 error interrupt handler */
153 request_irq(MV64360_IRQ_PCI1, mv64360_pci_error_int_handler,
154 SA_INTERRUPT, PCI1_INTR_STR, (void *) 1);
155 mv64x60_write(&base_bh, MV64x60_PCI1_ERR_MASK, 0x00a50c25);
158 ppc_md.progress("mv64360_init_irq: exit", 0x0);
164 * This function returns the lowest interrupt number of all interrupts that
165 * are currently asserted.
168 * struct pt_regs* not used
170 * Output Variable(s):
174 * int <interrupt number> or -2 (bogus interrupt)
178 mv64360_get_irq(struct pt_regs *regs)
184 #define BIT28 (1<<28)
186 * Second CPU gets only doorbell (message) interrupts.
187 * The doorbell interrupt is BIT28 in the main interrupt low cause reg.
189 int cpu_nr = smp_processor_id();
191 irq = mv64x60_read(&base_bh, MV64360_IC_MAIN_CAUSE_LO);
198 irq = mv64x60_read(&base_bh, MV64360_IC_MAIN_CAUSE_LO);
199 irq = __ilog2((irq & 0x3dfffffe) & ppc_cached_irq_mask[0]);
201 irq = mv64x60_read(&base_bh, MV64360_IC_MAIN_CAUSE_HI);
202 irq = __ilog2((irq & 0x1f0003f7) & ppc_cached_irq_mask[1]);
204 irq = -2; /* bogus interrupt, should never happen */
206 if ((irq >= 24) && (irq < 28)) {
208 mv64x60_read(&base_bh,
209 MV64x60_GPP_INTR_CAUSE);
212 ppc_cached_irq_mask[2]);
218 mv64x60_write(&base_bh,
219 MV64x60_GPP_INTR_CAUSE,
231 return (mv64360_irq_base + irq);
235 /* mv64360_unmask_irq()
237 * This function enables an interrupt.
240 * unsigned int interrupt number (IRQ0...IRQ95).
242 * Output Variable(s):
250 mv64360_unmask_irq(unsigned int irq)
253 /* second CPU gets only doorbell interrupts */
254 if ((irq - mv64360_irq_base) == 28) {
255 mv64x60_set_bits(&base_bh, MV64360_IC_CPU1_INTR_MASK_LO, BIT28);
259 irq -= mv64360_irq_base;
263 mv64x60_write(&base_bh, MV64x60_GPP_INTR_MASK,
264 ppc_cached_irq_mask[2] |= (1 << (irq - 64)));
266 /* mask high interrupt register */
267 mv64x60_write(&base_bh, MV64360_IC_CPU0_INTR_MASK_HI,
268 ppc_cached_irq_mask[1] |= (1 << (irq - 32)));
271 /* mask low interrupt register */
272 mv64x60_write(&base_bh, MV64360_IC_CPU0_INTR_MASK_LO,
273 ppc_cached_irq_mask[0] |= (1 << irq));
278 /* mv64360_mask_irq()
280 * This function disables the requested interrupt.
283 * unsigned int interrupt number (IRQ0...IRQ95).
285 * Output Variable(s):
293 mv64360_mask_irq(unsigned int irq)
296 if ((irq - mv64360_irq_base) == 28) {
297 mv64x60_clr_bits(&base_bh, MV64360_IC_CPU1_INTR_MASK_LO, BIT28);
301 irq -= mv64360_irq_base;
305 mv64x60_write(&base_bh, MV64x60_GPP_INTR_MASK,
306 ppc_cached_irq_mask[2] &= ~(1 << (irq - 64)));
308 /* mask high interrupt register */
309 mv64x60_write(&base_bh, MV64360_IC_CPU0_INTR_MASK_HI,
310 ppc_cached_irq_mask[1] &= ~(1 << (irq - 32)));
313 /* mask low interrupt register */
314 mv64x60_write(&base_bh, MV64360_IC_CPU0_INTR_MASK_LO,
315 ppc_cached_irq_mask[0] &= ~(1 << irq));
321 mv64360_cpu_error_int_handler(int irq, void *dev_id, struct pt_regs *regs)
324 val = mv64x60_read(&base_bh, MV64x60_CPU_ERR_CAUSE);
326 "mv64360_cpu_error_int_handler: Error on CPU interface - Cause regiser 0x%08x\n",
328 printk(KERN_ERR "\tCPU error register dump:\n");
329 printk(KERN_ERR "\tAddress low 0x%08x\n",
330 mv64x60_read(&base_bh, MV64x60_CPU_ERR_ADDR_LO));
331 printk(KERN_ERR "\tAddress high 0x%08x\n",
332 mv64x60_read(&base_bh, MV64x60_CPU_ERR_ADDR_HI));
333 printk(KERN_ERR "\tData low 0x%08x\n",
334 mv64x60_read(&base_bh, MV64x60_CPU_ERR_DATA_LO));
335 printk(KERN_ERR "\tData high 0x%08x\n",
336 mv64x60_read(&base_bh, MV64x60_CPU_ERR_DATA_HI));
337 printk(KERN_ERR "\tParity 0x%08x\n",
338 mv64x60_read(&base_bh, MV64x60_CPU_ERR_PARITY));
339 mv64x60_write(&base_bh, MV64x60_CPU_ERR_CAUSE, 0);
344 mv64360_sram_error_int_handler(int irq, void *dev_id, struct pt_regs *regs)
347 "mv64360_sram_error_int_handler: Error in internal SRAM - Cause register 0x%08x\n",
348 mv64x60_read(&base_bh, MV64360_SRAM_ERR_CAUSE));
349 printk(KERN_ERR "\tSRAM error register dump:\n");
350 printk(KERN_ERR "\tAddress Low 0x%08x\n",
351 mv64x60_read(&base_bh, MV64360_SRAM_ERR_ADDR_LO));
352 printk(KERN_ERR "\tAddress High 0x%08x\n",
353 mv64x60_read(&base_bh, MV64360_SRAM_ERR_ADDR_HI));
354 printk(KERN_ERR "\tData Low 0x%08x\n",
355 mv64x60_read(&base_bh, MV64360_SRAM_ERR_DATA_LO));
356 printk(KERN_ERR "\tData High 0x%08x\n",
357 mv64x60_read(&base_bh, MV64360_SRAM_ERR_DATA_HI));
358 printk(KERN_ERR "\tParity 0x%08x\n",
359 mv64x60_read(&base_bh, MV64360_SRAM_ERR_PARITY));
360 mv64x60_write(&base_bh, MV64360_SRAM_ERR_CAUSE, 0);
365 mv64360_pci_error_int_handler(int irq, void *dev_id, struct pt_regs *regs)
368 unsigned int pci_bus = (unsigned int) dev_id;
369 if (pci_bus == 0) { /* Error on PCI 0 */
370 val = mv64x60_read(&base_bh, MV64x60_PCI0_ERR_CAUSE);
372 "mv64360_pci_error_int_handler: Error in PCI %d Interface\n",
374 printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus);
375 printk(KERN_ERR "\tCause register 0x%08x\n", val);
376 printk(KERN_ERR "\tAddress Low 0x%08x\n",
377 mv64x60_read(&base_bh, MV64x60_PCI0_ERR_ADDR_LO));
378 printk(KERN_ERR "\tAddress High 0x%08x\n",
379 mv64x60_read(&base_bh, MV64x60_PCI0_ERR_ADDR_HI));
380 printk(KERN_ERR "\tAttribute 0x%08x\n",
381 mv64x60_read(&base_bh, MV64x60_PCI0_ERR_DATA_LO));
382 printk(KERN_ERR "\tCommand 0x%08x\n",
383 mv64x60_read(&base_bh, MV64x60_PCI0_ERR_CMD));
384 mv64x60_write(&base_bh, MV64x60_PCI0_ERR_CAUSE, ~val);
386 if (pci_bus == 1) { /* Error on PCI 1 */
387 val = mv64x60_read(&base_bh, MV64x60_PCI1_ERR_CAUSE);
389 "mv64360_pci_error_int_handler: Error in PCI %d Interface\n",
391 printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus);
392 printk(KERN_ERR "\tCause register 0x%08x\n", val);
393 printk(KERN_ERR "\tAddress Low 0x%08x\n",
394 mv64x60_read(&base_bh, MV64x60_PCI1_ERR_ADDR_LO));
395 printk(KERN_ERR "\tAddress High 0x%08x\n",
396 mv64x60_read(&base_bh, MV64x60_PCI1_ERR_ADDR_HI));
397 printk(KERN_ERR "\tAttribute 0x%08x\n",
398 mv64x60_read(&base_bh, MV64x60_PCI1_ERR_DATA_LO));
399 printk(KERN_ERR "\tCommand 0x%08x\n",
400 mv64x60_read(&base_bh, MV64x60_PCI1_ERR_CMD));
401 mv64x60_write(&base_bh, MV64x60_PCI1_ERR_CAUSE, ~val);