2 * arch/ppc/syslib/mv64x60.c
4 * Common routines for the Marvell/Galileo Discovery line of host bridges
5 * (e.g, gt64260 and mv64360).
7 * Author: Mark A. Greer <mgreer@mvista.com>
8 * Rabeeh Khoury <rabeeh@galileo.co.il>
10 * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/pci.h>
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <linux/string.h>
22 #include <asm/byteorder.h>
25 #include <asm/uaccess.h>
26 #include <asm/machdep.h>
27 #include <asm/pci-bridge.h>
28 #include <asm/mv64x60.h>
29 #include <asm/delay.h>
36 #define DBG(x...) printk(x)
42 static u32 mv64x60_mask(u32 val, u32 num_bits);
43 static u32 mv64x60_shift_left(u32 val, u32 num_bits);
44 static u32 mv64x60_shift_right(u32 val, u32 num_bits);
45 static void mv64x60_early_init(mv64x60_handle_t *bh, mv64x60_setup_info_t *si);
46 static int mv64x60_get_type(mv64x60_handle_t *bh);
47 static int mv64x60_setup_for_chip(mv64x60_handle_t *bh);
48 static void mv64x60_get_mem_windows(mv64x60_handle_t *bh,
49 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
50 static u32 mv64x60_calc_mem_size(mv64x60_handle_t *bh,
51 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
52 static void mv64x60_config_cpu2mem_windows(mv64x60_handle_t *bh,
53 mv64x60_setup_info_t *si, u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
54 static void mv64x60_config_cpu2pci_windows(mv64x60_handle_t *bh,
55 mv64x60_setup_info_t *si);
56 static void mv64x60_set_cpu2pci_window(mv64x60_handle_t *bh,
57 mv64x60_pci_info_t *pi, u32 *win_tab, u32 *remap_tab);
58 static void mv64x60_config_pci2mem_windows(mv64x60_handle_t *bh,
59 mv64x60_setup_info_t *si, u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
60 static void mv64x60_alloc_hoses(mv64x60_handle_t *bh, mv64x60_setup_info_t *si);
61 static void mv64x60_init_hoses(mv64x60_handle_t *bh, mv64x60_setup_info_t *si);
62 static void mv64x60_init_resources(struct pci_controller *hose,
63 mv64x60_pci_info_t *pi, u32 io_base);
64 static void mv64x60_set_pci_params(struct pci_controller *hose,
65 mv64x60_pci_info_t *pi);
66 static void mv64x60_enumerate_buses(mv64x60_handle_t *bh,
67 mv64x60_setup_info_t *si);
68 static int mv64x60_pci_exclude_device(u8 bus, u8 devfn);
69 static void mv64x60_fixup_ocp(struct ocp_device *, void *arg);
71 static u32 gt64260_translate_size(u32 base, u32 size, u32 num_bits);
72 static u32 gt64260_untranslate_size(u32 base, u32 size, u32 num_bits);
73 static void gt64260_set_pci2mem_window(struct pci_controller *hose,
74 u32 window, u32 base);
75 static u32 gt64260_is_enabled_32bit(mv64x60_handle_t *bh, u32 window);
76 static void gt64260_enable_window_32bit(mv64x60_handle_t *bh, u32 window);
77 static void gt64260_disable_window_32bit(mv64x60_handle_t *bh, u32 window);
78 static void gt64260_enable_window_64bit(mv64x60_handle_t *bh, u32 window);
79 static void gt64260_disable_window_64bit(mv64x60_handle_t *bh, u32 window);
80 static void gt64260_disable_all_windows(mv64x60_handle_t *bh,
81 mv64x60_setup_info_t *si);
82 static void gt64260a_chip_specific_init(mv64x60_handle_t *bh,
83 mv64x60_setup_info_t *si);
84 static void gt64260b_chip_specific_init(mv64x60_handle_t *bh,
85 mv64x60_setup_info_t *si);
87 static u32 mv64360_translate_size(u32 base_addr, u32 size, u32 num_bits);
88 static u32 mv64360_untranslate_size(u32 base_addr, u32 size, u32 num_bits);
89 static void mv64360_set_pci2mem_window(struct pci_controller *hose,
90 u32 window, u32 base);
91 static u32 mv64360_is_enabled_32bit(mv64x60_handle_t *bh, u32 window);
92 static void mv64360_enable_window_32bit(mv64x60_handle_t *bh, u32 window);
93 static void mv64360_disable_window_32bit(mv64x60_handle_t *bh, u32 window);
94 static void mv64360_enable_window_64bit(mv64x60_handle_t *bh, u32 window);
95 static void mv64360_disable_window_64bit(mv64x60_handle_t *bh, u32 window);
96 static void mv64360_disable_all_windows(mv64x60_handle_t *bh,
97 mv64x60_setup_info_t *si);
98 static void mv64360_chip_specific_init(mv64x60_handle_t *bh,
99 mv64x60_setup_info_t *si);
100 static void mv64460_chip_specific_init(mv64x60_handle_t *bh,
101 mv64x60_setup_info_t *si);
104 u8 mv64x60_pci_exclude_bridge = TRUE;
106 spinlock_t mv64x60_lock = SPIN_LOCK_UNLOCKED;
107 spinlock_t mv64x60_rmw_lock = SPIN_LOCK_UNLOCKED;
109 static mv64x60_32bit_window_t gt64260_32bit_windows[] __initdata = {
110 /* CPU->MEM Windows */
111 [MV64x60_CPU2MEM_0_WIN] = {
112 .base_reg = MV64x60_CPU2MEM_0_BASE,
113 .size_reg = MV64x60_CPU2MEM_0_SIZE,
116 .get_from_field = mv64x60_shift_left,
117 .map_to_field = mv64x60_shift_right,
119 [MV64x60_CPU2MEM_1_WIN] = {
120 .base_reg = MV64x60_CPU2MEM_1_BASE,
121 .size_reg = MV64x60_CPU2MEM_1_SIZE,
124 .get_from_field = mv64x60_shift_left,
125 .map_to_field = mv64x60_shift_right,
127 [MV64x60_CPU2MEM_2_WIN] = {
128 .base_reg = MV64x60_CPU2MEM_2_BASE,
129 .size_reg = MV64x60_CPU2MEM_2_SIZE,
132 .get_from_field = mv64x60_shift_left,
133 .map_to_field = mv64x60_shift_right,
135 [MV64x60_CPU2MEM_3_WIN] = {
136 .base_reg = MV64x60_CPU2MEM_3_BASE,
137 .size_reg = MV64x60_CPU2MEM_3_SIZE,
140 .get_from_field = mv64x60_shift_left,
141 .map_to_field = mv64x60_shift_right,
143 /* CPU->Device Windows */
144 [MV64x60_CPU2DEV_0_WIN] = {
145 .base_reg = MV64x60_CPU2DEV_0_BASE,
146 .size_reg = MV64x60_CPU2DEV_0_SIZE,
149 .get_from_field = mv64x60_shift_left,
150 .map_to_field = mv64x60_shift_right,
152 [MV64x60_CPU2DEV_1_WIN] = {
153 .base_reg = MV64x60_CPU2DEV_1_BASE,
154 .size_reg = MV64x60_CPU2DEV_1_SIZE,
157 .get_from_field = mv64x60_shift_left,
158 .map_to_field = mv64x60_shift_right,
160 [MV64x60_CPU2DEV_2_WIN] = {
161 .base_reg = MV64x60_CPU2DEV_2_BASE,
162 .size_reg = MV64x60_CPU2DEV_2_SIZE,
165 .get_from_field = mv64x60_shift_left,
166 .map_to_field = mv64x60_shift_right,
168 [MV64x60_CPU2DEV_3_WIN] = {
169 .base_reg = MV64x60_CPU2DEV_3_BASE,
170 .size_reg = MV64x60_CPU2DEV_3_SIZE,
173 .get_from_field = mv64x60_shift_left,
174 .map_to_field = mv64x60_shift_right,
176 /* CPU->Boot Window */
177 [MV64x60_CPU2BOOT_WIN] = {
178 .base_reg = MV64x60_CPU2BOOT_0_BASE,
179 .size_reg = MV64x60_CPU2BOOT_0_SIZE,
182 .get_from_field = mv64x60_shift_left,
183 .map_to_field = mv64x60_shift_right,
185 /* CPU->PCI 0 Windows */
186 [MV64x60_CPU2PCI0_IO_WIN] = {
187 .base_reg = MV64x60_CPU2PCI0_IO_BASE,
188 .size_reg = MV64x60_CPU2PCI0_IO_SIZE,
191 .get_from_field = mv64x60_shift_left,
192 .map_to_field = mv64x60_shift_right,
194 [MV64x60_CPU2PCI0_MEM_0_WIN] = {
195 .base_reg = MV64x60_CPU2PCI0_MEM_0_BASE,
196 .size_reg = MV64x60_CPU2PCI0_MEM_0_SIZE,
199 .get_from_field = mv64x60_shift_left,
200 .map_to_field = mv64x60_shift_right,
202 [MV64x60_CPU2PCI0_MEM_1_WIN] = {
203 .base_reg = MV64x60_CPU2PCI0_MEM_1_BASE,
204 .size_reg = MV64x60_CPU2PCI0_MEM_1_SIZE,
207 .get_from_field = mv64x60_shift_left,
208 .map_to_field = mv64x60_shift_right,
210 [MV64x60_CPU2PCI0_MEM_2_WIN] = {
211 .base_reg = MV64x60_CPU2PCI0_MEM_2_BASE,
212 .size_reg = MV64x60_CPU2PCI0_MEM_2_SIZE,
215 .get_from_field = mv64x60_shift_left,
216 .map_to_field = mv64x60_shift_right,
218 [MV64x60_CPU2PCI0_MEM_3_WIN] = {
219 .base_reg = MV64x60_CPU2PCI0_MEM_3_BASE,
220 .size_reg = MV64x60_CPU2PCI0_MEM_3_SIZE,
223 .get_from_field = mv64x60_shift_left,
224 .map_to_field = mv64x60_shift_right,
226 /* CPU->PCI 1 Windows */
227 [MV64x60_CPU2PCI1_IO_WIN] = {
228 .base_reg = MV64x60_CPU2PCI1_IO_BASE,
229 .size_reg = MV64x60_CPU2PCI1_IO_SIZE,
232 .get_from_field = mv64x60_shift_left,
233 .map_to_field = mv64x60_shift_right,
235 [MV64x60_CPU2PCI1_MEM_0_WIN] = {
236 .base_reg = MV64x60_CPU2PCI1_MEM_0_BASE,
237 .size_reg = MV64x60_CPU2PCI1_MEM_0_SIZE,
240 .get_from_field = mv64x60_shift_left,
241 .map_to_field = mv64x60_shift_right,
243 [MV64x60_CPU2PCI1_MEM_1_WIN] = {
244 .base_reg = MV64x60_CPU2PCI1_MEM_1_BASE,
245 .size_reg = MV64x60_CPU2PCI1_MEM_1_SIZE,
248 .get_from_field = mv64x60_shift_left,
249 .map_to_field = mv64x60_shift_right,
251 [MV64x60_CPU2PCI1_MEM_2_WIN] = {
252 .base_reg = MV64x60_CPU2PCI1_MEM_2_BASE,
253 .size_reg = MV64x60_CPU2PCI1_MEM_2_SIZE,
256 .get_from_field = mv64x60_shift_left,
257 .map_to_field = mv64x60_shift_right,
259 [MV64x60_CPU2PCI1_MEM_3_WIN] = {
260 .base_reg = MV64x60_CPU2PCI1_MEM_3_BASE,
261 .size_reg = MV64x60_CPU2PCI1_MEM_3_SIZE,
264 .get_from_field = mv64x60_shift_left,
265 .map_to_field = mv64x60_shift_right,
267 /* CPU->SRAM Window (64260 has no integrated SRAM) */
268 /* CPU->PCI 0 Remap I/O Window */
269 [MV64x60_CPU2PCI0_IO_REMAP_WIN] = {
270 .base_reg = MV64x60_CPU2PCI0_IO_REMAP,
274 .get_from_field = mv64x60_shift_left,
275 .map_to_field = mv64x60_shift_right,
277 /* CPU->PCI 1 Remap I/O Window */
278 [MV64x60_CPU2PCI1_IO_REMAP_WIN] = {
279 .base_reg = MV64x60_CPU2PCI1_IO_REMAP,
283 .get_from_field = mv64x60_shift_left,
284 .map_to_field = mv64x60_shift_right,
286 /* CPU Memory Protection Windows */
287 [MV64x60_CPU_PROT_0_WIN] = {
288 .base_reg = MV64x60_CPU_PROT_BASE_0,
289 .size_reg = MV64x60_CPU_PROT_SIZE_0,
292 .get_from_field = mv64x60_shift_left,
293 .map_to_field = mv64x60_shift_right,
295 [MV64x60_CPU_PROT_1_WIN] = {
296 .base_reg = MV64x60_CPU_PROT_BASE_1,
297 .size_reg = MV64x60_CPU_PROT_SIZE_1,
300 .get_from_field = mv64x60_shift_left,
301 .map_to_field = mv64x60_shift_right,
303 [MV64x60_CPU_PROT_2_WIN] = {
304 .base_reg = MV64x60_CPU_PROT_BASE_2,
305 .size_reg = MV64x60_CPU_PROT_SIZE_2,
308 .get_from_field = mv64x60_shift_left,
309 .map_to_field = mv64x60_shift_right,
311 [MV64x60_CPU_PROT_3_WIN] = {
312 .base_reg = MV64x60_CPU_PROT_BASE_3,
313 .size_reg = MV64x60_CPU_PROT_SIZE_3,
316 .get_from_field = mv64x60_shift_left,
317 .map_to_field = mv64x60_shift_right,
319 /* CPU Snoop Windows */
320 [MV64x60_CPU_SNOOP_0_WIN] = {
321 .base_reg = GT64260_CPU_SNOOP_BASE_0,
322 .size_reg = GT64260_CPU_SNOOP_SIZE_0,
325 .get_from_field = mv64x60_shift_left,
326 .map_to_field = mv64x60_shift_right,
328 [MV64x60_CPU_SNOOP_1_WIN] = {
329 .base_reg = GT64260_CPU_SNOOP_BASE_1,
330 .size_reg = GT64260_CPU_SNOOP_SIZE_1,
333 .get_from_field = mv64x60_shift_left,
334 .map_to_field = mv64x60_shift_right,
336 [MV64x60_CPU_SNOOP_2_WIN] = {
337 .base_reg = GT64260_CPU_SNOOP_BASE_2,
338 .size_reg = GT64260_CPU_SNOOP_SIZE_2,
341 .get_from_field = mv64x60_shift_left,
342 .map_to_field = mv64x60_shift_right,
344 [MV64x60_CPU_SNOOP_3_WIN] = {
345 .base_reg = GT64260_CPU_SNOOP_BASE_3,
346 .size_reg = GT64260_CPU_SNOOP_SIZE_3,
349 .get_from_field = mv64x60_shift_left,
350 .map_to_field = mv64x60_shift_right,
352 /* PCI 0->System Memory Remap Windows */
353 [MV64x60_PCI02MEM_REMAP_0_WIN] = {
354 .base_reg = MV64x60_PCI0_SLAVE_MEM_0_REMAP,
358 .get_from_field = mv64x60_mask,
359 .map_to_field = mv64x60_mask,
361 [MV64x60_PCI02MEM_REMAP_1_WIN] = {
362 .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP,
366 .get_from_field = mv64x60_mask,
367 .map_to_field = mv64x60_mask,
369 [MV64x60_PCI02MEM_REMAP_2_WIN] = {
370 .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP,
374 .get_from_field = mv64x60_mask,
375 .map_to_field = mv64x60_mask,
377 [MV64x60_PCI02MEM_REMAP_3_WIN] = {
378 .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP,
382 .get_from_field = mv64x60_mask,
383 .map_to_field = mv64x60_mask,
385 /* PCI 1->System Memory Remap Windows */
386 [MV64x60_PCI12MEM_REMAP_0_WIN] = {
387 .base_reg = MV64x60_PCI1_SLAVE_MEM_0_REMAP,
391 .get_from_field = mv64x60_mask,
392 .map_to_field = mv64x60_mask,
394 [MV64x60_PCI12MEM_REMAP_1_WIN] = {
395 .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP,
399 .get_from_field = mv64x60_mask,
400 .map_to_field = mv64x60_mask,
402 [MV64x60_PCI12MEM_REMAP_2_WIN] = {
403 .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP,
407 .get_from_field = mv64x60_mask,
408 .map_to_field = mv64x60_mask,
410 [MV64x60_PCI12MEM_REMAP_3_WIN] = {
411 .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP,
415 .get_from_field = mv64x60_mask,
416 .map_to_field = mv64x60_mask,
420 static mv64x60_64bit_window_t gt64260_64bit_windows[] __initdata = {
421 /* CPU->PCI 0 MEM Remap Windows */
422 [MV64x60_CPU2PCI0_MEM_0_REMAP_WIN] = {
423 .base_hi_reg = MV64x60_CPU2PCI0_MEM_0_REMAP_HI,
424 .base_lo_reg = MV64x60_CPU2PCI0_MEM_0_REMAP_LO,
428 .get_from_field = mv64x60_shift_left,
429 .map_to_field = mv64x60_shift_right,
431 [MV64x60_CPU2PCI0_MEM_1_REMAP_WIN] = {
432 .base_hi_reg = MV64x60_CPU2PCI0_MEM_1_REMAP_HI,
433 .base_lo_reg = MV64x60_CPU2PCI0_MEM_1_REMAP_LO,
437 .get_from_field = mv64x60_shift_left,
438 .map_to_field = mv64x60_shift_right,
440 [MV64x60_CPU2PCI0_MEM_2_REMAP_WIN] = {
441 .base_hi_reg = MV64x60_CPU2PCI0_MEM_2_REMAP_HI,
442 .base_lo_reg = MV64x60_CPU2PCI0_MEM_2_REMAP_LO,
446 .get_from_field = mv64x60_shift_left,
447 .map_to_field = mv64x60_shift_right,
449 [MV64x60_CPU2PCI0_MEM_3_REMAP_WIN] = {
450 .base_hi_reg = MV64x60_CPU2PCI0_MEM_3_REMAP_HI,
451 .base_lo_reg = MV64x60_CPU2PCI0_MEM_3_REMAP_LO,
455 .get_from_field = mv64x60_shift_left,
456 .map_to_field = mv64x60_shift_right,
458 /* CPU->PCI 1 MEM Remap Windows */
459 [MV64x60_CPU2PCI1_MEM_0_REMAP_WIN] = {
460 .base_hi_reg = MV64x60_CPU2PCI1_MEM_0_REMAP_HI,
461 .base_lo_reg = MV64x60_CPU2PCI1_MEM_0_REMAP_LO,
465 .get_from_field = mv64x60_shift_left,
466 .map_to_field = mv64x60_shift_right,
468 [MV64x60_CPU2PCI1_MEM_1_REMAP_WIN] = {
469 .base_hi_reg = MV64x60_CPU2PCI1_MEM_1_REMAP_HI,
470 .base_lo_reg = MV64x60_CPU2PCI1_MEM_1_REMAP_LO,
474 .get_from_field = mv64x60_shift_left,
475 .map_to_field = mv64x60_shift_right,
477 [MV64x60_CPU2PCI1_MEM_2_REMAP_WIN] = {
478 .base_hi_reg = MV64x60_CPU2PCI1_MEM_2_REMAP_HI,
479 .base_lo_reg = MV64x60_CPU2PCI1_MEM_2_REMAP_LO,
483 .get_from_field = mv64x60_shift_left,
484 .map_to_field = mv64x60_shift_right,
486 [MV64x60_CPU2PCI1_MEM_3_REMAP_WIN] = {
487 .base_hi_reg = MV64x60_CPU2PCI1_MEM_3_REMAP_HI,
488 .base_lo_reg = MV64x60_CPU2PCI1_MEM_3_REMAP_LO,
492 .get_from_field = mv64x60_shift_left,
493 .map_to_field = mv64x60_shift_right,
495 /* PCI 0->MEM Access Control Windows */
496 [MV64x60_PCI02MEM_ACC_CNTL_0_WIN] = {
497 .base_hi_reg = MV64x60_PCI0_ACC_CNTL_0_BASE_HI,
498 .base_lo_reg = MV64x60_PCI0_ACC_CNTL_0_BASE_LO,
499 .size_reg = MV64x60_PCI0_ACC_CNTL_0_SIZE,
502 .get_from_field = mv64x60_shift_left,
503 .map_to_field = mv64x60_shift_right,
505 [MV64x60_PCI02MEM_ACC_CNTL_1_WIN] = {
506 .base_hi_reg = MV64x60_PCI0_ACC_CNTL_1_BASE_HI,
507 .base_lo_reg = MV64x60_PCI0_ACC_CNTL_1_BASE_LO,
508 .size_reg = MV64x60_PCI0_ACC_CNTL_1_SIZE,
511 .get_from_field = mv64x60_shift_left,
512 .map_to_field = mv64x60_shift_right,
514 [MV64x60_PCI02MEM_ACC_CNTL_2_WIN] = {
515 .base_hi_reg = MV64x60_PCI0_ACC_CNTL_2_BASE_HI,
516 .base_lo_reg = MV64x60_PCI0_ACC_CNTL_2_BASE_LO,
517 .size_reg = MV64x60_PCI0_ACC_CNTL_2_SIZE,
520 .get_from_field = mv64x60_shift_left,
521 .map_to_field = mv64x60_shift_right,
523 [MV64x60_PCI02MEM_ACC_CNTL_3_WIN] = {
524 .base_hi_reg = MV64x60_PCI0_ACC_CNTL_3_BASE_HI,
525 .base_lo_reg = MV64x60_PCI0_ACC_CNTL_3_BASE_LO,
526 .size_reg = MV64x60_PCI0_ACC_CNTL_3_SIZE,
529 .get_from_field = mv64x60_shift_left,
530 .map_to_field = mv64x60_shift_right,
532 /* PCI 1->MEM Access Control Windows */
533 [MV64x60_PCI12MEM_ACC_CNTL_0_WIN] = {
534 .base_hi_reg = MV64x60_PCI1_ACC_CNTL_0_BASE_HI,
535 .base_lo_reg = MV64x60_PCI1_ACC_CNTL_0_BASE_LO,
536 .size_reg = MV64x60_PCI1_ACC_CNTL_0_SIZE,
539 .get_from_field = mv64x60_shift_left,
540 .map_to_field = mv64x60_shift_right,
542 [MV64x60_PCI12MEM_ACC_CNTL_1_WIN] = {
543 .base_hi_reg = MV64x60_PCI1_ACC_CNTL_1_BASE_HI,
544 .base_lo_reg = MV64x60_PCI1_ACC_CNTL_1_BASE_LO,
545 .size_reg = MV64x60_PCI1_ACC_CNTL_1_SIZE,
548 .get_from_field = mv64x60_shift_left,
549 .map_to_field = mv64x60_shift_right,
551 [MV64x60_PCI12MEM_ACC_CNTL_2_WIN] = {
552 .base_hi_reg = MV64x60_PCI1_ACC_CNTL_2_BASE_HI,
553 .base_lo_reg = MV64x60_PCI1_ACC_CNTL_2_BASE_LO,
554 .size_reg = MV64x60_PCI1_ACC_CNTL_2_SIZE,
557 .get_from_field = mv64x60_shift_left,
558 .map_to_field = mv64x60_shift_right,
560 [MV64x60_PCI12MEM_ACC_CNTL_3_WIN] = {
561 .base_hi_reg = MV64x60_PCI1_ACC_CNTL_3_BASE_HI,
562 .base_lo_reg = MV64x60_PCI1_ACC_CNTL_3_BASE_LO,
563 .size_reg = MV64x60_PCI1_ACC_CNTL_3_SIZE,
566 .get_from_field = mv64x60_shift_left,
567 .map_to_field = mv64x60_shift_right,
569 /* PCI 0->MEM Snoop Windows */
570 [MV64x60_PCI02MEM_SNOOP_0_WIN] = {
571 .base_hi_reg = GT64260_PCI0_SNOOP_0_BASE_HI,
572 .base_lo_reg = GT64260_PCI0_SNOOP_0_BASE_LO,
573 .size_reg = GT64260_PCI0_SNOOP_0_SIZE,
576 .get_from_field = mv64x60_shift_left,
577 .map_to_field = mv64x60_shift_right,
579 [MV64x60_PCI02MEM_SNOOP_1_WIN] = {
580 .base_hi_reg = GT64260_PCI0_SNOOP_1_BASE_HI,
581 .base_lo_reg = GT64260_PCI0_SNOOP_1_BASE_LO,
582 .size_reg = GT64260_PCI0_SNOOP_1_SIZE,
585 .get_from_field = mv64x60_shift_left,
586 .map_to_field = mv64x60_shift_right,
588 [MV64x60_PCI02MEM_SNOOP_2_WIN] = {
589 .base_hi_reg = GT64260_PCI0_SNOOP_2_BASE_HI,
590 .base_lo_reg = GT64260_PCI0_SNOOP_2_BASE_LO,
591 .size_reg = GT64260_PCI0_SNOOP_2_SIZE,
594 .get_from_field = mv64x60_shift_left,
595 .map_to_field = mv64x60_shift_right,
597 [MV64x60_PCI02MEM_SNOOP_3_WIN] = {
598 .base_hi_reg = GT64260_PCI0_SNOOP_3_BASE_HI,
599 .base_lo_reg = GT64260_PCI0_SNOOP_3_BASE_LO,
600 .size_reg = GT64260_PCI0_SNOOP_3_SIZE,
603 .get_from_field = mv64x60_shift_left,
604 .map_to_field = mv64x60_shift_right,
606 /* PCI 1->MEM Snoop Windows */
607 [MV64x60_PCI12MEM_SNOOP_0_WIN] = {
608 .base_hi_reg = GT64260_PCI1_SNOOP_0_BASE_HI,
609 .base_lo_reg = GT64260_PCI1_SNOOP_0_BASE_LO,
610 .size_reg = GT64260_PCI1_SNOOP_0_SIZE,
613 .get_from_field = mv64x60_shift_left,
614 .map_to_field = mv64x60_shift_right,
616 [MV64x60_PCI12MEM_SNOOP_1_WIN] = {
617 .base_hi_reg = GT64260_PCI1_SNOOP_1_BASE_HI,
618 .base_lo_reg = GT64260_PCI1_SNOOP_1_BASE_LO,
619 .size_reg = GT64260_PCI1_SNOOP_1_SIZE,
622 .get_from_field = mv64x60_shift_left,
623 .map_to_field = mv64x60_shift_right,
625 [MV64x60_PCI12MEM_SNOOP_2_WIN] = {
626 .base_hi_reg = GT64260_PCI1_SNOOP_2_BASE_HI,
627 .base_lo_reg = GT64260_PCI1_SNOOP_2_BASE_LO,
628 .size_reg = GT64260_PCI1_SNOOP_2_SIZE,
631 .get_from_field = mv64x60_shift_left,
632 .map_to_field = mv64x60_shift_right,
634 [MV64x60_PCI12MEM_SNOOP_3_WIN] = {
635 .base_hi_reg = GT64260_PCI1_SNOOP_3_BASE_HI,
636 .base_lo_reg = GT64260_PCI1_SNOOP_3_BASE_LO,
637 .size_reg = GT64260_PCI1_SNOOP_3_SIZE,
640 .get_from_field = mv64x60_shift_left,
641 .map_to_field = mv64x60_shift_right,
645 static mv64x60_chip_info_t gt64260a_ci __initdata = {
646 .translate_size = gt64260_translate_size,
647 .untranslate_size = gt64260_untranslate_size,
648 .set_pci2mem_window = gt64260_set_pci2mem_window,
649 .is_enabled_32bit = gt64260_is_enabled_32bit,
650 .enable_window_32bit = gt64260_enable_window_32bit,
651 .disable_window_32bit = gt64260_disable_window_32bit,
652 .enable_window_64bit = gt64260_enable_window_64bit,
653 .disable_window_64bit = gt64260_disable_window_64bit,
654 .disable_all_windows = gt64260_disable_all_windows,
655 .chip_specific_init = gt64260a_chip_specific_init,
656 .window_tab_32bit = gt64260_32bit_windows,
657 .window_tab_64bit = gt64260_64bit_windows,
660 static mv64x60_chip_info_t gt64260b_ci __initdata = {
661 .translate_size = gt64260_translate_size,
662 .untranslate_size = gt64260_untranslate_size,
663 .set_pci2mem_window = gt64260_set_pci2mem_window,
664 .is_enabled_32bit = gt64260_is_enabled_32bit,
665 .enable_window_32bit = gt64260_enable_window_32bit,
666 .disable_window_32bit = gt64260_disable_window_32bit,
667 .enable_window_64bit = gt64260_enable_window_64bit,
668 .disable_window_64bit = gt64260_disable_window_64bit,
669 .disable_all_windows = gt64260_disable_all_windows,
670 .chip_specific_init = gt64260b_chip_specific_init,
671 .window_tab_32bit = gt64260_32bit_windows,
672 .window_tab_64bit = gt64260_64bit_windows,
676 static mv64x60_32bit_window_t mv64360_32bit_windows[] __initdata = {
677 /* CPU->MEM Windows */
678 [MV64x60_CPU2MEM_0_WIN] = {
679 .base_reg = MV64x60_CPU2MEM_0_BASE,
680 .size_reg = MV64x60_CPU2MEM_0_SIZE,
683 .get_from_field = mv64x60_shift_left,
684 .map_to_field = mv64x60_shift_right,
686 [MV64x60_CPU2MEM_1_WIN] = {
687 .base_reg = MV64x60_CPU2MEM_1_BASE,
688 .size_reg = MV64x60_CPU2MEM_1_SIZE,
691 .get_from_field = mv64x60_shift_left,
692 .map_to_field = mv64x60_shift_right,
694 [MV64x60_CPU2MEM_2_WIN] = {
695 .base_reg = MV64x60_CPU2MEM_2_BASE,
696 .size_reg = MV64x60_CPU2MEM_2_SIZE,
699 .get_from_field = mv64x60_shift_left,
700 .map_to_field = mv64x60_shift_right,
702 [MV64x60_CPU2MEM_3_WIN] = {
703 .base_reg = MV64x60_CPU2MEM_3_BASE,
704 .size_reg = MV64x60_CPU2MEM_3_SIZE,
707 .get_from_field = mv64x60_shift_left,
708 .map_to_field = mv64x60_shift_right,
710 /* CPU->Device Windows */
711 [MV64x60_CPU2DEV_0_WIN] = {
712 .base_reg = MV64x60_CPU2DEV_0_BASE,
713 .size_reg = MV64x60_CPU2DEV_0_SIZE,
716 .get_from_field = mv64x60_shift_left,
717 .map_to_field = mv64x60_shift_right,
719 [MV64x60_CPU2DEV_1_WIN] = {
720 .base_reg = MV64x60_CPU2DEV_1_BASE,
721 .size_reg = MV64x60_CPU2DEV_1_SIZE,
724 .get_from_field = mv64x60_shift_left,
725 .map_to_field = mv64x60_shift_right,
727 [MV64x60_CPU2DEV_2_WIN] = {
728 .base_reg = MV64x60_CPU2DEV_2_BASE,
729 .size_reg = MV64x60_CPU2DEV_2_SIZE,
732 .get_from_field = mv64x60_shift_left,
733 .map_to_field = mv64x60_shift_right,
735 [MV64x60_CPU2DEV_3_WIN] = {
736 .base_reg = MV64x60_CPU2DEV_3_BASE,
737 .size_reg = MV64x60_CPU2DEV_3_SIZE,
740 .get_from_field = mv64x60_shift_left,
741 .map_to_field = mv64x60_shift_right,
743 /* CPU->Boot Window */
744 [MV64x60_CPU2BOOT_WIN] = {
745 .base_reg = MV64x60_CPU2BOOT_0_BASE,
746 .size_reg = MV64x60_CPU2BOOT_0_SIZE,
749 .get_from_field = mv64x60_shift_left,
750 .map_to_field = mv64x60_shift_right,
752 /* CPU->PCI 0 Windows */
753 [MV64x60_CPU2PCI0_IO_WIN] = {
754 .base_reg = MV64x60_CPU2PCI0_IO_BASE,
755 .size_reg = MV64x60_CPU2PCI0_IO_SIZE,
758 .get_from_field = mv64x60_shift_left,
759 .map_to_field = mv64x60_shift_right,
761 [MV64x60_CPU2PCI0_MEM_0_WIN] = {
762 .base_reg = MV64x60_CPU2PCI0_MEM_0_BASE,
763 .size_reg = MV64x60_CPU2PCI0_MEM_0_SIZE,
766 .get_from_field = mv64x60_shift_left,
767 .map_to_field = mv64x60_shift_right,
769 [MV64x60_CPU2PCI0_MEM_1_WIN] = {
770 .base_reg = MV64x60_CPU2PCI0_MEM_1_BASE,
771 .size_reg = MV64x60_CPU2PCI0_MEM_1_SIZE,
774 .get_from_field = mv64x60_shift_left,
775 .map_to_field = mv64x60_shift_right,
777 [MV64x60_CPU2PCI0_MEM_2_WIN] = {
778 .base_reg = MV64x60_CPU2PCI0_MEM_2_BASE,
779 .size_reg = MV64x60_CPU2PCI0_MEM_2_SIZE,
782 .get_from_field = mv64x60_shift_left,
783 .map_to_field = mv64x60_shift_right,
785 [MV64x60_CPU2PCI0_MEM_3_WIN] = {
786 .base_reg = MV64x60_CPU2PCI0_MEM_3_BASE,
787 .size_reg = MV64x60_CPU2PCI0_MEM_3_SIZE,
790 .get_from_field = mv64x60_shift_left,
791 .map_to_field = mv64x60_shift_right,
793 /* CPU->PCI 1 Windows */
794 [MV64x60_CPU2PCI1_IO_WIN] = {
795 .base_reg = MV64x60_CPU2PCI1_IO_BASE,
796 .size_reg = MV64x60_CPU2PCI1_IO_SIZE,
799 .get_from_field = mv64x60_shift_left,
800 .map_to_field = mv64x60_shift_right,
802 [MV64x60_CPU2PCI1_MEM_0_WIN] = {
803 .base_reg = MV64x60_CPU2PCI1_MEM_0_BASE,
804 .size_reg = MV64x60_CPU2PCI1_MEM_0_SIZE,
807 .get_from_field = mv64x60_shift_left,
808 .map_to_field = mv64x60_shift_right,
810 [MV64x60_CPU2PCI1_MEM_1_WIN] = {
811 .base_reg = MV64x60_CPU2PCI1_MEM_1_BASE,
812 .size_reg = MV64x60_CPU2PCI1_MEM_1_SIZE,
815 .get_from_field = mv64x60_shift_left,
816 .map_to_field = mv64x60_shift_right,
818 [MV64x60_CPU2PCI1_MEM_2_WIN] = {
819 .base_reg = MV64x60_CPU2PCI1_MEM_2_BASE,
820 .size_reg = MV64x60_CPU2PCI1_MEM_2_SIZE,
823 .get_from_field = mv64x60_shift_left,
824 .map_to_field = mv64x60_shift_right,
826 [MV64x60_CPU2PCI1_MEM_3_WIN] = {
827 .base_reg = MV64x60_CPU2PCI1_MEM_3_BASE,
828 .size_reg = MV64x60_CPU2PCI1_MEM_3_SIZE,
831 .get_from_field = mv64x60_shift_left,
832 .map_to_field = mv64x60_shift_right,
834 /* CPU->SRAM Window */
835 [MV64x60_CPU2SRAM_WIN] = {
836 .base_reg = MV64360_CPU2SRAM_BASE,
840 .get_from_field = mv64x60_shift_left,
841 .map_to_field = mv64x60_shift_right,
843 /* CPU->PCI 0 Remap I/O Window */
844 [MV64x60_CPU2PCI0_IO_REMAP_WIN] = {
845 .base_reg = MV64x60_CPU2PCI0_IO_REMAP,
849 .get_from_field = mv64x60_shift_left,
850 .map_to_field = mv64x60_shift_right,
852 /* CPU->PCI 1 Remap I/O Window */
853 [MV64x60_CPU2PCI1_IO_REMAP_WIN] = {
854 .base_reg = MV64x60_CPU2PCI1_IO_REMAP,
858 .get_from_field = mv64x60_shift_left,
859 .map_to_field = mv64x60_shift_right,
861 /* CPU Memory Protection Windows */
862 [MV64x60_CPU_PROT_0_WIN] = {
863 .base_reg = MV64x60_CPU_PROT_BASE_0,
864 .size_reg = MV64x60_CPU_PROT_SIZE_0,
867 .get_from_field = mv64x60_shift_left,
868 .map_to_field = mv64x60_shift_right,
869 .extra = 0x80000000 | 31 },
870 [MV64x60_CPU_PROT_1_WIN] = {
871 .base_reg = MV64x60_CPU_PROT_BASE_1,
872 .size_reg = MV64x60_CPU_PROT_SIZE_1,
875 .get_from_field = mv64x60_shift_left,
876 .map_to_field = mv64x60_shift_right,
877 .extra = 0x80000000 | 31 },
878 [MV64x60_CPU_PROT_2_WIN] = {
879 .base_reg = MV64x60_CPU_PROT_BASE_2,
880 .size_reg = MV64x60_CPU_PROT_SIZE_2,
883 .get_from_field = mv64x60_shift_left,
884 .map_to_field = mv64x60_shift_right,
885 .extra = 0x80000000 | 31 },
886 [MV64x60_CPU_PROT_3_WIN] = {
887 .base_reg = MV64x60_CPU_PROT_BASE_3,
888 .size_reg = MV64x60_CPU_PROT_SIZE_3,
891 .get_from_field = mv64x60_shift_left,
892 .map_to_field = mv64x60_shift_right,
893 .extra = 0x80000000 | 31 },
894 /* CPU Snoop Windows -- don't exist on 64360 */
895 /* PCI 0->System Memory Remap Windows */
896 [MV64x60_PCI02MEM_REMAP_0_WIN] = {
897 .base_reg = MV64x60_PCI0_SLAVE_MEM_0_REMAP,
901 .get_from_field = mv64x60_mask,
902 .map_to_field = mv64x60_mask,
904 [MV64x60_PCI02MEM_REMAP_1_WIN] = {
905 .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP,
909 .get_from_field = mv64x60_mask,
910 .map_to_field = mv64x60_mask,
912 [MV64x60_PCI02MEM_REMAP_2_WIN] = {
913 .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP,
917 .get_from_field = mv64x60_mask,
918 .map_to_field = mv64x60_mask,
920 [MV64x60_PCI02MEM_REMAP_3_WIN] = {
921 .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP,
925 .get_from_field = mv64x60_mask,
926 .map_to_field = mv64x60_mask,
928 /* PCI 1->System Memory Remap Windows */
929 [MV64x60_PCI12MEM_REMAP_0_WIN] = {
930 .base_reg = MV64x60_PCI1_SLAVE_MEM_0_REMAP,
934 .get_from_field = mv64x60_mask,
935 .map_to_field = mv64x60_mask,
937 [MV64x60_PCI12MEM_REMAP_1_WIN] = {
938 .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP,
942 .get_from_field = mv64x60_mask,
943 .map_to_field = mv64x60_mask,
945 [MV64x60_PCI12MEM_REMAP_2_WIN] = {
946 .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP,
950 .get_from_field = mv64x60_mask,
951 .map_to_field = mv64x60_mask,
953 [MV64x60_PCI12MEM_REMAP_3_WIN] = {
954 .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP,
958 .get_from_field = mv64x60_mask,
959 .map_to_field = mv64x60_mask,
963 static mv64x60_64bit_window_t mv64360_64bit_windows[MV64x60_64BIT_WIN_COUNT]
965 /* CPU->PCI 0 MEM Remap Windows */
966 [MV64x60_CPU2PCI0_MEM_0_REMAP_WIN] = {
967 .base_hi_reg = MV64x60_CPU2PCI0_MEM_0_REMAP_HI,
968 .base_lo_reg = MV64x60_CPU2PCI0_MEM_0_REMAP_LO,
972 .get_from_field = mv64x60_shift_left,
973 .map_to_field = mv64x60_shift_right,
975 [MV64x60_CPU2PCI0_MEM_1_REMAP_WIN] = {
976 .base_hi_reg = MV64x60_CPU2PCI0_MEM_1_REMAP_HI,
977 .base_lo_reg = MV64x60_CPU2PCI0_MEM_1_REMAP_LO,
981 .get_from_field = mv64x60_shift_left,
982 .map_to_field = mv64x60_shift_right,
984 [MV64x60_CPU2PCI0_MEM_2_REMAP_WIN] = {
985 .base_hi_reg = MV64x60_CPU2PCI0_MEM_2_REMAP_HI,
986 .base_lo_reg = MV64x60_CPU2PCI0_MEM_2_REMAP_LO,
990 .get_from_field = mv64x60_shift_left,
991 .map_to_field = mv64x60_shift_right,
993 [MV64x60_CPU2PCI0_MEM_3_REMAP_WIN] = {
994 .base_hi_reg = MV64x60_CPU2PCI0_MEM_3_REMAP_HI,
995 .base_lo_reg = MV64x60_CPU2PCI0_MEM_3_REMAP_LO,
999 .get_from_field = mv64x60_shift_left,
1000 .map_to_field = mv64x60_shift_right,
1002 /* CPU->PCI 1 MEM Remap Windows */
1003 [MV64x60_CPU2PCI1_MEM_0_REMAP_WIN] = {
1004 .base_hi_reg = MV64x60_CPU2PCI1_MEM_0_REMAP_HI,
1005 .base_lo_reg = MV64x60_CPU2PCI1_MEM_0_REMAP_LO,
1009 .get_from_field = mv64x60_shift_left,
1010 .map_to_field = mv64x60_shift_right,
1012 [MV64x60_CPU2PCI1_MEM_1_REMAP_WIN] = {
1013 .base_hi_reg = MV64x60_CPU2PCI1_MEM_1_REMAP_HI,
1014 .base_lo_reg = MV64x60_CPU2PCI1_MEM_1_REMAP_LO,
1018 .get_from_field = mv64x60_shift_left,
1019 .map_to_field = mv64x60_shift_right,
1021 [MV64x60_CPU2PCI1_MEM_2_REMAP_WIN] = {
1022 .base_hi_reg = MV64x60_CPU2PCI1_MEM_2_REMAP_HI,
1023 .base_lo_reg = MV64x60_CPU2PCI1_MEM_2_REMAP_LO,
1027 .get_from_field = mv64x60_shift_left,
1028 .map_to_field = mv64x60_shift_right,
1030 [MV64x60_CPU2PCI1_MEM_3_REMAP_WIN] = {
1031 .base_hi_reg = MV64x60_CPU2PCI1_MEM_3_REMAP_HI,
1032 .base_lo_reg = MV64x60_CPU2PCI1_MEM_3_REMAP_LO,
1036 .get_from_field = mv64x60_shift_left,
1037 .map_to_field = mv64x60_shift_right,
1039 /* PCI 0->MEM Access Control Windows */
1040 [MV64x60_PCI02MEM_ACC_CNTL_0_WIN] = {
1041 .base_hi_reg = MV64x60_PCI0_ACC_CNTL_0_BASE_HI,
1042 .base_lo_reg = MV64x60_PCI0_ACC_CNTL_0_BASE_LO,
1043 .size_reg = MV64x60_PCI0_ACC_CNTL_0_SIZE,
1046 .get_from_field = mv64x60_mask,
1047 .map_to_field = mv64x60_mask,
1048 .extra = 0x80000000 | 0 },
1049 [MV64x60_PCI02MEM_ACC_CNTL_1_WIN] = {
1050 .base_hi_reg = MV64x60_PCI0_ACC_CNTL_1_BASE_HI,
1051 .base_lo_reg = MV64x60_PCI0_ACC_CNTL_1_BASE_LO,
1052 .size_reg = MV64x60_PCI0_ACC_CNTL_1_SIZE,
1055 .get_from_field = mv64x60_mask,
1056 .map_to_field = mv64x60_mask,
1057 .extra = 0x80000000 | 0 },
1058 [MV64x60_PCI02MEM_ACC_CNTL_2_WIN] = {
1059 .base_hi_reg = MV64x60_PCI0_ACC_CNTL_2_BASE_HI,
1060 .base_lo_reg = MV64x60_PCI0_ACC_CNTL_2_BASE_LO,
1061 .size_reg = MV64x60_PCI0_ACC_CNTL_2_SIZE,
1064 .get_from_field = mv64x60_mask,
1065 .map_to_field = mv64x60_mask,
1066 .extra = 0x80000000 | 0 },
1067 [MV64x60_PCI02MEM_ACC_CNTL_3_WIN] = {
1068 .base_hi_reg = MV64x60_PCI0_ACC_CNTL_3_BASE_HI,
1069 .base_lo_reg = MV64x60_PCI0_ACC_CNTL_3_BASE_LO,
1070 .size_reg = MV64x60_PCI0_ACC_CNTL_3_SIZE,
1073 .get_from_field = mv64x60_mask,
1074 .map_to_field = mv64x60_mask,
1075 .extra = 0x80000000 | 0 },
1076 /* PCI 1->MEM Access Control Windows */
1077 [MV64x60_PCI12MEM_ACC_CNTL_0_WIN] = {
1078 .base_hi_reg = MV64x60_PCI1_ACC_CNTL_0_BASE_HI,
1079 .base_lo_reg = MV64x60_PCI1_ACC_CNTL_0_BASE_LO,
1080 .size_reg = MV64x60_PCI1_ACC_CNTL_0_SIZE,
1083 .get_from_field = mv64x60_mask,
1084 .map_to_field = mv64x60_mask,
1085 .extra = 0x80000000 | 0 },
1086 [MV64x60_PCI12MEM_ACC_CNTL_1_WIN] = {
1087 .base_hi_reg = MV64x60_PCI1_ACC_CNTL_1_BASE_HI,
1088 .base_lo_reg = MV64x60_PCI1_ACC_CNTL_1_BASE_LO,
1089 .size_reg = MV64x60_PCI1_ACC_CNTL_1_SIZE,
1092 .get_from_field = mv64x60_mask,
1093 .map_to_field = mv64x60_mask,
1094 .extra = 0x80000000 | 0 },
1095 [MV64x60_PCI12MEM_ACC_CNTL_2_WIN] = {
1096 .base_hi_reg = MV64x60_PCI1_ACC_CNTL_2_BASE_HI,
1097 .base_lo_reg = MV64x60_PCI1_ACC_CNTL_2_BASE_LO,
1098 .size_reg = MV64x60_PCI1_ACC_CNTL_2_SIZE,
1101 .get_from_field = mv64x60_mask,
1102 .map_to_field = mv64x60_mask,
1103 .extra = 0x80000000 | 0 },
1104 [MV64x60_PCI12MEM_ACC_CNTL_3_WIN] = {
1105 .base_hi_reg = MV64x60_PCI1_ACC_CNTL_3_BASE_HI,
1106 .base_lo_reg = MV64x60_PCI1_ACC_CNTL_3_BASE_LO,
1107 .size_reg = MV64x60_PCI1_ACC_CNTL_3_SIZE,
1110 .get_from_field = mv64x60_mask,
1111 .map_to_field = mv64x60_mask,
1112 .extra = 0x80000000 | 0 },
1113 /* PCI 0->MEM Snoop Windows -- don't exist on 64360 */
1114 /* PCI 1->MEM Snoop Windows -- don't exist on 64360 */
1117 static mv64x60_chip_info_t mv64360_ci __initdata = {
1118 .translate_size = mv64360_translate_size,
1119 .untranslate_size = mv64360_untranslate_size,
1120 .set_pci2mem_window = mv64360_set_pci2mem_window,
1121 .is_enabled_32bit = mv64360_is_enabled_32bit,
1122 .enable_window_32bit = mv64360_enable_window_32bit,
1123 .disable_window_32bit = mv64360_disable_window_32bit,
1124 .enable_window_64bit = mv64360_enable_window_64bit,
1125 .disable_window_64bit = mv64360_disable_window_64bit,
1126 .disable_all_windows = mv64360_disable_all_windows,
1127 .chip_specific_init = mv64360_chip_specific_init,
1128 .window_tab_32bit = mv64360_32bit_windows,
1129 .window_tab_64bit = mv64360_64bit_windows,
1132 static mv64x60_chip_info_t mv64460_ci __initdata = {
1133 .translate_size = mv64360_translate_size,
1134 .untranslate_size = mv64360_untranslate_size,
1135 .set_pci2mem_window = mv64360_set_pci2mem_window,
1136 .is_enabled_32bit = mv64360_is_enabled_32bit,
1137 .enable_window_32bit = mv64360_enable_window_32bit,
1138 .disable_window_32bit = mv64360_disable_window_32bit,
1139 .enable_window_64bit = mv64360_enable_window_64bit,
1140 .disable_window_64bit = mv64360_disable_window_64bit,
1141 .disable_all_windows = mv64360_disable_all_windows,
1142 .chip_specific_init = mv64460_chip_specific_init,
1143 .window_tab_32bit = mv64360_32bit_windows,
1144 .window_tab_64bit = mv64360_64bit_windows,
1149 *****************************************************************************
1151 * Bridge Initialization Routines
1153 *****************************************************************************
1158 * Initialze the bridge based on setting passed in via 'si'. The bridge
1159 * handle, 'bh', will be set so that it can be used to make subsequent
1160 * calls to routines in this file.
1163 mv64x60_init(mv64x60_handle_t *bh, mv64x60_setup_info_t *si)
1165 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2];
1168 if (ppc_md.progress)
1169 ppc_md.progress("mv64x60_init: Enter", 0x0);
1171 mv64x60_early_init(bh, si);
1172 mv64x60_alloc_hoses(bh, si); /* Allocate pci hose structures */
1173 if (mv64x60_get_type(bh))
1176 if (mv64x60_setup_for_chip(bh) != 0) {
1177 iounmap((void *)bh->v_base);
1179 if (ppc_md.progress)
1180 ppc_md.progress("mv64x60_init: Exit--error", 0x0);
1184 bh->ci->disable_all_windows(bh, si); /* Disable windows except mem ctlr */
1185 mv64x60_config_cpu2pci_windows(bh, si); /* Init CPU->PCI windows */
1186 mv64x60_get_mem_windows(bh, mem_windows); /* Read mem ctlr regs */
1187 mv64x60_config_cpu2mem_windows(bh, si, mem_windows); /* CPU->MEM setup*/
1188 mv64x60_config_pci2mem_windows(bh, si, mem_windows); /* PCI->Sys MEM */
1189 mv64x60_init_hoses(bh, si); /* Init hose structs & PCI params */
1190 bh->ci->chip_specific_init(bh, si);
1191 mv64x60_enumerate_buses(bh, si); /* Enumerate PCI buses */
1192 ocp_for_each_device(mv64x60_fixup_ocp, (void *)bh);
1194 if (ppc_md.progress)
1195 ppc_md.progress("mv64x60_init: Exit", 0x0);
1198 } /* mv64x60_init() */
1201 *****************************************************************************
1203 * Pre-Bridge-Init Routines (Externally Visible)
1205 *****************************************************************************
1208 * mv64x60_get_mem_size()
1210 * Calculate the amount of memory that the memory controller is set up for.
1211 * This should only be used by board-specific code if there is no other
1212 * way to determine the amount of memory in the system.
1215 mv64x60_get_mem_size(u32 bridge_base, u32 chip_type)
1217 mv64x60_handle_t bh;
1218 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2];
1220 memset(&bh, 0, sizeof(bh));
1222 bh.type = chip_type;
1223 bh.p_base = bridge_base;
1224 bh.v_base = bridge_base;
1226 (void)mv64x60_setup_for_chip(&bh);
1227 mv64x60_get_mem_windows(&bh, mem_windows);
1228 return mv64x60_calc_mem_size(&bh, mem_windows);
1232 *****************************************************************************
1234 * Window Config Routines (Externally Visible)
1236 *****************************************************************************
1239 * mv64x60_get_32bit_window()
1241 * Determine the base address and size of a 32-bit window on the bridge.
1244 mv64x60_get_32bit_window(mv64x60_handle_t *bh, u32 window, u32 *base, u32 *size)
1246 u32 val, base_reg, size_reg, base_bits, size_bits;
1247 u32 (*get_from_field)(u32 val, u32 num_bits);
1249 base_reg = bh->ci->window_tab_32bit[window].base_reg;
1251 if (base_reg != 0) {
1252 size_reg = bh->ci->window_tab_32bit[window].size_reg;
1253 base_bits = bh->ci->window_tab_32bit[window].base_bits;
1254 size_bits = bh->ci->window_tab_32bit[window].size_bits;
1255 get_from_field= bh->ci->window_tab_32bit[window].get_from_field;
1257 val = mv64x60_read(bh, base_reg);
1258 *base = get_from_field(val, base_bits);
1260 if (size_reg != 0) {
1261 val = mv64x60_read(bh, size_reg);
1262 val = get_from_field(val, size_bits);
1263 *size = bh->ci->untranslate_size(*base, val, size_bits);
1274 DBG("get 32bit window: %d, base: 0x%x, size: 0x%x\n",
1275 window, *base, *size);
1281 * mv64x60_set_32bit_window()
1283 * Set the base address and size of a 32-bit window on the bridge.
1286 mv64x60_set_32bit_window(mv64x60_handle_t *bh, u32 window, u32 base, u32 size,
1289 u32 val, base_reg, size_reg, base_bits, size_bits;
1290 u32 (*map_to_field)(u32 val, u32 num_bits);
1292 DBG("set 32bit window: %d, base: 0x%x, size: 0x%x, other: 0x%x\n",
1293 window, base, size, other_bits);
1295 base_reg = bh->ci->window_tab_32bit[window].base_reg;
1297 if (base_reg != 0) {
1298 size_reg = bh->ci->window_tab_32bit[window].size_reg;
1299 base_bits = bh->ci->window_tab_32bit[window].base_bits;
1300 size_bits = bh->ci->window_tab_32bit[window].size_bits;
1301 map_to_field = bh->ci->window_tab_32bit[window].map_to_field;
1303 val = map_to_field(base, base_bits) | other_bits;
1304 mv64x60_write(bh, base_reg, val);
1306 if (size_reg != 0) {
1307 val = bh->ci->translate_size(base, size, size_bits);
1308 val = map_to_field(val, size_bits);
1309 mv64x60_write(bh, size_reg, val);
1311 (void)mv64x60_read(bh, base_reg); /* Flush FIFO */
1318 * mv64x60_get_64bit_window()
1320 * Determine the base address and size of a 64-bit window on the bridge.
1323 mv64x60_get_64bit_window(mv64x60_handle_t *bh, u32 window, u32 *base_hi,
1324 u32 *base_lo, u32 *size)
1326 u32 val, base_lo_reg, size_reg, base_lo_bits, size_bits;
1327 u32 (*get_from_field)(u32 val, u32 num_bits);
1329 base_lo_reg = bh->ci->window_tab_64bit[window].base_lo_reg;
1331 if (base_lo_reg != 0) {
1332 size_reg = bh->ci->window_tab_64bit[window].size_reg;
1333 base_lo_bits = bh->ci->window_tab_64bit[window].base_lo_bits;
1334 size_bits = bh->ci->window_tab_64bit[window].size_bits;
1335 get_from_field= bh->ci->window_tab_64bit[window].get_from_field;
1337 *base_hi = mv64x60_read(bh,
1338 bh->ci->window_tab_64bit[window].base_hi_reg);
1340 val = mv64x60_read(bh, base_lo_reg);
1341 *base_lo = get_from_field(val, base_lo_bits);
1343 if (size_reg != 0) {
1344 val = mv64x60_read(bh, size_reg);
1345 val = get_from_field(val, size_bits);
1346 *size = bh->ci->untranslate_size(*base_lo, val,
1359 DBG("get 64bit window: %d, base hi: 0x%x, base lo: 0x%x, size: 0x%x\n",
1360 window, *base_hi, *base_lo, *size);
1366 * mv64x60_set_64bit_window()
1368 * Set the base address and size of a 64-bit window on the bridge.
1371 mv64x60_set_64bit_window(mv64x60_handle_t *bh, u32 window,
1372 u32 base_hi, u32 base_lo, u32 size, u32 other_bits)
1374 u32 val, base_lo_reg, size_reg, base_lo_bits, size_bits;
1375 u32 (*map_to_field)(u32 val, u32 num_bits);
1377 DBG("set 64bit window: %d, base hi: 0x%x, base lo: 0x%x, " \
1378 "size: 0x%x, other: 0x%x\n",
1379 window, base_hi, base_lo, size, other_bits);
1381 base_lo_reg = bh->ci->window_tab_64bit[window].base_lo_reg;
1383 if (base_lo_reg != 0) {
1384 size_reg = bh->ci->window_tab_64bit[window].size_reg;
1385 base_lo_bits = bh->ci->window_tab_64bit[window].base_lo_bits;
1386 size_bits = bh->ci->window_tab_64bit[window].size_bits;
1387 map_to_field = bh->ci->window_tab_64bit[window].map_to_field;
1389 mv64x60_write(bh, bh->ci->window_tab_64bit[window].base_hi_reg,
1392 val = map_to_field(base_lo, base_lo_bits) | other_bits;
1393 mv64x60_write(bh, base_lo_reg, val);
1395 if (size_reg != 0) {
1396 val = bh->ci->translate_size(base_lo, size, size_bits);
1397 val = map_to_field(val, size_bits);
1398 mv64x60_write(bh, size_reg, val);
1401 (void)mv64x60_read(bh, base_lo_reg); /* Flush FIFO */
1410 * Take the high-order 'num_bits' of 'val' & mask off low bits.
1413 mv64x60_mask(u32 val, u32 num_bits)
1415 DBG("mask val: 0x%x, num_bits: %d == 0x%x\n", val,
1416 num_bits, val & (0xffffffff << (32 - num_bits)));
1418 return val & (0xffffffff << (32 - num_bits));
1422 * mv64x60_mask_shift_left()
1424 * Take the low-order 'num_bits' of 'val', shift left to align at bit 31 (MSB).
1427 mv64x60_shift_left(u32 val, u32 num_bits)
1429 DBG("shift left val: 0x%x, num_bits: %d == 0x%x\n", val,
1430 num_bits, val << (32 - num_bits));
1432 return val << (32 - num_bits);
1436 * mv64x60_shift_right()
1438 * Take the high-order 'num_bits' of 'val', shift right to align at bit 0 (LSB).
1441 mv64x60_shift_right(u32 val, u32 num_bits)
1443 DBG("shift right val: 0x%x, num_bits: %d == 0x%x\n", val, num_bits,
1444 val >> (32 - num_bits));
1446 return val >> (32 - num_bits);
1450 *****************************************************************************
1452 * Early Init Routines
1454 *****************************************************************************
1457 * mv64x60_early_init()
1459 * Do some bridge work that must take place before we start messing with
1460 * the bridge for real.
1463 mv64x60_early_init(mv64x60_handle_t *bh, mv64x60_setup_info_t *si)
1465 memset(bh, 0, sizeof(*bh));
1467 bh->p_base = si->phys_reg_base;
1468 bh->v_base = (u32)ioremap(bh->p_base, MV64x60_INTERNAL_SPACE_SIZE);
1469 bh->base_irq = si->base_irq;
1471 /* Bit 12 MUST be 0; set bit 27--don't auto-update cpu remap regs */
1472 mv64x60_clr_bits(bh, MV64x60_CPU_CONFIG, (1<<12));
1473 mv64x60_set_bits(bh, MV64x60_CPU_CONFIG, (1<<27));
1476 * Turn off timer/counters. Not turning off watchdog timer because
1477 * can't read its reg on the 64260A so don't know if we'll be enabling
1480 mv64x60_clr_bits(bh, MV64x60_TIMR_CNTR_0_3_CNTL,
1481 ((1<<0) | (1<<8) | (1<<16) | (1<<24)));
1483 #ifdef CONFIG_GT64260
1484 mv64x60_clr_bits(bh, GT64260_TIMR_CNTR_4_7_CNTL,
1485 ((1<<0) | (1<<8) | (1<<16) | (1<<24)));
1489 XXXX Put in PCI_x_RETRY adjustment XXXX
1496 *****************************************************************************
1498 * Chip Identification Routines
1500 *****************************************************************************
1503 * mv64x60_get_type()
1505 * Determine the type of bridge chip we have.
1507 static int __init mv64x60_get_type(struct mv64x60_handle *bh)
1509 struct pci_controller *hose = bh->hose_a;
1515 pcidev = (mv64x60_read(bh, MV64x60_PCI0_P2P_CONFIG) >> 24) & 0xf;
1516 devfn = PCI_DEVFN(pcidev, 0);
1518 save_exclude = mv64x60_pci_exclude_bridge;
1519 mv64x60_pci_exclude_bridge = FALSE;
1521 /* Sanity check of bridge's Vendor ID */
1522 early_read_config_word(hose, 0, devfn, PCI_VENDOR_ID, &val);
1524 if (val != PCI_VENDOR_ID_MARVELL)
1527 /* Figure out the type of Marvell bridge it is */
1528 early_read_config_word(hose, 0, devfn, PCI_DEVICE_ID, &val);
1531 case PCI_DEVICE_ID_MARVELL_GT64260:
1532 early_read_config_word(hose, 0, devfn,
1533 PCI_CLASS_REVISION, &val);
1535 switch (val & 0xff) {
1537 bh->type = MV64x60_TYPE_GT64260A;
1540 bh->type = MV64x60_TYPE_GT64260B;
1545 case PCI_DEVICE_ID_MARVELL_MV64360:
1546 /* Marvell won't tell me how to distinguish a 64361 & 64362 */
1547 bh->type = MV64x60_TYPE_MV64360;
1550 case PCI_DEVICE_ID_MARVELL_MV64460:
1551 bh->type = MV64x60_TYPE_MV64460;
1555 printk(KERN_CRIT "Unknown Marvell bridge type %04x\n", val);
1559 mv64x60_pci_exclude_bridge = save_exclude;
1564 * mv64x60_setup_for_chip()
1566 * Set 'bh' to use the proper set of routine for the bridge chip that we have.
1569 mv64x60_setup_for_chip(mv64x60_handle_t *bh)
1573 /* Set up chip-specific info based on the chip/bridge type */
1575 case MV64x60_TYPE_GT64260A:
1576 bh->ci = >64260a_ci;
1579 case MV64x60_TYPE_GT64260B:
1580 bh->ci = >64260b_ci;
1583 case MV64x60_TYPE_MV64360:
1584 bh->ci = &mv64360_ci;
1587 #if 0 /* Marvell won't tell me how to distinguish--MAG */
1588 case MV64x60_TYPE_MV64361:
1589 case MV64x60_TYPE_MV64362:
1591 case MV64x60_TYPE_MV64460:
1592 bh->ci = &mv64460_ci;
1595 case MV64x60_TYPE_INVALID:
1597 if (ppc_md.progress)
1598 ppc_md.progress("mv64x60: Unsupported bridge",
1600 printk("mv64x60: Unsupported bridge\n");
1608 *****************************************************************************
1610 * System Memory Window Related Routines
1612 *****************************************************************************
1615 * mv64x60_get_mem_windows()
1617 * Get the values in the memory controller & return in the 'mem_windows' array.
1620 mv64x60_get_mem_windows(mv64x60_handle_t *bh,
1621 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1624 u32 windows[] = { MV64x60_CPU2MEM_0_WIN, MV64x60_CPU2MEM_1_WIN,
1625 MV64x60_CPU2MEM_2_WIN, MV64x60_CPU2MEM_3_WIN };
1627 for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
1628 if (bh->ci->is_enabled_32bit(bh, i)) {
1629 mv64x60_get_32bit_window(bh, windows[i],
1630 &mem_windows[i][0], &mem_windows[i][1]);
1633 mem_windows[i][0] = 0;
1634 mem_windows[i][1] = 0;
1642 * mv64x60_calc_mem_size()
1644 * Using the memory controller register values in 'mem_windows', determine
1645 * how much memory it is set up for.
1648 mv64x60_calc_mem_size(mv64x60_handle_t *bh,
1649 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1653 for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
1654 total += mem_windows[i][1];
1661 *****************************************************************************
1663 * CPU->System MEM Config Routines
1665 *****************************************************************************
1668 * mv64x60_config_cpu2mem_windows()
1670 * Configure CPU->Memory windows on the bridge.
1673 mv64x60_config_cpu2mem_windows(mv64x60_handle_t *bh, mv64x60_setup_info_t *si,
1674 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1677 u32 prot_windows[] = {
1678 MV64x60_CPU_PROT_0_WIN, MV64x60_CPU_PROT_1_WIN,
1679 MV64x60_CPU_PROT_2_WIN, MV64x60_CPU_PROT_3_WIN };
1680 u32 cpu_snoop_windows[] = {
1681 MV64x60_CPU_SNOOP_0_WIN, MV64x60_CPU_SNOOP_1_WIN,
1682 MV64x60_CPU_SNOOP_2_WIN, MV64x60_CPU_SNOOP_3_WIN };
1684 /* Set CPU protection & snoop windows */
1685 for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
1686 if (bh->ci->is_enabled_32bit(bh, i)) {
1687 mv64x60_set_32bit_window(bh, prot_windows[i],
1688 mem_windows[i][0], mem_windows[i][1],
1689 si->cpu_prot_options[i]);
1690 bh->ci->enable_window_32bit(bh, prot_windows[i]);
1692 if (bh->ci->window_tab_32bit[cpu_snoop_windows[i]].
1694 mv64x60_set_32bit_window(bh,
1695 cpu_snoop_windows[i], mem_windows[i][0],
1697 si->cpu_snoop_options[i]);
1698 bh->ci->enable_window_32bit(bh,
1699 cpu_snoop_windows[i]);
1709 *****************************************************************************
1711 * CPU->PCI Config Routines
1713 *****************************************************************************
1717 * mv64x60_config_cpu2pci_windows()
1719 * Configure the CPU->PCI windows on the bridge.
1722 mv64x60_config_cpu2pci_windows(mv64x60_handle_t *bh, mv64x60_setup_info_t *si)
1724 if (ppc_md.progress)
1725 ppc_md.progress("mv64x60_config_bridge: Enter", 0x0);
1728 * Set up various parts of the bridge including CPU->PCI windows.
1729 * Depending on the board, there may be only one hose that needs to
1732 if (si->pci_0.enable_bus) {
1733 u32 win_tab[] = { MV64x60_CPU2PCI0_IO_WIN,
1734 MV64x60_CPU2PCI0_MEM_0_WIN,
1735 MV64x60_CPU2PCI0_MEM_1_WIN,
1736 MV64x60_CPU2PCI0_MEM_2_WIN };
1737 u32 remap_tab[] = { MV64x60_CPU2PCI0_IO_REMAP_WIN,
1738 MV64x60_CPU2PCI0_MEM_0_REMAP_WIN,
1739 MV64x60_CPU2PCI0_MEM_1_REMAP_WIN,
1740 MV64x60_CPU2PCI0_MEM_2_REMAP_WIN };
1742 mv64x60_set_cpu2pci_window(bh, &si->pci_0, win_tab, remap_tab);
1745 if (si->pci_1.enable_bus) {
1746 u32 win_tab[] = { MV64x60_CPU2PCI1_IO_WIN,
1747 MV64x60_CPU2PCI1_MEM_0_WIN,
1748 MV64x60_CPU2PCI1_MEM_1_WIN,
1749 MV64x60_CPU2PCI1_MEM_2_WIN };
1750 u32 remap_tab[] = { MV64x60_CPU2PCI1_IO_REMAP_WIN,
1751 MV64x60_CPU2PCI1_MEM_0_REMAP_WIN,
1752 MV64x60_CPU2PCI1_MEM_1_REMAP_WIN,
1753 MV64x60_CPU2PCI1_MEM_2_REMAP_WIN };
1755 mv64x60_set_cpu2pci_window(bh, &si->pci_1, win_tab, remap_tab);
1759 } /* mv64x60_config_bridge() */
1762 * mv64x60_set_cpu2pci_window()
1764 * Configure the CPU->PCI windows for one of the PCI buses.
1767 mv64x60_set_cpu2pci_window(mv64x60_handle_t *bh, mv64x60_pci_info_t *pi,
1768 u32 *win_tab, u32 *remap_tab)
1772 if (pi->pci_io.size > 0) {
1773 mv64x60_set_32bit_window(bh, win_tab[0], pi->pci_io.cpu_base,
1774 pi->pci_io.size, pi->pci_io.swap);
1775 mv64x60_set_32bit_window(bh, remap_tab[0],
1776 pi->pci_io.pci_base_lo, 0, 0);
1777 bh->ci->enable_window_32bit(bh, win_tab[0]);
1779 else { /* Actually, the window should already be disabled */
1780 bh->ci->disable_window_32bit(bh, win_tab[0]);
1783 for (i=0; i<3; i++) {
1784 if (pi->pci_mem[i].size > 0) {
1785 mv64x60_set_32bit_window(bh, win_tab[i+1],
1786 pi->pci_mem[i].cpu_base, pi->pci_mem[i].size,
1787 pi->pci_mem[i].swap);
1788 mv64x60_set_64bit_window(bh, remap_tab[i+1],
1789 pi->pci_mem[i].pci_base_hi,
1790 pi->pci_mem[i].pci_base_lo, 0, 0);
1791 bh->ci->enable_window_32bit(bh, win_tab[i+1]);
1793 else { /* Actually, the window should already be disabled */
1794 bh->ci->disable_window_32bit(bh, win_tab[i+1]);
1802 *****************************************************************************
1804 * PCI->System MEM Config Routines
1806 *****************************************************************************
1809 * mv64x60_config_pci2mem_windows()
1811 * Configure the PCI->Memory windows on the bridge.
1814 mv64x60_config_pci2mem_windows(mv64x60_handle_t *bh, mv64x60_setup_info_t *si,
1815 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1818 u32 pci_0_acc_windows[] = {
1819 MV64x60_PCI02MEM_ACC_CNTL_0_WIN,
1820 MV64x60_PCI02MEM_ACC_CNTL_1_WIN,
1821 MV64x60_PCI02MEM_ACC_CNTL_2_WIN,
1822 MV64x60_PCI02MEM_ACC_CNTL_3_WIN };
1823 u32 pci_1_acc_windows[] = {
1824 MV64x60_PCI12MEM_ACC_CNTL_0_WIN,
1825 MV64x60_PCI12MEM_ACC_CNTL_1_WIN,
1826 MV64x60_PCI12MEM_ACC_CNTL_2_WIN,
1827 MV64x60_PCI12MEM_ACC_CNTL_3_WIN };
1828 u32 pci_0_snoop_windows[] = {
1829 MV64x60_PCI02MEM_SNOOP_0_WIN,
1830 MV64x60_PCI02MEM_SNOOP_1_WIN,
1831 MV64x60_PCI02MEM_SNOOP_2_WIN,
1832 MV64x60_PCI02MEM_SNOOP_3_WIN };
1833 u32 pci_1_snoop_windows[] = {
1834 MV64x60_PCI12MEM_SNOOP_0_WIN,
1835 MV64x60_PCI12MEM_SNOOP_1_WIN,
1836 MV64x60_PCI12MEM_SNOOP_2_WIN,
1837 MV64x60_PCI12MEM_SNOOP_3_WIN };
1838 u32 pci_0_size[] = {
1839 MV64x60_PCI0_MEM_0_SIZE, MV64x60_PCI0_MEM_1_SIZE,
1840 MV64x60_PCI0_MEM_2_SIZE, MV64x60_PCI0_MEM_3_SIZE };
1841 u32 pci_1_size[] = {
1842 MV64x60_PCI1_MEM_0_SIZE, MV64x60_PCI1_MEM_1_SIZE,
1843 MV64x60_PCI1_MEM_2_SIZE, MV64x60_PCI1_MEM_3_SIZE };
1845 /* Clear bit 0 of PCI addr decode control so PCI->CPU remap 1:1 */
1846 mv64x60_clr_bits(bh, MV64x60_PCI0_PCI_DECODE_CNTL, 0x00000001);
1847 mv64x60_clr_bits(bh, MV64x60_PCI1_PCI_DECODE_CNTL, 0x00000001);
1850 * Set the access control, snoop, BAR size, and window base addresses.
1851 * PCI->MEM windows base addresses will match exactly what the
1852 * CPU->MEM windows are.
1854 for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
1855 if (bh->ci->is_enabled_32bit(bh, i)) {
1856 if (si->pci_0.enable_bus) {
1857 mv64x60_set_64bit_window(bh,
1858 pci_0_acc_windows[i], 0,
1859 mem_windows[i][0], mem_windows[i][1],
1860 si->pci_0.acc_cntl_options[i]);
1861 bh->ci->enable_window_64bit(bh,
1862 pci_0_acc_windows[i]);
1864 if (bh->ci->window_tab_64bit[
1865 pci_0_snoop_windows[i]].base_lo_reg
1867 mv64x60_set_64bit_window(bh,
1868 pci_0_snoop_windows[i], 0,
1871 si->pci_0.snoop_options[i]);
1872 bh->ci->enable_window_64bit(bh,
1873 pci_0_snoop_windows[i]);
1876 bh->ci->set_pci2mem_window(bh->hose_a, i,
1878 mv64x60_write(bh, pci_0_size[i],
1879 mv64x60_mask(mem_windows[i][1] -1, 20));
1881 /* Enable the window */
1882 mv64x60_clr_bits(bh, MV64x60_PCI0_BAR_ENABLE,
1885 if (si->pci_1.enable_bus) {
1886 mv64x60_set_64bit_window(bh,
1887 pci_1_acc_windows[i], 0,
1888 mem_windows[i][0], mem_windows[i][1],
1889 si->pci_1.acc_cntl_options[i]);
1890 bh->ci->enable_window_64bit(bh,
1891 pci_1_acc_windows[i]);
1893 if (bh->ci->window_tab_64bit[
1894 pci_1_snoop_windows[i]].base_lo_reg
1896 mv64x60_set_64bit_window(bh,
1897 pci_1_snoop_windows[i], 0,
1900 si->pci_1.snoop_options[i]);
1901 bh->ci->enable_window_64bit(bh,
1902 pci_1_snoop_windows[i]);
1905 bh->ci->set_pci2mem_window(bh->hose_b, i,
1907 mv64x60_write(bh, pci_1_size[i],
1908 mv64x60_mask(mem_windows[i][1] -1, 20));
1910 /* Enable the window */
1911 mv64x60_clr_bits(bh, MV64x60_PCI1_BAR_ENABLE,
1921 *****************************************************************************
1923 * Hose & Resource Alloc/Init Routines
1925 *****************************************************************************
1928 * mv64x60_alloc_hoses()
1930 * Allocate the PCI hose structures for the bridge's PCI buses.
1933 mv64x60_alloc_hoses(mv64x60_handle_t *bh, mv64x60_setup_info_t *si)
1936 * Alloc first hose struct even when its not to be configured b/c the
1937 * chip identification routines need to use it.
1939 bh->hose_a = pcibios_alloc_controller();
1940 setup_indirect_pci(bh->hose_a,
1941 bh->p_base + MV64x60_PCI0_CONFIG_ADDR,
1942 bh->p_base + MV64x60_PCI0_CONFIG_DATA);
1944 if (si->pci_1.enable_bus) {
1945 bh->hose_b = pcibios_alloc_controller();
1946 setup_indirect_pci(bh->hose_b,
1947 bh->p_base + MV64x60_PCI1_CONFIG_ADDR,
1948 bh->p_base + MV64x60_PCI1_CONFIG_DATA);
1955 * mv64x60_init_hoses()
1957 * Initialize the PCI hose structures for the bridge's PCI hoses.
1960 mv64x60_init_hoses(mv64x60_handle_t *bh, mv64x60_setup_info_t *si)
1962 if (si->pci_1.enable_bus) {
1963 bh->io_base_b = (u32)ioremap(si->pci_1.pci_io.cpu_base,
1964 si->pci_1.pci_io.size);
1965 isa_io_base = bh->io_base_b;
1968 if (si->pci_0.enable_bus) {
1969 bh->io_base_a = (u32)ioremap(si->pci_0.pci_io.cpu_base,
1970 si->pci_0.pci_io.size);
1971 isa_io_base = bh->io_base_a;
1973 mv64x60_init_resources(bh->hose_a, &si->pci_0, bh->io_base_a);
1974 mv64x60_set_pci_params(bh->hose_a, &si->pci_0);
1977 /* Must do here so proper isa_io_base is used in calculations */
1978 if (si->pci_1.enable_bus) {
1979 mv64x60_init_resources(bh->hose_b, &si->pci_1, bh->io_base_b);
1980 mv64x60_set_pci_params(bh->hose_b, &si->pci_1);
1987 * mv64x60_init_resources()
1989 * Calculate the offsets, etc. for the hose structures to reflect all of
1990 * the address remapping that happens as you go from CPU->PCI and PCI->MEM.
1993 mv64x60_init_resources(struct pci_controller *hose, mv64x60_pci_info_t *pi,
1997 /* 2 hoses; 4 resources/hose; sting <= 64 bytes; not work if > 1 chip */
1998 static char s[2][4][64];
2000 if (pi->pci_io.size != 0) {
2001 sprintf(s[hose->index][0], "PCI hose %d I/O Space",
2003 pci_init_resource(&hose->io_resource, io_base - isa_io_base,
2004 io_base - isa_io_base + pi->pci_io.size - 1,
2005 IORESOURCE_IO, s[hose->index][0]);
2006 hose->io_space.start = pi->pci_io.pci_base_lo;
2007 hose->io_space.end = pi->pci_io.pci_base_lo + pi->pci_io.size-1;
2008 hose->io_base_virt = (void *)isa_io_base;
2011 for (i=0; i<3; i++) {
2012 if (pi->pci_mem[i].size != 0) {
2013 sprintf(s[hose->index][i+1], "PCI hose %d MEM Space %d",
2015 pci_init_resource(&hose->mem_resources[i],
2016 pi->pci_mem[i].cpu_base,
2017 pi->pci_mem[i].cpu_base + pi->pci_mem[i].size-1,
2018 IORESOURCE_MEM, s[hose->index][i+1]);
2022 hose->mem_space.end = pi->pci_mem[0].pci_base_lo +
2023 pi->pci_mem[0].size - 1;
2024 hose->pci_mem_offset = pi->pci_mem[0].cpu_base -
2025 pi->pci_mem[0].pci_base_lo;
2028 } /* mv64x60_init_resources() */
2031 * mv64x60_set_pci_params()
2033 * Configure a hose's PCI config space parameters.
2036 mv64x60_set_pci_params(struct pci_controller *hose, mv64x60_pci_info_t *pi)
2042 devfn = PCI_DEVFN(0,0);
2044 save_exclude = mv64x60_pci_exclude_bridge;
2045 mv64x60_pci_exclude_bridge = FALSE;
2047 /* Set class code to indicate host bridge */
2048 u16_val = PCI_CLASS_BRIDGE_HOST; /* 0x0600 (host bridge) */
2049 early_write_config_word(hose, 0, devfn, PCI_CLASS_DEVICE, u16_val);
2051 /* Enable 64260 to be PCI master & respond to PCI MEM cycles */
2052 early_read_config_word(hose, 0, devfn, PCI_COMMAND, &u16_val);
2053 u16_val &= ~(PCI_COMMAND_IO | PCI_COMMAND_INVALIDATE |
2054 PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
2055 u16_val |= pi->pci_cmd_bits | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
2056 early_write_config_word(hose, 0, devfn, PCI_COMMAND, u16_val);
2058 /* Set latency timer, cache line size, clear BIST */
2059 u16_val = (pi->latency_timer << 8) | (L1_CACHE_LINE_SIZE >> 2);
2060 early_write_config_word(hose, 0, devfn, PCI_CACHE_LINE_SIZE, u16_val);
2062 mv64x60_pci_exclude_bridge = save_exclude;
2067 *****************************************************************************
2069 * PCI Related Routine
2071 *****************************************************************************
2074 * mv64x60_enumerate_buses()
2076 * If requested, enumerate the PCI buses and set the appropriate
2077 * info in the hose structures.
2080 mv64x60_enumerate_buses(mv64x60_handle_t *bh, mv64x60_setup_info_t *si)
2084 pci_dram_offset = 0; /* System mem at same addr on PCI & cpu bus */
2086 ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
2087 ppc_md.pci_swizzle = common_swizzle;
2088 ppc_md.pci_map_irq = si->map_irq;
2090 /* Now that the bridge is set up, its safe to scan the PCI buses */
2091 if (si->pci_0.enable_bus) {
2092 if (si->pci_0.enumerate_bus) {
2093 /* Set bus number for PCI 0 to 0 */
2094 val = mv64x60_read(bh, MV64x60_PCI0_P2P_CONFIG);
2097 mv64x60_write(bh, MV64x60_PCI0_P2P_CONFIG, val);
2099 (void)mv64x60_read(bh, MV64x60_PCI0_P2P_CONFIG);
2102 XXXX Different if in PCI-X mode (look at mv64360_find_bridges()) XXXX
2105 bh->hose_a->first_busno = 0;
2106 bh->hose_a->last_busno = 0xff;
2108 bh->hose_a->last_busno = pciauto_bus_scan(bh->hose_a,
2109 bh->hose_a->first_busno);
2112 /* Assume bridge set up correctly by someone else */
2113 val = mv64x60_read(bh, MV64x60_PCI0_P2P_CONFIG);
2114 bh->hose_a->first_busno = (val & 0x00ff0000) >> 16;
2118 if (si->pci_1.enable_bus) {
2119 if (si->pci_1.enumerate_bus) {
2120 if (si->pci_0.enable_bus) {
2121 bh->hose_b->first_busno =
2122 bh->hose_a->last_busno + 1;
2124 /* Set bus number for PCI 1 hose */
2125 val = mv64x60_read(bh, MV64x60_PCI1_P2P_CONFIG);
2127 val |= (bh->hose_b->first_busno << 16) | 0xff;
2128 mv64x60_write(bh, MV64x60_PCI1_P2P_CONFIG, val);
2130 (void)mv64x60_read(bh, MV64x60_PCI1_P2P_CONFIG);
2133 bh->hose_b->first_busno = 0;
2136 bh->hose_b->last_busno = 0xff;
2137 bh->hose_b->last_busno = pciauto_bus_scan(bh->hose_b,
2138 bh->hose_b->first_busno);
2141 /* Assume bridge set up correctly by someone else */
2142 val = mv64x60_read(bh, MV64x60_PCI1_P2P_CONFIG);
2143 bh->hose_b->first_busno = (val & 0x00ff0000) >> 16;
2144 bh->hose_b->last_busno = 0xff; /* No way to know */
2148 if (si->pci_0.enable_bus && !si->pci_0.enumerate_bus) {
2149 if (si->pci_1.enable_bus) {
2150 bh->hose_a->last_busno = bh->hose_b->first_busno - 1;
2153 bh->hose_a->last_busno = 0xff; /* No way to know */
2161 * mv64x60_exclude_pci_device()
2163 * This routine is used to make the bridge not appear when the
2164 * PCI subsystem is accessing PCI devices (in PCI config space).
2167 mv64x60_pci_exclude_device(u8 bus, u8 devfn)
2169 struct pci_controller *hose;
2171 hose = pci_bus_to_hose(bus);
2173 /* Skip slot 0 on both hoses */
2174 if ((mv64x60_pci_exclude_bridge == TRUE) &&
2175 (PCI_SLOT(devfn) == 0) &&
2176 (hose->first_busno == bus)) {
2177 return PCIBIOS_DEVICE_NOT_FOUND;
2180 return PCIBIOS_SUCCESSFUL;
2182 } /* mv64x60_pci_exclude_device() */
2185 *****************************************************************************
2187 * OCP Fixup Routines
2189 *****************************************************************************
2192 * mv64x60_fixup_ocp()
2194 * Adjust the 'paddr' field in the bridge's OCP entries to reflect where they
2195 * really are in the physical address space.
2198 mv64x60_fixup_ocp(struct ocp_device *dev, void *arg)
2200 mv64x60_handle_t *bh = (mv64x60_handle_t *)arg;
2202 if (dev->def->vendor == OCP_VENDOR_MARVELL) {
2203 dev->def->paddr += bh->p_base;
2210 *****************************************************************************
2212 * GT64260-Specific Routines
2214 *****************************************************************************
2217 * gt64260_translate_size()
2219 * On the GT64260, the size register is really the "top" address of the window.
2222 gt64260_translate_size(u32 base, u32 size, u32 num_bits)
2224 return base + mv64x60_mask(size - 1, num_bits);
2228 * gt64260_untranslate_size()
2230 * Translate the top address of a window into a window size.
2233 gt64260_untranslate_size(u32 base, u32 size, u32 num_bits)
2236 size = size - base + (1 << (32 - num_bits));
2246 * gt64260_set_pci2mem_window()
2248 * The PCI->MEM window registers are actually in PCI config space so need
2249 * to set them by setting the correct config space BARs.
2252 gt64260_set_pci2mem_window(struct pci_controller *hose, u32 window, u32 base)
2254 u32 reg_addrs[] = { 0x10, 0x14, 0x18, 0x1c };
2256 DBG("set pci->mem window: %d, hose: %d, base: 0x%x\n", window,
2259 early_write_config_dword(hose, hose->first_busno,
2260 PCI_DEVFN(0, 0), reg_addrs[window],
2261 mv64x60_mask(base, 20) | 0x8);
2266 * gt64260_is_enabled_32bit()
2268 * On a GT64260, a window is enabled iff its top address is >= to its base
2272 gt64260_is_enabled_32bit(mv64x60_handle_t *bh, u32 window)
2276 if ((gt64260_32bit_windows[window].base_reg != 0) &&
2277 (gt64260_32bit_windows[window].size_reg != 0) &&
2278 ((mv64x60_read(bh, gt64260_32bit_windows[window].size_reg) &
2279 ((1 << gt64260_32bit_windows[window].size_bits) - 1)) >=
2280 (mv64x60_read(bh, gt64260_32bit_windows[window].base_reg) &
2281 ((1 << gt64260_32bit_windows[window].base_bits) - 1)))){
2287 DBG("32bit window %d is enabled\n", window);
2290 DBG("32bit window %d is disabled\n", window);
2297 * gt64260_enable_window_32bit()
2299 * On the GT64260, a window is enabled iff the top address is >= to the base
2300 * address of the window. Since the window has already been configured by
2301 * the time this routine is called, we have nothing to do here.
2304 gt64260_enable_window_32bit(mv64x60_handle_t *bh, u32 window)
2306 DBG("enable 32bit window: %d\n", window);
2311 * gt64260_disable_window_32bit()
2313 * On a GT64260, you disable a window by setting its top address to be less
2314 * than its base address.
2317 gt64260_disable_window_32bit(mv64x60_handle_t *bh, u32 window)
2319 DBG("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
2320 window, gt64260_32bit_windows[window].base_reg,
2321 gt64260_32bit_windows[window].size_reg);
2323 if ((gt64260_32bit_windows[window].base_reg != 0) &&
2324 (gt64260_32bit_windows[window].size_reg != 0)) {
2326 /* To disable, make bottom reg higher than top reg */
2327 mv64x60_write(bh, gt64260_32bit_windows[window].base_reg,0xfff);
2328 mv64x60_write(bh, gt64260_32bit_windows[window].size_reg, 0);
2335 * gt64260_enable_window_64bit()
2337 * On the GT64260, a window is enabled iff the top address is >= to the base
2338 * address of the window. Since the window has already been configured by
2339 * the time this routine is called, we have nothing to do here.
2342 gt64260_enable_window_64bit(mv64x60_handle_t *bh, u32 window)
2344 DBG("enable 64bit window: %d\n", window);
2345 return; /* Enabled when window configured (i.e., when top >= base) */
2349 * gt64260_disable_window_64bit()
2351 * On a GT64260, you disable a window by setting its top address to be less
2352 * than its base address.
2355 gt64260_disable_window_64bit(mv64x60_handle_t *bh, u32 window)
2357 DBG("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
2358 window, gt64260_64bit_windows[window].base_lo_reg,
2359 gt64260_64bit_windows[window].size_reg);
2361 if ((gt64260_64bit_windows[window].base_lo_reg != 0) &&
2362 (gt64260_64bit_windows[window].size_reg != 0)) {
2364 /* To disable, make bottom reg higher than top reg */
2365 mv64x60_write(bh, gt64260_64bit_windows[window].base_lo_reg,
2367 mv64x60_write(bh, gt64260_64bit_windows[window].base_hi_reg, 0);
2368 mv64x60_write(bh, gt64260_64bit_windows[window].size_reg, 0);
2375 * gt64260_disable_all_windows()
2377 * The GT64260 has several windows that aren't represented in the table of
2378 * windows at the top of this file. This routine turns all of them off
2379 * except for the memory controller windows, of course.
2382 gt64260_disable_all_windows(mv64x60_handle_t *bh, mv64x60_setup_info_t *si)
2386 /* Disable 32bit windows (don't disable cpu->mem windows) */
2387 for (i=MV64x60_CPU2DEV_0_WIN; i<MV64x60_32BIT_WIN_COUNT; i++) {
2388 if (!(si->window_preserve_mask_32 & (1<<i)))
2389 gt64260_disable_window_32bit(bh, i);
2392 /* Disable 64bit windows */
2393 for (i=0; i<MV64x60_64BIT_WIN_COUNT; i++) {
2394 if (!(si->window_preserve_mask_64 & (1<<i)))
2395 gt64260_disable_window_64bit(bh, i);
2398 /* Turn off cpu protection windows not in gt64260_32bit_windows[] */
2399 mv64x60_write(bh, GT64260_CPU_PROT_BASE_4, 0xfff);
2400 mv64x60_write(bh, GT64260_CPU_PROT_SIZE_4, 0);
2401 mv64x60_write(bh, GT64260_CPU_PROT_BASE_5, 0xfff);
2402 mv64x60_write(bh, GT64260_CPU_PROT_SIZE_5, 0);
2403 mv64x60_write(bh, GT64260_CPU_PROT_BASE_6, 0xfff);
2404 mv64x60_write(bh, GT64260_CPU_PROT_SIZE_6, 0);
2405 mv64x60_write(bh, GT64260_CPU_PROT_BASE_7, 0xfff);
2406 mv64x60_write(bh, GT64260_CPU_PROT_SIZE_7, 0);
2408 /* Turn off PCI->MEM access cntl wins not in gt64260_64bit_windows[] */
2409 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_LO, 0xfff);
2410 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_HI, 0);
2411 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_SIZE, 0);
2412 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_LO, 0xfff);
2413 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_HI, 0);
2414 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_SIZE, 0);
2415 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_BASE_LO, 0xfff);
2416 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_BASE_HI, 0);
2417 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_SIZE, 0);
2418 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_BASE_LO, 0xfff);
2419 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_BASE_HI, 0);
2420 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_SIZE, 0);
2422 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_LO, 0xfff);
2423 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_HI, 0);
2424 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_SIZE, 0);
2425 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_LO, 0xfff);
2426 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_HI, 0);
2427 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_SIZE, 0);
2428 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_BASE_LO, 0xfff);
2429 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_BASE_HI, 0);
2430 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_SIZE, 0);
2431 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_BASE_LO, 0xfff);
2432 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_BASE_HI, 0);
2433 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_SIZE, 0);
2435 /* Disable all PCI-><whatever> windows */
2436 mv64x60_set_bits(bh, MV64x60_PCI0_BAR_ENABLE, 0x07ffffff);
2437 mv64x60_set_bits(bh, MV64x60_PCI1_BAR_ENABLE, 0x07ffffff);
2443 * gt64260a_chip_specific_init()
2445 * Implement errata work arounds for the GT64260A.
2448 gt64260a_chip_specific_init(mv64x60_handle_t *bh, mv64x60_setup_info_t *si)
2450 struct ocp_device *dev;
2451 mv64x60_ocp_mpsc_data_t *mpsc_dp;
2456 /* cpu read buffer to buffer 1 (reg 0x0448) */
2457 mv64x60_set_bits(bh, GT64260_SDRAM_CONFIG, (1<<26));
2459 /* No longer errata so turn on */
2460 /* Enable pci read/write combine, master write trigger,
2461 * disable slave sync barrier
2462 * readmultiple (reg 0x0c00 and 0x0c80)
2464 if (si->pci_0.enable_bus) {
2465 mv64x60_set_bits(bh, MV64x60_PCI0_CMD,
2466 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
2469 if (si->pci_1.enable_bus) {
2470 mv64x60_set_bits(bh, MV64x60_PCI1_CMD,
2471 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
2476 * Dave Wilhardt found that bit 4 in the PCI Command registers must
2477 * be set if you are using cache coherency.
2479 * Note: he also said that bit 4 must be on in all PCI devices but
2480 * that has not been implemented yet.
2482 save_exclude = mv64x60_pci_exclude_bridge;
2483 mv64x60_pci_exclude_bridge = FALSE;
2485 early_read_config_dword(bh->hose_a,
2486 bh->hose_a->first_busno,
2490 val |= PCI_COMMAND_INVALIDATE;
2491 early_write_config_dword(bh->hose_a,
2492 bh->hose_a->first_busno,
2497 early_read_config_dword(bh->hose_b,
2498 bh->hose_b->first_busno,
2502 val |= PCI_COMMAND_INVALIDATE;
2503 early_write_config_dword(bh->hose_b,
2504 bh->hose_b->first_busno,
2509 mv64x60_pci_exclude_bridge = save_exclude;
2512 if ((dev = ocp_find_device(OCP_VENDOR_MARVELL, OCP_FUNC_MPSC, 0))
2514 mpsc_dp = (mv64x60_ocp_mpsc_data_t *)dev->def->additions;
2515 mpsc_dp->mirror_regs = 1;
2516 mpsc_dp->cache_mgmt = 1;
2519 if ((dev = ocp_find_device(OCP_VENDOR_MARVELL, OCP_FUNC_MPSC, 1))
2521 mpsc_dp = (mv64x60_ocp_mpsc_data_t *)dev->def->additions;
2522 mpsc_dp->mirror_regs = 1;
2523 mpsc_dp->cache_mgmt = 1;
2530 * gt64260b_chip_specific_init()
2532 * Implement errata work arounds for the GT64260B.
2535 gt64260b_chip_specific_init(mv64x60_handle_t *bh, mv64x60_setup_info_t *si)
2537 struct ocp_device *dev;
2538 mv64x60_ocp_mpsc_data_t *mpsc_dp;
2541 /* cpu read buffer to buffer 1 (reg 0x0448) */
2542 mv64x60_set_bits(bh, GT64260_SDRAM_CONFIG, (1<<26));
2544 /* No longer errata so turn on */
2545 /* Enable pci read/write combine, master write trigger,
2546 * disable slave sync barrier
2547 * readmultiple (reg 0x0c00 and 0x0c80)
2549 if (si->pci_0.enable_bus) {
2550 mv64x60_set_bits(bh, MV64x60_PCI0_CMD,
2551 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
2554 if (si->pci_1.enable_bus) {
2555 mv64x60_set_bits(bh, MV64x60_PCI1_CMD,
2556 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
2559 mv64x60_set_bits(bh, GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH, 0xf);
2562 * The 64260B is not supposed to have the bug where the MPSC & ENET
2563 * can't access cache coherent regions. However, testing has shown
2564 * that the MPSC, at least, still has this bug.
2566 if ((dev = ocp_find_device(OCP_VENDOR_MARVELL, OCP_FUNC_MPSC, 0))
2568 mpsc_dp = (mv64x60_ocp_mpsc_data_t *)dev->def->additions;
2569 mpsc_dp->cache_mgmt = 1;
2572 if ((dev = ocp_find_device(OCP_VENDOR_MARVELL, OCP_FUNC_MPSC, 1))
2574 mpsc_dp = (mv64x60_ocp_mpsc_data_t *)dev->def->additions;
2575 mpsc_dp->cache_mgmt = 1;
2582 *****************************************************************************
2584 * MV64360-Specific Routines
2586 *****************************************************************************
2589 * mv64360_translate_size()
2591 * On the MV64360, the size register is set similar to the size you get
2592 * from a pci config space BAR register. That is, programmed from LSB to MSB
2593 * as a sequence of 1's followed by a sequence of 0's. IOW, "size -1" with the
2594 * assumption that the size is a power of 2.
2597 mv64360_translate_size(u32 base_addr, u32 size, u32 num_bits)
2599 return mv64x60_mask(size - 1, num_bits);
2603 * mv64360_untranslate_size()
2605 * Translate the size register value of a window into a window size.
2608 mv64360_untranslate_size(u32 base_addr, u32 size, u32 num_bits)
2611 size >>= (32 - num_bits);
2613 size <<= (32 - num_bits);
2620 * mv64360_set_pci2mem_window()
2622 * The PCI->MEM window registers are actually in PCI config space so need
2623 * to set them by setting the correct config space BARs.
2626 mv64360_set_pci2mem_window(struct pci_controller *hose, u32 window, u32 base)
2632 } reg_addrs[] = {{ 0, 0x14, 0x10 }, { 0, 0x1c, 0x18 },
2633 { 1, 0x14, 0x10 }, { 1, 0x1c, 0x18 }};
2635 DBG("set pci->mem window: %d, hose: %d, base: 0x%x\n", window,
2638 early_write_config_dword(hose, hose->first_busno,
2639 PCI_DEVFN(0, reg_addrs[window].fcn),
2640 reg_addrs[window].base_hi_bar, 0);
2641 early_write_config_dword(hose, hose->first_busno,
2642 PCI_DEVFN(0, reg_addrs[window].fcn),
2643 reg_addrs[window].base_lo_bar,
2644 mv64x60_mask(base, 20) | 0xc);
2649 * mv64360_is_enabled_32bit()
2651 * On a MV64360, a window is enabled by either clearing a bit in the
2652 * CPU BAR Enable reg or setting a bit in the window's base reg.
2653 * Note that this doesn't work for windows on the PCI slave side but we don't
2654 * check those so its okay.
2657 mv64360_is_enabled_32bit(mv64x60_handle_t *bh, u32 window)
2661 if ((mv64360_32bit_windows[window].base_reg != 0) &&
2662 (mv64360_32bit_windows[window].size_reg != 0)) {
2664 if (mv64360_32bit_windows[window].extra & 0x80000000) {
2665 rc = (mv64x60_read(bh,
2666 mv64360_32bit_windows[window].base_reg) &
2667 (1 << (mv64360_32bit_windows[window].extra &
2671 rc = (mv64x60_read(bh, MV64360_CPU_BAR_ENABLE) &
2672 (1 << mv64360_32bit_windows[window].extra)) ==0;
2677 DBG("32bit window %d is enabled\n", window);
2680 DBG("32bit window %d is disabled\n", window);
2687 * mv64360_enable_window_32bit()
2689 * On a MV64360, a window is enabled by either clearing a bit in the
2690 * CPU BAR Enable reg or setting a bit in the window's base reg.
2693 mv64360_enable_window_32bit(mv64x60_handle_t *bh, u32 window)
2695 DBG("enable 32bit window: %d\n", window);
2697 if ((mv64360_32bit_windows[window].base_reg != 0) &&
2698 (mv64360_32bit_windows[window].size_reg != 0)) {
2700 if (mv64360_32bit_windows[window].extra & 0x80000000) {
2701 mv64x60_set_bits(bh,
2702 mv64360_32bit_windows[window].base_reg,
2703 (1 << (mv64360_32bit_windows[window].extra &
2707 mv64x60_clr_bits(bh, MV64360_CPU_BAR_ENABLE,
2708 (1 << mv64360_32bit_windows[window].extra));
2716 * mv64360_disable_window_32bit()
2718 * On a MV64360, a window is disabled by either setting a bit in the
2719 * CPU BAR Enable reg or clearing a bit in the window's base reg.
2722 mv64360_disable_window_32bit(mv64x60_handle_t *bh, u32 window)
2724 DBG("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
2725 window, mv64360_32bit_windows[window].base_reg,
2726 mv64360_32bit_windows[window].size_reg);
2728 if ((mv64360_32bit_windows[window].base_reg != 0) &&
2729 (mv64360_32bit_windows[window].size_reg != 0)) {
2731 if (mv64360_32bit_windows[window].extra & 0x80000000) {
2732 mv64x60_clr_bits(bh,
2733 mv64360_32bit_windows[window].base_reg,
2734 (1 << (mv64360_32bit_windows[window].extra &
2738 mv64x60_set_bits(bh, MV64360_CPU_BAR_ENABLE,
2739 (1 << mv64360_32bit_windows[window].extra));
2747 * mv64360_enable_window_64bit()
2749 * On the MV64360, a 64-bit window is enabled by setting a bit in the window's
2753 mv64360_enable_window_64bit(mv64x60_handle_t *bh, u32 window)
2755 DBG("enable 64bit window: %d\n", window);
2757 /* For 64360, 'extra' field holds bit that enables the window */
2758 if ((mv64360_64bit_windows[window].base_lo_reg!= 0) &&
2759 (mv64360_64bit_windows[window].size_reg != 0)) {
2761 if (mv64360_64bit_windows[window].extra & 0x80000000) {
2762 mv64x60_set_bits(bh,
2763 mv64360_64bit_windows[window].base_lo_reg,
2764 (1 << (mv64360_64bit_windows[window].extra &
2766 } /* Should be no 'else' ones */
2773 * mv64360_disable_window_64bit()
2775 * On a MV64360, a 64-bit window is disabled by clearing a bit in the window's
2779 mv64360_disable_window_64bit(mv64x60_handle_t *bh, u32 window)
2781 DBG("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
2782 window, mv64360_64bit_windows[window].base_lo_reg,
2783 mv64360_64bit_windows[window].size_reg);
2785 if ((mv64360_64bit_windows[window].base_lo_reg != 0) &&
2786 (mv64360_64bit_windows[window].size_reg != 0)) {
2788 if (mv64360_64bit_windows[window].extra & 0x80000000) {
2789 mv64x60_clr_bits(bh,
2790 mv64360_64bit_windows[window].base_lo_reg,
2791 (1 << (mv64360_64bit_windows[window].extra &
2793 } /* Should be no 'else' ones */
2800 * mv64360_disable_all_windows()
2802 * The MV64360 has a few windows that aren't represented in the table of
2803 * windows at the top of this file. This routine turns all of them off
2804 * except for the memory controller windows, of course.
2807 mv64360_disable_all_windows(mv64x60_handle_t *bh, mv64x60_setup_info_t *si)
2811 /* Disable 32bit windows (don't disable cpu->mem windows) */
2812 for (i=MV64x60_CPU2DEV_0_WIN; i<MV64x60_32BIT_WIN_COUNT; i++) {
2813 if (!(si->window_preserve_mask_32 & (1<<i)))
2814 mv64360_disable_window_32bit(bh, i);
2817 /* Disable 64bit windows */
2818 for (i=0; i<MV64x60_64BIT_WIN_COUNT; i++) {
2819 if (!(si->window_preserve_mask_64 & (1<<i)))
2820 mv64360_disable_window_64bit(bh, i);
2823 /* Turn off PCI->MEM access cntl wins not in mv64360_64bit_windows[] */
2824 mv64x60_clr_bits(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_LO, 0);
2825 mv64x60_clr_bits(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_LO, 0);
2826 mv64x60_clr_bits(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_LO, 0);
2827 mv64x60_clr_bits(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_LO, 0);
2829 /* Disable all PCI-><whatever> windows */
2830 mv64x60_set_bits(bh, MV64x60_PCI0_BAR_ENABLE, 0x0000f9ff);
2831 mv64x60_set_bits(bh, MV64x60_PCI1_BAR_ENABLE, 0x0000f9ff);
2837 * mv64360_chip_specific_init()
2839 * No errata work arounds for the MV64360 implemented at this point.
2842 mv64360_chip_specific_init(mv64x60_handle_t *bh, mv64x60_setup_info_t *si)
2844 struct ocp_device *dev;
2845 mv64x60_ocp_mpsc_data_t *mpsc_dp;
2847 if ((dev = ocp_find_device(OCP_VENDOR_MARVELL, OCP_FUNC_MPSC, 0))
2849 mpsc_dp = (mv64x60_ocp_mpsc_data_t *)dev->def->additions;
2850 mpsc_dp->brg_can_tune = 1;
2853 if ((dev = ocp_find_device(OCP_VENDOR_MARVELL, OCP_FUNC_MPSC, 1))
2855 mpsc_dp = (mv64x60_ocp_mpsc_data_t *)dev->def->additions;
2856 mpsc_dp->brg_can_tune = 1;
2863 * mv64460_chip_specific_init()
2865 * No errata work arounds for the MV64460 implemented at this point.
2868 mv64460_chip_specific_init(mv64x60_handle_t *bh, mv64x60_setup_info_t *si)
2870 mv64360_chip_specific_init(bh, si); /* XXXX check errata */