arch/ppc/syslib/open_pic.c

   1 /*
   2  *  arch/ppc/kernel/open_pic.c -- OpenPIC Interrupt Handling
   3  *
   4  *  Copyright (C) 1997 Geert Uytterhoeven
   5  *
   6  *  This file is subject to the terms and conditions of the GNU General Public
   7  *  License.  See the file COPYING in the main directory of this archive
   8  *  for more details.
   9  */
  10
  11 #include <linux/config.h>
  12 #include <linux/types.h>
  13 #include <linux/kernel.h>
  14 #include <linux/sched.h>
  15 #include <linux/init.h>
  16 #include <linux/irq.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/sysdev.h>
  19 #include <asm/ptrace.h>
  20 #include <asm/signal.h>
  21 #include <asm/io.h>
  22 #include <asm/irq.h>
  23 #include <asm/prom.h>
  24 #include <asm/sections.h>
  25 #include <asm/open_pic.h>
  26 #include <asm/i8259.h>
  27 #include <asm/hardirq.h>
  28
  29 #include "open_pic_defs.h"
  30
  31 #if defined(CONFIG_PRPMC800) || defined(CONFIG_85xx)
  32 #define OPENPIC_BIG_ENDIAN
  33 #endif
  34
  35 void* OpenPIC_Addr;
  36 static volatile struct OpenPIC *OpenPIC = NULL;
  37
  38 /*
  39  * We define OpenPIC_InitSenses table thusly:
  40  * bit 0x1: sense, 0 for edge and 1 for level.
  41  * bit 0x2: polarity, 0 for negative, 1 for positive.
  42  */
  43 u_int OpenPIC_NumInitSenses __initdata = 0;
  44 u_char *OpenPIC_InitSenses __initdata = NULL;
  45 extern int use_of_interrupt_tree;
  46
  47 static u_int NumProcessors;
  48 static u_int NumSources;
  49 static int open_pic_irq_offset;
  50 static volatile OpenPIC_Source *ISR[NR_IRQS];
  51 static int openpic_cascade_irq = -1;
  52 static int (*openpic_cascade_fn)(struct pt_regs *);
  53
  54 /* Global Operations */
  55 static void openpic_disable_8259_pass_through(void);
  56 static void openpic_set_priority(u_int pri);
  57 static void openpic_set_spurious(u_int vector);
  58
  59 #ifdef CONFIG_SMP
  60 /* Interprocessor Interrupts */
  61 static void openpic_initipi(u_int ipi, u_int pri, u_int vector);
  62 static irqreturn_t openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *);
  63 #endif
  64
  65 /* Timer Interrupts */
  66 static void openpic_inittimer(u_int timer, u_int pri, u_int vector);
  67 static void openpic_maptimer(u_int timer, cpumask_t cpumask);
  68
  69 /* Interrupt Sources */
  70 static void openpic_enable_irq(u_int irq);
  71 static void openpic_disable_irq(u_int irq);
  72 static void openpic_initirq(u_int irq, u_int pri, u_int vector, int polarity,
  73                             int is_level);
  74 static void openpic_mapirq(u_int irq, cpumask_t cpumask, cpumask_t keepmask);
  75
  76 /*
  77  * These functions are not used but the code is kept here
  78  * for completeness and future reference.
  79  */
  80 #ifdef notused
  81 static void openpic_enable_8259_pass_through(void);
  82 static u_int openpic_get_priority(void);
  83 static u_int openpic_get_spurious(void);
  84 static void openpic_set_sense(u_int irq, int sense);
  85 #endif /* notused */
  86
  87 /*
  88  * Description of the openpic for the higher-level irq code
  89  */
  90 static void openpic_end_irq(unsigned int irq_nr);
  91 static void openpic_ack_irq(unsigned int irq_nr);
  92 static void openpic_set_affinity(unsigned int irq_nr, cpumask_t cpumask);
  93
  94 struct hw_interrupt_type open_pic = {
  95         .typename       = " OpenPIC  ",
  96         .enable         = openpic_enable_irq,
  97         .disable        = openpic_disable_irq,
  98         .ack            = openpic_ack_irq,
  99         .end            = openpic_end_irq,
 100         .set_affinity   = openpic_set_affinity,
 101 };
 102
 103 #ifdef CONFIG_SMP
 104 static void openpic_end_ipi(unsigned int irq_nr);
 105 static void openpic_ack_ipi(unsigned int irq_nr);
 106 static void openpic_enable_ipi(unsigned int irq_nr);
 107 static void openpic_disable_ipi(unsigned int irq_nr);
 108
 109 struct hw_interrupt_type open_pic_ipi = {
 110         .typename       = " OpenPIC  ",
 111         .enable         = openpic_enable_ipi,
 112         .disable        = openpic_disable_ipi,
 113         .ack            = openpic_ack_ipi,
 114         .end            = openpic_end_ipi,
 115 };
 116 #endif /* CONFIG_SMP */
 117
 118 /*
 119  *  Accesses to the current processor's openpic registers
 120  */
 121 #ifdef CONFIG_SMP
 122 #define THIS_CPU                Processor[cpu]
 123 #define DECL_THIS_CPU           int cpu = smp_hw_index[smp_processor_id()]
 124 #define CHECK_THIS_CPU          check_arg_cpu(cpu)
 125 #else
 126 #define THIS_CPU                Processor[0]
 127 #define DECL_THIS_CPU
 128 #define CHECK_THIS_CPU
 129 #endif /* CONFIG_SMP */
 130
 131 #if 1
 132 #define check_arg_ipi(ipi) \
 133     if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \
 134         printk("open_pic.c:%d: invalid ipi %d\n", __LINE__, ipi);
 135 #define check_arg_timer(timer) \
 136     if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \
 137         printk("open_pic.c:%d: invalid timer %d\n", __LINE__, timer);
 138 #define check_arg_vec(vec) \
 139     if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \
 140         printk("open_pic.c:%d: invalid vector %d\n", __LINE__, vec);
 141 #define check_arg_pri(pri) \
 142     if (pri < 0 || pri >= OPENPIC_NUM_PRI) \
 143         printk("open_pic.c:%d: invalid priority %d\n", __LINE__, pri);
 144 /*
 145  * Print out a backtrace if it's out of range, since if it's larger than NR_IRQ's
 146  * data has probably been corrupted and we're going to panic or deadlock later
 147  * anyway --Troy
 148  */
 149 #define check_arg_irq(irq) \
 150     if (irq < open_pic_irq_offset || irq >= NumSources+open_pic_irq_offset \
 151         || ISR[irq - open_pic_irq_offset] == 0) { \
 152       printk("open_pic.c:%d: invalid irq %d\n", __LINE__, irq); \
 153       dump_stack(); }
 154 #define check_arg_cpu(cpu) \
 155     if (cpu < 0 || cpu >= NumProcessors){ \
 156         printk("open_pic.c:%d: invalid cpu %d\n", __LINE__, cpu); \
 157         dump_stack(); }
 158 #else
 159 #define check_arg_ipi(ipi)      do {} while (0)
 160 #define check_arg_timer(timer)  do {} while (0)
 161 #define check_arg_vec(vec)      do {} while (0)
 162 #define check_arg_pri(pri)      do {} while (0)
 163 #define check_arg_irq(irq)      do {} while (0)
 164 #define check_arg_cpu(cpu)      do {} while (0)
 165 #endif
 166
 167 u_int openpic_read(volatile u_int *addr)
 168 {
 169         u_int val;
 170
 171 #ifdef OPENPIC_BIG_ENDIAN
 172         val = in_be32(addr);
 173 #else
 174         val = in_le32(addr);
 175 #endif
 176         return val;
 177 }
 178
 179 static inline void openpic_write(volatile u_int *addr, u_int val)
 180 {
 181 #ifdef OPENPIC_BIG_ENDIAN
 182         out_be32(addr, val);
 183 #else
 184         out_le32(addr, val);
 185 #endif
 186 }
 187
 188 static inline u_int openpic_readfield(volatile u_int *addr, u_int mask)
 189 {
 190         u_int val = openpic_read(addr);
 191         return val & mask;
 192 }
 193
 194 inline void openpic_writefield(volatile u_int *addr, u_int mask,
 195                                u_int field)
 196 {
 197         u_int val = openpic_read(addr);
 198         openpic_write(addr, (val & ~mask) | (field & mask));
 199 }
 200
 201 static inline void openpic_clearfield(volatile u_int *addr, u_int mask)
 202 {
 203         openpic_writefield(addr, mask, 0);
 204 }
 205
 206 static inline void openpic_setfield(volatile u_int *addr, u_int mask)
 207 {
 208         openpic_writefield(addr, mask, mask);
 209 }
 210
 211 static void openpic_safe_writefield(volatile u_int *addr, u_int mask,
 212                                     u_int field)
 213 {
 214         openpic_setfield(addr, OPENPIC_MASK);
 215         while (openpic_read(addr) & OPENPIC_ACTIVITY);
 216         openpic_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
 217 }
 218
 219 #ifdef CONFIG_SMP
 220 /* yes this is right ... bug, feature, you decide! -- tgall */
 221 u_int openpic_read_IPI(volatile u_int* addr)
 222 {
 223          u_int val = 0;
 224 #if defined(OPENPIC_BIG_ENDIAN) || defined(CONFIG_POWER3)
 225         val = in_be32(addr);
 226 #else
 227         val = in_le32(addr);
 228 #endif
 229         return val;
 230 }
 231
 232 /* because of the power3 be / le above, this is needed */
 233 inline void openpic_writefield_IPI(volatile u_int* addr, u_int mask, u_int field)
 234 {
 235         u_int  val = openpic_read_IPI(addr);
 236         openpic_write(addr, (val & ~mask) | (field & mask));
 237 }
 238
 239 static inline void openpic_clearfield_IPI(volatile u_int *addr, u_int mask)
 240 {
 241         openpic_writefield_IPI(addr, mask, 0);
 242 }
 243
 244 static inline void openpic_setfield_IPI(volatile u_int *addr, u_int mask)
 245 {
 246         openpic_writefield_IPI(addr, mask, mask);
 247 }
 248
 249 static void openpic_safe_writefield_IPI(volatile u_int *addr, u_int mask, u_int field)
 250 {
 251         openpic_setfield_IPI(addr, OPENPIC_MASK);
 252
 253         /* wait until it's not in use */
 254         /* BenH: Is this code really enough ? I would rather check the result
 255          *       and eventually retry ...
 256          */
 257         while(openpic_read_IPI(addr) & OPENPIC_ACTIVITY);
 258
 259         openpic_writefield_IPI(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
 260 }
 261 #endif /* CONFIG_SMP */
 262
 263 #ifdef CONFIG_EPIC_SERIAL_MODE
 264 static void __init openpic_eicr_set_clk(u_int clkval)
 265 {
 266         openpic_writefield(&OpenPIC->Global.Global_Configuration1,
 267                         OPENPIC_EICR_S_CLK_MASK, (clkval << 28));
 268 }
 269
 270 static void __init openpic_enable_sie(void)
 271 {
 272         openpic_setfield(&OpenPIC->Global.Global_Configuration1,
 273                         OPENPIC_EICR_SIE);
 274 }
 275 #endif
 276
 277 #if defined(CONFIG_EPIC_SERIAL_MODE) || defined(CONFIG_PM)
 278 static void openpic_reset(void)
 279 {
 280         openpic_setfield(&OpenPIC->Global.Global_Configuration0,
 281                          OPENPIC_CONFIG_RESET);
 282         while (openpic_readfield(&OpenPIC->Global.Global_Configuration0,
 283                                  OPENPIC_CONFIG_RESET))
 284                 mb();
 285 }
 286 #endif
 287
 288 void __init openpic_set_sources(int first_irq, int num_irqs, void *first_ISR)
 289 {
 290         volatile OpenPIC_Source *src = first_ISR;
 291         int i, last_irq;
 292
 293         last_irq = first_irq + num_irqs;
 294         if (last_irq > NumSources)
 295                 NumSources = last_irq;
 296         if (src == 0)
 297                 src = &((struct OpenPIC *)OpenPIC_Addr)->Source[first_irq];
 298         for (i = first_irq; i < last_irq; ++i, ++src)
 299                 ISR[i] = src;
 300 }
 301
 302 /*
 303  * The `offset' parameter defines where the interrupts handled by the
 304  * OpenPIC start in the space of interrupt numbers that the kernel knows
 305  * about.  In other words, the OpenPIC's IRQ0 is numbered `offset' in the
 306  * kernel's interrupt numbering scheme.
 307  * We assume there is only one OpenPIC.
 308  */
 309 void __init openpic_init(int offset)
 310 {
 311         u_int t, i;
 312         u_int timerfreq;
 313         const char *version;
 314
 315         if (!OpenPIC_Addr) {
 316                 printk("No OpenPIC found !\n");
 317                 return;
 318         }
 319         OpenPIC = (volatile struct OpenPIC *)OpenPIC_Addr;
 320
 321 #ifdef CONFIG_EPIC_SERIAL_MODE
 322         /* Have to start from ground zero.
 323         */
 324         openpic_reset();
 325 #endif
 326
 327         if (ppc_md.progress) ppc_md.progress("openpic: enter", 0x122);
 328
 329         t = openpic_read(&OpenPIC->Global.Feature_Reporting0);
 330         switch (t & OPENPIC_FEATURE_VERSION_MASK) {
 331         case 1:
 332                 version = "1.0";
 333                 break;
 334         case 2:
 335                 version = "1.2";
 336                 break;
 337         case 3:
 338                 version = "1.3";
 339                 break;
 340         default:
 341                 version = "?";
 342                 break;
 343         }
 344         NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >>
 345                          OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1;
 346         if (NumSources == 0)
 347                 openpic_set_sources(0,
 348                                     ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >>
 349                                      OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1,
 350                                     NULL);
 351         printk("OpenPIC Version %s (%d CPUs and %d IRQ sources) at %p\n",
 352                version, NumProcessors, NumSources, OpenPIC);
 353         timerfreq = openpic_read(&OpenPIC->Global.Timer_Frequency);
 354         if (timerfreq)
 355                 printk("OpenPIC timer frequency is %d.%06d MHz\n",
 356                        timerfreq / 1000000, timerfreq % 1000000);
 357
 358         open_pic_irq_offset = offset;
 359
 360         /* Initialize timer interrupts */
 361         if ( ppc_md.progress ) ppc_md.progress("openpic: timer",0x3ba);
 362         for (i = 0; i < OPENPIC_NUM_TIMERS; i++) {
 363                 /* Disabled, Priority 0 */
 364                 openpic_inittimer(i, 0, OPENPIC_VEC_TIMER+i+offset);
 365                 /* No processor */
 366                 openpic_maptimer(i, CPU_MASK_NONE);
 367         }
 368
 369 #ifdef CONFIG_SMP
 370         /* Initialize IPI interrupts */
 371         if ( ppc_md.progress ) ppc_md.progress("openpic: ipi",0x3bb);
 372         for (i = 0; i < OPENPIC_NUM_IPI; i++) {
 373                 /* Disabled, Priority 10..13 */
 374                 openpic_initipi(i, 10+i, OPENPIC_VEC_IPI+i+offset);
 375                 /* IPIs are per-CPU */
 376                 irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU;
 377                 irq_desc[OPENPIC_VEC_IPI+i+offset].handler = &open_pic_ipi;
 378         }
 379 #endif
 380
 381         /* Initialize external interrupts */
 382         if (ppc_md.progress) ppc_md.progress("openpic: external",0x3bc);
 383
 384         openpic_set_priority(0xf);
 385
 386         /* Init all external sources, including possibly the cascade. */
 387         for (i = 0; i < NumSources; i++) {
 388                 int sense;
 389
 390                 if (ISR[i] == 0)
 391                         continue;
 392
 393                 /* the bootloader may have left it enabled (bad !) */
 394                 openpic_disable_irq(i+offset);
 395
 396                 sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: \
 397                                 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE);
 398
 399                 if (sense & IRQ_SENSE_MASK)
 400                         irq_desc[i+offset].status = IRQ_LEVEL;
 401
 402                 /* Enabled, Priority 8 */
 403                 openpic_initirq(i, 8, i+offset, (sense & IRQ_POLARITY_MASK),
 404                                 (sense & IRQ_SENSE_MASK));
 405                 /* Processor 0 */
 406                 openpic_mapirq(i, CPU_MASK_CPU0, CPU_MASK_NONE);
 407         }
 408
 409         /* Init descriptors */
 410         for (i = offset; i < NumSources + offset; i++)
 411                 irq_desc[i].handler = &open_pic;
 412
 413         /* Initialize the spurious interrupt */
 414         if (ppc_md.progress) ppc_md.progress("openpic: spurious",0x3bd);
 415         openpic_set_spurious(OPENPIC_VEC_SPURIOUS+offset);
 416         openpic_disable_8259_pass_through();
 417 #ifdef CONFIG_EPIC_SERIAL_MODE
 418         openpic_eicr_set_clk(7);        /* Slowest value until we know better */
 419         openpic_enable_sie();
 420 #endif
 421         openpic_set_priority(0);
 422
 423         if (ppc_md.progress) ppc_md.progress("openpic: exit",0x222);
 424 }
 425
 426 #ifdef notused
 427 static void openpic_enable_8259_pass_through(void)
 428 {
 429         openpic_clearfield(&OpenPIC->Global.Global_Configuration0,
 430                            OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
 431 }
 432 #endif /* notused */
 433
 434 static void openpic_disable_8259_pass_through(void)
 435 {
 436         openpic_setfield(&OpenPIC->Global.Global_Configuration0,
 437                          OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
 438 }
 439
 440 /*
 441  *  Find out the current interrupt
 442  */
 443 u_int openpic_irq(void)
 444 {
 445         u_int vec;
 446         DECL_THIS_CPU;
 447
 448         CHECK_THIS_CPU;
 449         vec = openpic_readfield(&OpenPIC->THIS_CPU.Interrupt_Acknowledge,
 450                                 OPENPIC_VECTOR_MASK);
 451         return vec;
 452 }
 453
 454 void openpic_eoi(void)
 455 {
 456         DECL_THIS_CPU;
 457
 458         CHECK_THIS_CPU;
 459         openpic_write(&OpenPIC->THIS_CPU.EOI, 0);
 460         /* Handle PCI write posting */
 461         (void)openpic_read(&OpenPIC->THIS_CPU.EOI);
 462 }
 463
 464 #ifdef notused
 465 static u_int openpic_get_priority(void)
 466 {
 467         DECL_THIS_CPU;
 468
 469         CHECK_THIS_CPU;
 470         return openpic_readfield(&OpenPIC->THIS_CPU.Current_Task_Priority,
 471                                  OPENPIC_CURRENT_TASK_PRIORITY_MASK);
 472 }
 473 #endif /* notused */
 474
 475 static void __init openpic_set_priority(u_int pri)
 476 {
 477         DECL_THIS_CPU;
 478
 479         CHECK_THIS_CPU;
 480         check_arg_pri(pri);
 481         openpic_writefield(&OpenPIC->THIS_CPU.Current_Task_Priority,
 482                            OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri);
 483 }
 484
 485 /*
 486  *  Get/set the spurious vector
 487  */
 488 #ifdef notused
 489 static u_int openpic_get_spurious(void)
 490 {
 491         return openpic_readfield(&OpenPIC->Global.Spurious_Vector,
 492                                  OPENPIC_VECTOR_MASK);
 493 }
 494 #endif /* notused */
 495
 496 static void openpic_set_spurious(u_int vec)
 497 {
 498         check_arg_vec(vec);
 499         openpic_writefield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK,
 500                            vec);
 501 }
 502
 503 #ifdef CONFIG_SMP
 504 /*
 505  * Convert a cpu mask from logical to physical cpu numbers.
 506  */
 507 static inline cpumask_t physmask(cpumask_t cpumask)
 508 {
 509         int i;
 510         cpumask_t mask = CPU_MASK_NONE;
 511
 512         cpus_and(cpumask, cpu_online_map, cpumask);
 513
 514         for (i = 0; i < NR_CPUS; i++)
 515                 if (cpu_isset(i, cpumask))
 516                         cpu_set(smp_hw_index[i], mask);
 517
 518         return mask;
 519 }
 520 #else
 521 #define physmask(cpumask)       (cpumask)
 522 #endif
 523
 524 void openpic_reset_processor_phys(u_int mask)
 525 {
 526         openpic_write(&OpenPIC->Global.Processor_Initialization, mask);
 527 }
 528
 529 #if defined(CONFIG_SMP) || defined(CONFIG_PM)
 530 static spinlock_t openpic_setup_lock = SPIN_LOCK_UNLOCKED;
 531 #endif
 532
 533 #ifdef CONFIG_SMP
 534 /*
 535  *  Initialize an interprocessor interrupt (and disable it)
 536  *
 537  *  ipi: OpenPIC interprocessor interrupt number
 538  *  pri: interrupt source priority
 539  *  vec: the vector it will produce
 540  */
 541 static void __init openpic_initipi(u_int ipi, u_int pri, u_int vec)
 542 {
 543         check_arg_ipi(ipi);
 544         check_arg_pri(pri);
 545         check_arg_vec(vec);
 546         openpic_safe_writefield_IPI(&OpenPIC->Global.IPI_Vector_Priority(ipi),
 547                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
 548                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
 549 }
 550
 551 /*
 552  *  Send an IPI to one or more CPUs
 553  *
 554  *  Externally called, however, it takes an IPI number (0...OPENPIC_NUM_IPI)
 555  *  and not a system-wide interrupt number
 556  */
 557 void openpic_cause_IPI(u_int ipi, u_int cpumask)
 558 {
 559         DECL_THIS_CPU;
 560
 561         CHECK_THIS_CPU;
 562         check_arg_ipi(ipi);
 563         openpic_write(&OpenPIC->THIS_CPU.IPI_Dispatch(ipi),
 564                       physmask(cpumask));
 565 }
 566
 567 void openpic_request_IPIs(void)
 568 {
 569         int i;
 570
 571         /*
 572          * Make sure this matches what is defined in smp.c for
 573          * smp_message_{pass|recv}() or what shows up in
 574          * /proc/interrupts will be wrong!!! --Troy */
 575
 576         if (OpenPIC == NULL)
 577                 return;
 578
 579         /* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */
 580         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset,
 581                     openpic_ipi_action, SA_INTERRUPT,
 582                     "IPI0 (call function)", 0);
 583         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+1,
 584                     openpic_ipi_action, SA_INTERRUPT,
 585                     "IPI1 (reschedule)", 0);
 586         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+2,
 587                     openpic_ipi_action, SA_INTERRUPT,
 588                     "IPI2 (invalidate tlb)", 0);
 589         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+3,
 590                     openpic_ipi_action, SA_INTERRUPT,
 591                     "IPI3 (xmon break)", 0);
 592
 593         for ( i = 0; i < OPENPIC_NUM_IPI ; i++ )
 594                 openpic_enable_ipi(OPENPIC_VEC_IPI+open_pic_irq_offset+i);
 595 }
 596
 597 /*
 598  * Do per-cpu setup for SMP systems.
 599  *
 600  * Get IPI's working and start taking interrupts.
 601  *   -- Cort
 602  */
 603
 604 void __devinit do_openpic_setup_cpu(void)
 605 {
 606 #ifdef CONFIG_IRQ_ALL_CPUS
 607         int i;
 608         cpumask_t msk = CPU_MASK_NONE;
 609 #endif
 610         spin_lock(&openpic_setup_lock);
 611
 612 #ifdef CONFIG_IRQ_ALL_CPUS
 613         cpu_set(smp_hw_index[smp_processor_id()], mask);
 614
 615         /* let the openpic know we want intrs. default affinity
 616          * is 0xffffffff until changed via /proc
 617          * That's how it's done on x86. If we want it differently, then
 618          * we should make sure we also change the default values of irq_affinity
 619          * in irq.c.
 620          */
 621         for (i = 0; i < NumSources; i++)
 622                 openpic_mapirq(i, msk, CPU_MASK_ALL);
 623 #endif /* CONFIG_IRQ_ALL_CPUS */
 624         openpic_set_priority(0);
 625
 626         spin_unlock(&openpic_setup_lock);
 627 }
 628 #endif /* CONFIG_SMP */
 629
 630 /*
 631  *  Initialize a timer interrupt (and disable it)
 632  *
 633  *  timer: OpenPIC timer number
 634  *  pri: interrupt source priority
 635  *  vec: the vector it will produce
 636  */
 637 static void __init openpic_inittimer(u_int timer, u_int pri, u_int vec)
 638 {
 639         check_arg_timer(timer);
 640         check_arg_pri(pri);
 641         check_arg_vec(vec);
 642         openpic_safe_writefield(&OpenPIC->Global.Timer[timer].Vector_Priority,
 643                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
 644                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
 645 }
 646
 647 /*
 648  *  Map a timer interrupt to one or more CPUs
 649  */
 650 static void __init openpic_maptimer(u_int timer, cpumask_t cpumask)
 651 {
 652         cpumask_t phys = physmask(cpumask);
 653         check_arg_timer(timer);
 654         openpic_write(&OpenPIC->Global.Timer[timer].Destination,
 655                       cpus_addr(phys)[0]);
 656 }
 657
 658 /*
 659  * Initalize the interrupt source which will generate an NMI.
 660  * This raises the interrupt's priority from 8 to 9.
 661  *
 662  * irq: The logical IRQ which generates an NMI.
 663  */
 664 void __init
 665 openpic_init_nmi_irq(u_int irq)
 666 {
 667         check_arg_irq(irq);
 668         openpic_safe_writefield(&ISR[irq - open_pic_irq_offset]->Vector_Priority,
 669                                 OPENPIC_PRIORITY_MASK,
 670                                 9 << OPENPIC_PRIORITY_SHIFT);
 671 }
 672
 673 /*
 674  *
 675  * All functions below take an offset'ed irq argument
 676  *
 677  */
 678
 679 /*
 680  * Hookup a cascade to the OpenPIC.
 681  */
 682 void __init
 683 openpic_hookup_cascade(u_int irq, char *name,
 684         int (*cascade_fn)(struct pt_regs *))
 685 {
 686         openpic_cascade_irq = irq;
 687         openpic_cascade_fn = cascade_fn;
 688         if (request_irq(irq, no_action, SA_INTERRUPT, name, NULL))
 689                 printk("Unable to get OpenPIC IRQ %d for cascade\n",
 690                                 irq - open_pic_irq_offset);
 691 }
 692
 693 /*
 694  *  Enable/disable an external interrupt source
 695  *
 696  *  Externally called, irq is an offseted system-wide interrupt number
 697  */
 698 static void openpic_enable_irq(u_int irq)
 699 {
 700         volatile u_int *vpp;
 701
 702         check_arg_irq(irq);
 703         vpp = &ISR[irq - open_pic_irq_offset]->Vector_Priority;
 704         openpic_clearfield(vpp, OPENPIC_MASK);
 705         /* make sure mask gets to controller before we return to user */
 706         do {
 707                 mb(); /* sync is probably useless here */
 708         } while (openpic_readfield(vpp, OPENPIC_MASK));
 709 }
 710
 711 static void openpic_disable_irq(u_int irq)
 712 {
 713         volatile u_int *vpp;
 714         u32 vp;
 715
 716         check_arg_irq(irq);
 717         vpp = &ISR[irq - open_pic_irq_offset]->Vector_Priority;
 718         openpic_setfield(vpp, OPENPIC_MASK);
 719         /* make sure mask gets to controller before we return to user */
 720         do {
 721                 mb();  /* sync is probably useless here */
 722                 vp = openpic_readfield(vpp, OPENPIC_MASK | OPENPIC_ACTIVITY);
 723         } while((vp & OPENPIC_ACTIVITY) && !(vp & OPENPIC_MASK));
 724 }
 725
 726 #ifdef CONFIG_SMP
 727 /*
 728  *  Enable/disable an IPI interrupt source
 729  *
 730  *  Externally called, irq is an offseted system-wide interrupt number
 731  */
 732 void openpic_enable_ipi(u_int irq)
 733 {
 734         irq -= (OPENPIC_VEC_IPI+open_pic_irq_offset);
 735         check_arg_ipi(irq);
 736         openpic_clearfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK);
 737
 738 }
 739
 740 void openpic_disable_ipi(u_int irq)
 741 {
 742         irq -= (OPENPIC_VEC_IPI+open_pic_irq_offset);
 743         check_arg_ipi(irq);
 744         openpic_setfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK);
 745 }
 746 #endif
 747
 748 /*
 749  *  Initialize an interrupt source (and disable it!)
 750  *
 751  *  irq: OpenPIC interrupt number
 752  *  pri: interrupt source priority
 753  *  vec: the vector it will produce
 754  *  pol: polarity (1 for positive, 0 for negative)
 755  *  sense: 1 for level, 0 for edge
 756  */
 757 static void __init
 758 openpic_initirq(u_int irq, u_int pri, u_int vec, int pol, int sense)
 759 {
 760         openpic_safe_writefield(&ISR[irq]->Vector_Priority,
 761                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
 762                                 OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK,
 763                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec |
 764                                 (pol ? OPENPIC_POLARITY_POSITIVE :
 765                                         OPENPIC_POLARITY_NEGATIVE) |
 766                                 (sense ? OPENPIC_SENSE_LEVEL : OPENPIC_SENSE_EDGE));
 767 }
 768
 769 /*
 770  *  Map an interrupt source to one or more CPUs
 771  */
 772 static void openpic_mapirq(u_int irq, cpumask_t physmask, cpumask_t keepmask)
 773 {
 774         if (ISR[irq] == 0)
 775                 return;
 776         if (!cpus_empty(keepmask)) {
 777                 cpumask_t irqdest = { .bits[0] = openpic_read(&ISR[irq]->Destination) };
 778                 cpus_and(irqdest, irqdest, keepmask);
 779                 cpus_or(physmask, physmask, irqdest);
 780         }
 781         openpic_write(&ISR[irq]->Destination, cpus_addr(physmask)[0]);
 782 }
 783
 784 #ifdef notused
 785 /*
 786  *  Set the sense for an interrupt source (and disable it!)
 787  *
 788  *  sense: 1 for level, 0 for edge
 789  */
 790 static void openpic_set_sense(u_int irq, int sense)
 791 {
 792         if (ISR[irq] != 0)
 793                 openpic_safe_writefield(&ISR[irq]->Vector_Priority,
 794                                         OPENPIC_SENSE_LEVEL,
 795                                         (sense ? OPENPIC_SENSE_LEVEL : 0));
 796 }
 797 #endif /* notused */
 798
 799 /* No spinlocks, should not be necessary with the OpenPIC
 800  * (1 register = 1 interrupt and we have the desc lock).
 801  */
 802 static void openpic_ack_irq(unsigned int irq_nr)
 803 {
 804 #ifdef __SLOW_VERSION__
 805         openpic_disable_irq(irq_nr);
 806         openpic_eoi();
 807 #else
 808         if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0)
 809                 openpic_eoi();
 810 #endif
 811 }
 812
 813 static void openpic_end_irq(unsigned int irq_nr)
 814 {
 815 #ifdef __SLOW_VERSION__
 816         if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
 817             && irq_desc[irq_nr].action)
 818                 openpic_enable_irq(irq_nr);
 819 #else
 820         if ((irq_desc[irq_nr].status & IRQ_LEVEL) != 0)
 821                 openpic_eoi();
 822 #endif
 823 }
 824
 825 static void openpic_set_affinity(unsigned int irq_nr, cpumask_t cpumask)
 826 {
 827         openpic_mapirq(irq_nr - open_pic_irq_offset, physmask(cpumask), CPU_MASK_NONE);
 828 }
 829
 830 #ifdef CONFIG_SMP
 831 static void openpic_ack_ipi(unsigned int irq_nr)
 832 {
 833         openpic_eoi();
 834 }
 835
 836 static void openpic_end_ipi(unsigned int irq_nr)
 837 {
 838 }
 839
 840 static irqreturn_t openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *regs)
 841 {
 842         smp_message_recv(cpl-OPENPIC_VEC_IPI-open_pic_irq_offset, regs);
 843         return IRQ_HANDLED;
 844 }
 845
 846 #endif /* CONFIG_SMP */
 847
 848 int
 849 openpic_get_irq(struct pt_regs *regs)
 850 {
 851         int irq = openpic_irq();
 852
 853         /*
 854          * Check for the cascade interrupt and call the cascaded
 855          * interrupt controller function (usually i8259_irq) if so.
 856          * This should move to irq.c eventually.  -- paulus
 857          */
 858         if (irq == openpic_cascade_irq && openpic_cascade_fn != NULL) {
 859                 int cirq = openpic_cascade_fn(regs);
 860
 861                 /* Allow for the cascade being shared with other devices */
 862                 if (cirq != -1) {
 863                         irq = cirq;
 864                         openpic_eoi();
 865                 }
 866         } else if (irq == OPENPIC_VEC_SPURIOUS + open_pic_irq_offset)
 867                 irq = -1;
 868         return irq;
 869 }
 870
 871 #ifdef CONFIG_SMP
 872 void
 873 smp_openpic_message_pass(int target, int msg, unsigned long data, int wait)
 874 {
 875         /* make sure we're sending something that translates to an IPI */
 876         if (msg > 0x3) {
 877                 printk("SMP %d: smp_message_pass: unknown msg %d\n",
 878                        smp_processor_id(), msg);
 879                 return;
 880         }
 881         switch (target) {
 882         case MSG_ALL:
 883                 openpic_cause_IPI(msg, 0xffffffff);
 884                 break;
 885         case MSG_ALL_BUT_SELF:
 886                 openpic_cause_IPI(msg,
 887                                   0xffffffff & ~(1 << smp_processor_id()));
 888                 break;
 889         default:
 890                 openpic_cause_IPI(msg, 1<<target);
 891                 break;
 892         }
 893 }
 894 #endif /* CONFIG_SMP */
 895
 896 #ifdef CONFIG_PM
 897
 898 /*
 899  * We implement the IRQ controller as a sysdev and put it
 900  * to sleep at powerdown stage (the callback is named suspend,
 901  * but it's old semantics, for the Device Model, it's really
 902  * powerdown). The possible problem is that another sysdev that
 903  * happens to be suspend after this one will have interrupts off,
 904  * that may be an issue... For now, this isn't an issue on pmac
 905  * though...
 906  */
 907
 908 static u32 save_ipi_vp[OPENPIC_NUM_IPI];
 909 static u32 save_irq_src_vp[OPENPIC_MAX_SOURCES];
 910 static u32 save_irq_src_dest[OPENPIC_MAX_SOURCES];
 911 static u32 save_cpu_task_pri[OPENPIC_MAX_PROCESSORS];
 912 static int openpic_suspend_count;
 913
 914 static void openpic_cached_enable_irq(u_int irq)
 915 {
 916         check_arg_irq(irq);
 917         save_irq_src_vp[irq - open_pic_irq_offset] &= ~OPENPIC_MASK;
 918 }
 919
 920 static void openpic_cached_disable_irq(u_int irq)
 921 {
 922         check_arg_irq(irq);
 923         save_irq_src_vp[irq - open_pic_irq_offset] |= OPENPIC_MASK;
 924 }
 925
 926 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
 927  * we need something better to deal with that... Maybe switch to S1 for
 928  * cpufreq changes
 929  */
 930 int openpic_suspend(struct sys_device *sysdev, u32 state)
 931 {
 932         int     i;
 933         unsigned long flags;
 934
 935         spin_lock_irqsave(&openpic_setup_lock, flags);
 936
 937         if (openpic_suspend_count++ > 0) {
 938                 spin_unlock_irqrestore(&openpic_setup_lock, flags);
 939                 return 0;
 940         }
 941
 942         open_pic.enable = openpic_cached_enable_irq;
 943         open_pic.disable = openpic_cached_disable_irq;
 944
 945         for (i=0; i<NumProcessors; i++) {
 946                 save_cpu_task_pri[i] = openpic_read(&OpenPIC->Processor[i].Current_Task_Priority);
 947                 openpic_writefield(&OpenPIC->Processor[i].Current_Task_Priority,
 948                                    OPENPIC_CURRENT_TASK_PRIORITY_MASK, 0xf);
 949         }
 950
 951         for (i=0; i<OPENPIC_NUM_IPI; i++)
 952                 save_ipi_vp[i] = openpic_read(&OpenPIC->Global.IPI_Vector_Priority(i));
 953         for (i=0; i<NumSources; i++) {
 954                 if (ISR[i] == 0)
 955                         continue;
 956                 save_irq_src_vp[i] = openpic_read(&ISR[i]->Vector_Priority) & ~OPENPIC_ACTIVITY;
 957                 save_irq_src_dest[i] = openpic_read(&ISR[i]->Destination);
 958         }
 959
 960         spin_unlock_irqrestore(&openpic_setup_lock, flags);
 961
 962         return 0;
 963 }
 964
 965 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
 966  * we need something better to deal with that... Maybe switch to S1 for
 967  * cpufreq changes
 968  */
 969 int openpic_resume(struct sys_device *sysdev)
 970 {
 971         int             i;
 972         unsigned long   flags;
 973         u32             vppmask =       OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
 974                                         OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK |
 975                                         OPENPIC_MASK;
 976
 977         spin_lock_irqsave(&openpic_setup_lock, flags);
 978
 979         if ((--openpic_suspend_count) > 0) {
 980                 spin_unlock_irqrestore(&openpic_setup_lock, flags);
 981                 return 0;
 982         }
 983
 984         openpic_reset();
 985
 986         /* OpenPIC sometimes seem to need some time to be fully back up... */
 987         do {
 988                 openpic_set_spurious(OPENPIC_VEC_SPURIOUS+open_pic_irq_offset);
 989         } while(openpic_readfield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK)
 990                         != (OPENPIC_VEC_SPURIOUS + open_pic_irq_offset));
 991
 992         openpic_disable_8259_pass_through();
 993
 994         for (i=0; i<OPENPIC_NUM_IPI; i++)
 995                 openpic_write(&OpenPIC->Global.IPI_Vector_Priority(i),
 996                               save_ipi_vp[i]);
 997         for (i=0; i<NumSources; i++) {
 998                 if (ISR[i] == 0)
 999                         continue;
1000                 openpic_write(&ISR[i]->Destination, save_irq_src_dest[i]);
1001                 openpic_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
1002                 /* make sure mask gets to controller before we return to user */
1003                 do {
1004                         openpic_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
1005                 } while (openpic_readfield(&ISR[i]->Vector_Priority, vppmask)
1006                          != (save_irq_src_vp[i] & vppmask));
1007         }
1008         for (i=0; i<NumProcessors; i++)
1009                 openpic_write(&OpenPIC->Processor[i].Current_Task_Priority,
1010                               save_cpu_task_pri[i]);
1011
1012         open_pic.enable = openpic_enable_irq;
1013         open_pic.disable = openpic_disable_irq;
1014
1015         spin_unlock_irqrestore(&openpic_setup_lock, flags);
1016
1017         return 0;
1018 }
1019
1020 #endif /* CONFIG_PM */
1021
1022 static struct sysdev_class openpic_sysclass = {
1023         set_kset_name("openpic"),
1024 };
1025
1026 static struct sys_device device_openpic = {
1027         .id             = 0,
1028         .cls            = &openpic_sysclass,
1029 };
1030
1031 static struct sysdev_driver driver_openpic = {
1032 #ifdef CONFIG_PM
1033         .suspend        = &openpic_suspend,
1034         .resume         = &openpic_resume,
1035 #endif /* CONFIG_PM */
1036 };
1037
1038 static int __init init_openpic_sysfs(void)
1039 {
1040         int rc;
1041
1042         if (!OpenPIC_Addr)
1043                 return -ENODEV;
1044         printk(KERN_DEBUG "Registering openpic with sysfs...\n");
1045         rc = sysdev_class_register(&openpic_sysclass);
1046         if (rc) {
1047                 printk(KERN_ERR "Failed registering openpic sys class\n");
1048                 return -ENODEV;
1049         }
1050         rc = sysdev_register(&device_openpic);
1051         if (rc) {
1052                 printk(KERN_ERR "Failed registering openpic sys device\n");
1053                 return -ENODEV;
1054         }
1055         rc = sysdev_driver_register(&openpic_sysclass, &driver_openpic);
1056         if (rc) {
1057                 printk(KERN_ERR "Failed registering openpic sys driver\n");
1058                 return -ENODEV;
1059         }
1060         return 0;
1061 }
1062
1063 subsys_initcall(init_openpic_sysfs);
1064