2 * arch/ppc/kernel/open_pic.c -- OpenPIC Interrupt Handling
4 * Copyright (C) 1997 Geert Uytterhoeven
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
11 #include <linux/config.h>
12 #include <linux/types.h>
13 #include <linux/kernel.h>
14 #include <linux/sched.h>
15 #include <linux/init.h>
16 #include <linux/irq.h>
17 #include <linux/interrupt.h>
18 #include <linux/sysdev.h>
19 #include <linux/errno.h>
20 #include <asm/ptrace.h>
21 #include <asm/signal.h>
25 #include <asm/sections.h>
26 #include <asm/open_pic.h>
27 #include <asm/i8259.h>
29 #include "open_pic_defs.h"
31 #if defined(CONFIG_PRPMC800) || defined(CONFIG_85xx)
32 #define OPENPIC_BIG_ENDIAN
36 static volatile struct OpenPIC *OpenPIC = NULL;
39 * We define OpenPIC_InitSenses table thusly:
40 * bit 0x1: sense, 0 for edge and 1 for level.
41 * bit 0x2: polarity, 0 for negative, 1 for positive.
43 u_int OpenPIC_NumInitSenses __initdata = 0;
44 u_char *OpenPIC_InitSenses __initdata = NULL;
45 extern int use_of_interrupt_tree;
47 static u_int NumProcessors;
48 static u_int NumSources;
49 static int open_pic_irq_offset;
50 static volatile OpenPIC_Source *ISR[NR_IRQS];
51 static int openpic_cascade_irq = -1;
52 static int (*openpic_cascade_fn)(struct pt_regs *);
54 /* Global Operations */
55 static void openpic_disable_8259_pass_through(void);
56 static void openpic_set_priority(u_int pri);
57 static void openpic_set_spurious(u_int vector);
60 /* Interprocessor Interrupts */
61 static void openpic_initipi(u_int ipi, u_int pri, u_int vector);
62 static irqreturn_t openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *);
65 /* Timer Interrupts */
66 static void openpic_inittimer(u_int timer, u_int pri, u_int vector);
67 static void openpic_maptimer(u_int timer, cpumask_t cpumask);
69 /* Interrupt Sources */
70 static void openpic_enable_irq(u_int irq);
71 static void openpic_disable_irq(u_int irq);
72 static void openpic_initirq(u_int irq, u_int pri, u_int vector, int polarity,
74 static void openpic_mapirq(u_int irq, cpumask_t cpumask, cpumask_t keepmask);
77 * These functions are not used but the code is kept here
78 * for completeness and future reference.
81 static void openpic_enable_8259_pass_through(void);
82 static u_int openpic_get_priority(void);
83 static u_int openpic_get_spurious(void);
84 static void openpic_set_sense(u_int irq, int sense);
88 * Description of the openpic for the higher-level irq code
90 static void openpic_end_irq(unsigned int irq_nr);
91 static void openpic_ack_irq(unsigned int irq_nr);
92 static void openpic_set_affinity(unsigned int irq_nr, cpumask_t cpumask);
94 struct hw_interrupt_type open_pic = {
95 .typename = " OpenPIC ",
96 .enable = openpic_enable_irq,
97 .disable = openpic_disable_irq,
98 .ack = openpic_ack_irq,
99 .end = openpic_end_irq,
100 .set_affinity = openpic_set_affinity,
104 static void openpic_end_ipi(unsigned int irq_nr);
105 static void openpic_ack_ipi(unsigned int irq_nr);
106 static void openpic_enable_ipi(unsigned int irq_nr);
107 static void openpic_disable_ipi(unsigned int irq_nr);
109 struct hw_interrupt_type open_pic_ipi = {
110 .typename = " OpenPIC ",
111 .enable = openpic_enable_ipi,
112 .disable = openpic_disable_ipi,
113 .ack = openpic_ack_ipi,
114 .end = openpic_end_ipi,
116 #endif /* CONFIG_SMP */
119 * Accesses to the current processor's openpic registers
122 #define THIS_CPU Processor[cpu]
123 #define DECL_THIS_CPU int cpu = smp_hw_index[smp_processor_id()]
124 #define CHECK_THIS_CPU check_arg_cpu(cpu)
126 #define THIS_CPU Processor[0]
127 #define DECL_THIS_CPU
128 #define CHECK_THIS_CPU
129 #endif /* CONFIG_SMP */
132 #define check_arg_ipi(ipi) \
133 if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \
134 printk("open_pic.c:%d: invalid ipi %d\n", __LINE__, ipi);
135 #define check_arg_timer(timer) \
136 if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \
137 printk("open_pic.c:%d: invalid timer %d\n", __LINE__, timer);
138 #define check_arg_vec(vec) \
139 if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \
140 printk("open_pic.c:%d: invalid vector %d\n", __LINE__, vec);
141 #define check_arg_pri(pri) \
142 if (pri < 0 || pri >= OPENPIC_NUM_PRI) \
143 printk("open_pic.c:%d: invalid priority %d\n", __LINE__, pri);
145 * Print out a backtrace if it's out of range, since if it's larger than NR_IRQ's
146 * data has probably been corrupted and we're going to panic or deadlock later
149 #define check_arg_irq(irq) \
150 if (irq < open_pic_irq_offset || irq >= NumSources+open_pic_irq_offset \
151 || ISR[irq - open_pic_irq_offset] == 0) { \
152 printk("open_pic.c:%d: invalid irq %d\n", __LINE__, irq); \
154 #define check_arg_cpu(cpu) \
155 if (cpu < 0 || cpu >= NumProcessors){ \
156 printk("open_pic.c:%d: invalid cpu %d\n", __LINE__, cpu); \
159 #define check_arg_ipi(ipi) do {} while (0)
160 #define check_arg_timer(timer) do {} while (0)
161 #define check_arg_vec(vec) do {} while (0)
162 #define check_arg_pri(pri) do {} while (0)
163 #define check_arg_irq(irq) do {} while (0)
164 #define check_arg_cpu(cpu) do {} while (0)
167 u_int openpic_read(volatile u_int *addr)
171 #ifdef OPENPIC_BIG_ENDIAN
179 static inline void openpic_write(volatile u_int *addr, u_int val)
181 #ifdef OPENPIC_BIG_ENDIAN
188 static inline u_int openpic_readfield(volatile u_int *addr, u_int mask)
190 u_int val = openpic_read(addr);
194 inline void openpic_writefield(volatile u_int *addr, u_int mask,
197 u_int val = openpic_read(addr);
198 openpic_write(addr, (val & ~mask) | (field & mask));
201 static inline void openpic_clearfield(volatile u_int *addr, u_int mask)
203 openpic_writefield(addr, mask, 0);
206 static inline void openpic_setfield(volatile u_int *addr, u_int mask)
208 openpic_writefield(addr, mask, mask);
211 static void openpic_safe_writefield(volatile u_int *addr, u_int mask,
214 openpic_setfield(addr, OPENPIC_MASK);
215 while (openpic_read(addr) & OPENPIC_ACTIVITY);
216 openpic_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
220 /* yes this is right ... bug, feature, you decide! -- tgall */
221 u_int openpic_read_IPI(volatile u_int* addr)
224 #if defined(OPENPIC_BIG_ENDIAN) || defined(CONFIG_POWER3)
232 /* because of the power3 be / le above, this is needed */
233 inline void openpic_writefield_IPI(volatile u_int* addr, u_int mask, u_int field)
235 u_int val = openpic_read_IPI(addr);
236 openpic_write(addr, (val & ~mask) | (field & mask));
239 static inline void openpic_clearfield_IPI(volatile u_int *addr, u_int mask)
241 openpic_writefield_IPI(addr, mask, 0);
244 static inline void openpic_setfield_IPI(volatile u_int *addr, u_int mask)
246 openpic_writefield_IPI(addr, mask, mask);
249 static void openpic_safe_writefield_IPI(volatile u_int *addr, u_int mask, u_int field)
251 openpic_setfield_IPI(addr, OPENPIC_MASK);
253 /* wait until it's not in use */
254 /* BenH: Is this code really enough ? I would rather check the result
255 * and eventually retry ...
257 while(openpic_read_IPI(addr) & OPENPIC_ACTIVITY);
259 openpic_writefield_IPI(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
261 #endif /* CONFIG_SMP */
263 #ifdef CONFIG_EPIC_SERIAL_MODE
264 static void __init openpic_eicr_set_clk(u_int clkval)
266 openpic_writefield(&OpenPIC->Global.Global_Configuration1,
267 OPENPIC_EICR_S_CLK_MASK, (clkval << 28));
270 static void __init openpic_enable_sie(void)
272 openpic_setfield(&OpenPIC->Global.Global_Configuration1,
277 #if defined(CONFIG_EPIC_SERIAL_MODE) || defined(CONFIG_PM)
278 static void openpic_reset(void)
280 openpic_setfield(&OpenPIC->Global.Global_Configuration0,
281 OPENPIC_CONFIG_RESET);
282 while (openpic_readfield(&OpenPIC->Global.Global_Configuration0,
283 OPENPIC_CONFIG_RESET))
288 void __init openpic_set_sources(int first_irq, int num_irqs, void *first_ISR)
290 volatile OpenPIC_Source *src = first_ISR;
293 last_irq = first_irq + num_irqs;
294 if (last_irq > NumSources)
295 NumSources = last_irq;
297 src = &((struct OpenPIC *)OpenPIC_Addr)->Source[first_irq];
298 for (i = first_irq; i < last_irq; ++i, ++src)
303 * The `offset' parameter defines where the interrupts handled by the
304 * OpenPIC start in the space of interrupt numbers that the kernel knows
305 * about. In other words, the OpenPIC's IRQ0 is numbered `offset' in the
306 * kernel's interrupt numbering scheme.
307 * We assume there is only one OpenPIC.
309 void __init openpic_init(int offset)
316 printk("No OpenPIC found !\n");
319 OpenPIC = (volatile struct OpenPIC *)OpenPIC_Addr;
321 #ifdef CONFIG_EPIC_SERIAL_MODE
322 /* Have to start from ground zero.
327 if (ppc_md.progress) ppc_md.progress("openpic: enter", 0x122);
329 t = openpic_read(&OpenPIC->Global.Feature_Reporting0);
330 switch (t & OPENPIC_FEATURE_VERSION_MASK) {
344 NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >>
345 OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1;
347 openpic_set_sources(0,
348 ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >>
349 OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1,
351 printk("OpenPIC Version %s (%d CPUs and %d IRQ sources) at %p\n",
352 version, NumProcessors, NumSources, OpenPIC);
353 timerfreq = openpic_read(&OpenPIC->Global.Timer_Frequency);
355 printk("OpenPIC timer frequency is %d.%06d MHz\n",
356 timerfreq / 1000000, timerfreq % 1000000);
358 open_pic_irq_offset = offset;
360 /* Initialize timer interrupts */
361 if ( ppc_md.progress ) ppc_md.progress("openpic: timer",0x3ba);
362 for (i = 0; i < OPENPIC_NUM_TIMERS; i++) {
363 /* Disabled, Priority 0 */
364 openpic_inittimer(i, 0, OPENPIC_VEC_TIMER+i+offset);
366 openpic_maptimer(i, CPU_MASK_NONE);
370 /* Initialize IPI interrupts */
371 if ( ppc_md.progress ) ppc_md.progress("openpic: ipi",0x3bb);
372 for (i = 0; i < OPENPIC_NUM_IPI; i++) {
373 /* Disabled, Priority 10..13 */
374 openpic_initipi(i, 10+i, OPENPIC_VEC_IPI+i+offset);
375 /* IPIs are per-CPU */
376 irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU;
377 irq_desc[OPENPIC_VEC_IPI+i+offset].handler = &open_pic_ipi;
381 /* Initialize external interrupts */
382 if (ppc_md.progress) ppc_md.progress("openpic: external",0x3bc);
384 openpic_set_priority(0xf);
386 /* Init all external sources, including possibly the cascade. */
387 for (i = 0; i < NumSources; i++) {
393 /* the bootloader may have left it enabled (bad !) */
394 openpic_disable_irq(i+offset);
396 sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: \
397 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE);
399 if (sense & IRQ_SENSE_MASK)
400 irq_desc[i+offset].status = IRQ_LEVEL;
402 /* Enabled, Priority 8 */
403 openpic_initirq(i, 8, i+offset, (sense & IRQ_POLARITY_MASK),
404 (sense & IRQ_SENSE_MASK));
406 openpic_mapirq(i, CPU_MASK_CPU0, CPU_MASK_NONE);
409 /* Init descriptors */
410 for (i = offset; i < NumSources + offset; i++)
411 irq_desc[i].handler = &open_pic;
413 /* Initialize the spurious interrupt */
414 if (ppc_md.progress) ppc_md.progress("openpic: spurious",0x3bd);
415 openpic_set_spurious(OPENPIC_VEC_SPURIOUS);
416 openpic_disable_8259_pass_through();
417 #ifdef CONFIG_EPIC_SERIAL_MODE
418 openpic_eicr_set_clk(7); /* Slowest value until we know better */
419 openpic_enable_sie();
421 openpic_set_priority(0);
423 if (ppc_md.progress) ppc_md.progress("openpic: exit",0x222);
427 static void openpic_enable_8259_pass_through(void)
429 openpic_clearfield(&OpenPIC->Global.Global_Configuration0,
430 OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
434 static void openpic_disable_8259_pass_through(void)
436 openpic_setfield(&OpenPIC->Global.Global_Configuration0,
437 OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
441 * Find out the current interrupt
443 u_int openpic_irq(void)
449 vec = openpic_readfield(&OpenPIC->THIS_CPU.Interrupt_Acknowledge,
450 OPENPIC_VECTOR_MASK);
454 void openpic_eoi(void)
459 openpic_write(&OpenPIC->THIS_CPU.EOI, 0);
460 /* Handle PCI write posting */
461 (void)openpic_read(&OpenPIC->THIS_CPU.EOI);
465 static u_int openpic_get_priority(void)
470 return openpic_readfield(&OpenPIC->THIS_CPU.Current_Task_Priority,
471 OPENPIC_CURRENT_TASK_PRIORITY_MASK);
475 static void __init openpic_set_priority(u_int pri)
481 openpic_writefield(&OpenPIC->THIS_CPU.Current_Task_Priority,
482 OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri);
486 * Get/set the spurious vector
489 static u_int openpic_get_spurious(void)
491 return openpic_readfield(&OpenPIC->Global.Spurious_Vector,
492 OPENPIC_VECTOR_MASK);
496 static void openpic_set_spurious(u_int vec)
499 openpic_writefield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK,
505 * Convert a cpu mask from logical to physical cpu numbers.
507 static inline cpumask_t physmask(cpumask_t cpumask)
510 cpumask_t mask = CPU_MASK_NONE;
512 cpus_and(cpumask, cpu_online_map, cpumask);
514 for (i = 0; i < NR_CPUS; i++)
515 if (cpu_isset(i, cpumask))
516 cpu_set(smp_hw_index[i], mask);
521 #define physmask(cpumask) (cpumask)
524 void openpic_reset_processor_phys(u_int mask)
526 openpic_write(&OpenPIC->Global.Processor_Initialization, mask);
529 #if defined(CONFIG_SMP) || defined(CONFIG_PM)
530 static spinlock_t openpic_setup_lock = SPIN_LOCK_UNLOCKED;
535 * Initialize an interprocessor interrupt (and disable it)
537 * ipi: OpenPIC interprocessor interrupt number
538 * pri: interrupt source priority
539 * vec: the vector it will produce
541 static void __init openpic_initipi(u_int ipi, u_int pri, u_int vec)
546 openpic_safe_writefield_IPI(&OpenPIC->Global.IPI_Vector_Priority(ipi),
547 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
548 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
552 * Send an IPI to one or more CPUs
554 * Externally called, however, it takes an IPI number (0...OPENPIC_NUM_IPI)
555 * and not a system-wide interrupt number
557 void openpic_cause_IPI(u_int ipi, cpumask_t cpumask)
564 phys = physmask(cpumask);
565 openpic_write(&OpenPIC->THIS_CPU.IPI_Dispatch(ipi),
566 cpus_addr(physmask(cpumask))[0]);
569 void openpic_request_IPIs(void)
574 * Make sure this matches what is defined in smp.c for
575 * smp_message_{pass|recv}() or what shows up in
576 * /proc/interrupts will be wrong!!! --Troy */
581 /* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */
582 request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset,
583 openpic_ipi_action, SA_INTERRUPT,
584 "IPI0 (call function)", NULL);
585 request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+1,
586 openpic_ipi_action, SA_INTERRUPT,
587 "IPI1 (reschedule)", NULL);
588 request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+2,
589 openpic_ipi_action, SA_INTERRUPT,
590 "IPI2 (invalidate tlb)", NULL);
591 request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+3,
592 openpic_ipi_action, SA_INTERRUPT,
593 "IPI3 (xmon break)", NULL);
595 for ( i = 0; i < OPENPIC_NUM_IPI ; i++ )
596 openpic_enable_ipi(OPENPIC_VEC_IPI+open_pic_irq_offset+i);
600 * Do per-cpu setup for SMP systems.
602 * Get IPI's working and start taking interrupts.
606 void __devinit do_openpic_setup_cpu(void)
608 #ifdef CONFIG_IRQ_ALL_CPUS
610 cpumask_t msk = CPU_MASK_NONE;
612 spin_lock(&openpic_setup_lock);
614 #ifdef CONFIG_IRQ_ALL_CPUS
615 cpu_set(smp_hw_index[smp_processor_id()], msk);
617 /* let the openpic know we want intrs. default affinity
618 * is 0xffffffff until changed via /proc
619 * That's how it's done on x86. If we want it differently, then
620 * we should make sure we also change the default values of irq_affinity
623 for (i = 0; i < NumSources; i++)
624 openpic_mapirq(i, msk, CPU_MASK_ALL);
625 #endif /* CONFIG_IRQ_ALL_CPUS */
626 openpic_set_priority(0);
628 spin_unlock(&openpic_setup_lock);
630 #endif /* CONFIG_SMP */
633 * Initialize a timer interrupt (and disable it)
635 * timer: OpenPIC timer number
636 * pri: interrupt source priority
637 * vec: the vector it will produce
639 static void __init openpic_inittimer(u_int timer, u_int pri, u_int vec)
641 check_arg_timer(timer);
644 openpic_safe_writefield(&OpenPIC->Global.Timer[timer].Vector_Priority,
645 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
646 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
650 * Map a timer interrupt to one or more CPUs
652 static void __init openpic_maptimer(u_int timer, cpumask_t cpumask)
654 cpumask_t phys = physmask(cpumask);
655 check_arg_timer(timer);
656 openpic_write(&OpenPIC->Global.Timer[timer].Destination,
661 * Initalize the interrupt source which will generate an NMI.
662 * This raises the interrupt's priority from 8 to 9.
664 * irq: The logical IRQ which generates an NMI.
667 openpic_init_nmi_irq(u_int irq)
670 openpic_safe_writefield(&ISR[irq - open_pic_irq_offset]->Vector_Priority,
671 OPENPIC_PRIORITY_MASK,
672 9 << OPENPIC_PRIORITY_SHIFT);
677 * All functions below take an offset'ed irq argument
682 * Hookup a cascade to the OpenPIC.
685 openpic_hookup_cascade(u_int irq, char *name,
686 int (*cascade_fn)(struct pt_regs *))
688 openpic_cascade_irq = irq;
689 openpic_cascade_fn = cascade_fn;
690 if (request_irq(irq, no_action, SA_INTERRUPT, name, NULL))
691 printk("Unable to get OpenPIC IRQ %d for cascade\n",
692 irq - open_pic_irq_offset);
696 * Enable/disable an external interrupt source
698 * Externally called, irq is an offseted system-wide interrupt number
700 static void openpic_enable_irq(u_int irq)
705 vpp = &ISR[irq - open_pic_irq_offset]->Vector_Priority;
706 openpic_clearfield(vpp, OPENPIC_MASK);
707 /* make sure mask gets to controller before we return to user */
709 mb(); /* sync is probably useless here */
710 } while (openpic_readfield(vpp, OPENPIC_MASK));
713 static void openpic_disable_irq(u_int irq)
719 vpp = &ISR[irq - open_pic_irq_offset]->Vector_Priority;
720 openpic_setfield(vpp, OPENPIC_MASK);
721 /* make sure mask gets to controller before we return to user */
723 mb(); /* sync is probably useless here */
724 vp = openpic_readfield(vpp, OPENPIC_MASK | OPENPIC_ACTIVITY);
725 } while((vp & OPENPIC_ACTIVITY) && !(vp & OPENPIC_MASK));
730 * Enable/disable an IPI interrupt source
732 * Externally called, irq is an offseted system-wide interrupt number
734 void openpic_enable_ipi(u_int irq)
736 irq -= (OPENPIC_VEC_IPI+open_pic_irq_offset);
738 openpic_clearfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK);
742 void openpic_disable_ipi(u_int irq)
744 irq -= (OPENPIC_VEC_IPI+open_pic_irq_offset);
746 openpic_setfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK);
751 * Initialize an interrupt source (and disable it!)
753 * irq: OpenPIC interrupt number
754 * pri: interrupt source priority
755 * vec: the vector it will produce
756 * pol: polarity (1 for positive, 0 for negative)
757 * sense: 1 for level, 0 for edge
760 openpic_initirq(u_int irq, u_int pri, u_int vec, int pol, int sense)
762 openpic_safe_writefield(&ISR[irq]->Vector_Priority,
763 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
764 OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK,
765 (pri << OPENPIC_PRIORITY_SHIFT) | vec |
766 (pol ? OPENPIC_POLARITY_POSITIVE :
767 OPENPIC_POLARITY_NEGATIVE) |
768 (sense ? OPENPIC_SENSE_LEVEL : OPENPIC_SENSE_EDGE));
772 * Map an interrupt source to one or more CPUs
774 static void openpic_mapirq(u_int irq, cpumask_t physmask, cpumask_t keepmask)
778 if (!cpus_empty(keepmask)) {
779 cpumask_t irqdest = { .bits[0] = openpic_read(&ISR[irq]->Destination) };
780 cpus_and(irqdest, irqdest, keepmask);
781 cpus_or(physmask, physmask, irqdest);
783 openpic_write(&ISR[irq]->Destination, cpus_addr(physmask)[0]);
788 * Set the sense for an interrupt source (and disable it!)
790 * sense: 1 for level, 0 for edge
792 static void openpic_set_sense(u_int irq, int sense)
795 openpic_safe_writefield(&ISR[irq]->Vector_Priority,
797 (sense ? OPENPIC_SENSE_LEVEL : 0));
801 /* No spinlocks, should not be necessary with the OpenPIC
802 * (1 register = 1 interrupt and we have the desc lock).
804 static void openpic_ack_irq(unsigned int irq_nr)
806 #ifdef __SLOW_VERSION__
807 openpic_disable_irq(irq_nr);
810 if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0)
815 static void openpic_end_irq(unsigned int irq_nr)
817 #ifdef __SLOW_VERSION__
818 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
819 && irq_desc[irq_nr].action)
820 openpic_enable_irq(irq_nr);
822 if ((irq_desc[irq_nr].status & IRQ_LEVEL) != 0)
827 static void openpic_set_affinity(unsigned int irq_nr, cpumask_t cpumask)
829 openpic_mapirq(irq_nr - open_pic_irq_offset, physmask(cpumask), CPU_MASK_NONE);
833 static void openpic_ack_ipi(unsigned int irq_nr)
838 static void openpic_end_ipi(unsigned int irq_nr)
842 static irqreturn_t openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *regs)
844 smp_message_recv(cpl-OPENPIC_VEC_IPI-open_pic_irq_offset, regs);
848 #endif /* CONFIG_SMP */
851 openpic_get_irq(struct pt_regs *regs)
853 int irq = openpic_irq();
856 * Check for the cascade interrupt and call the cascaded
857 * interrupt controller function (usually i8259_irq) if so.
858 * This should move to irq.c eventually. -- paulus
860 if (irq == openpic_cascade_irq && openpic_cascade_fn != NULL) {
861 int cirq = openpic_cascade_fn(regs);
863 /* Allow for the cascade being shared with other devices */
868 } else if (irq == OPENPIC_VEC_SPURIOUS)
875 smp_openpic_message_pass(int target, int msg, unsigned long data, int wait)
877 cpumask_t mask = CPU_MASK_ALL;
878 /* make sure we're sending something that translates to an IPI */
880 printk("SMP %d: smp_message_pass: unknown msg %d\n",
881 smp_processor_id(), msg);
886 openpic_cause_IPI(msg, mask);
888 case MSG_ALL_BUT_SELF:
889 cpu_clear(smp_processor_id(), mask);
890 openpic_cause_IPI(msg, mask);
893 openpic_cause_IPI(msg, cpumask_of_cpu(target));
897 #endif /* CONFIG_SMP */
902 * We implement the IRQ controller as a sysdev and put it
903 * to sleep at powerdown stage (the callback is named suspend,
904 * but it's old semantics, for the Device Model, it's really
905 * powerdown). The possible problem is that another sysdev that
906 * happens to be suspend after this one will have interrupts off,
907 * that may be an issue... For now, this isn't an issue on pmac
911 static u32 save_ipi_vp[OPENPIC_NUM_IPI];
912 static u32 save_irq_src_vp[OPENPIC_MAX_SOURCES];
913 static u32 save_irq_src_dest[OPENPIC_MAX_SOURCES];
914 static u32 save_cpu_task_pri[OPENPIC_MAX_PROCESSORS];
915 static int openpic_suspend_count;
917 static void openpic_cached_enable_irq(u_int irq)
920 save_irq_src_vp[irq - open_pic_irq_offset] &= ~OPENPIC_MASK;
923 static void openpic_cached_disable_irq(u_int irq)
926 save_irq_src_vp[irq - open_pic_irq_offset] |= OPENPIC_MASK;
929 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
930 * we need something better to deal with that... Maybe switch to S1 for
933 int openpic_suspend(struct sys_device *sysdev, u32 state)
938 spin_lock_irqsave(&openpic_setup_lock, flags);
940 if (openpic_suspend_count++ > 0) {
941 spin_unlock_irqrestore(&openpic_setup_lock, flags);
945 open_pic.enable = openpic_cached_enable_irq;
946 open_pic.disable = openpic_cached_disable_irq;
948 for (i=0; i<NumProcessors; i++) {
949 save_cpu_task_pri[i] = openpic_read(&OpenPIC->Processor[i].Current_Task_Priority);
950 openpic_writefield(&OpenPIC->Processor[i].Current_Task_Priority,
951 OPENPIC_CURRENT_TASK_PRIORITY_MASK, 0xf);
954 for (i=0; i<OPENPIC_NUM_IPI; i++)
955 save_ipi_vp[i] = openpic_read(&OpenPIC->Global.IPI_Vector_Priority(i));
956 for (i=0; i<NumSources; i++) {
959 save_irq_src_vp[i] = openpic_read(&ISR[i]->Vector_Priority) & ~OPENPIC_ACTIVITY;
960 save_irq_src_dest[i] = openpic_read(&ISR[i]->Destination);
963 spin_unlock_irqrestore(&openpic_setup_lock, flags);
968 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
969 * we need something better to deal with that... Maybe switch to S1 for
972 int openpic_resume(struct sys_device *sysdev)
976 u32 vppmask = OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
977 OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK |
980 spin_lock_irqsave(&openpic_setup_lock, flags);
982 if ((--openpic_suspend_count) > 0) {
983 spin_unlock_irqrestore(&openpic_setup_lock, flags);
989 /* OpenPIC sometimes seem to need some time to be fully back up... */
991 openpic_set_spurious(OPENPIC_VEC_SPURIOUS);
992 } while(openpic_readfield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK)
993 != OPENPIC_VEC_SPURIOUS);
995 openpic_disable_8259_pass_through();
997 for (i=0; i<OPENPIC_NUM_IPI; i++)
998 openpic_write(&OpenPIC->Global.IPI_Vector_Priority(i),
1000 for (i=0; i<NumSources; i++) {
1003 openpic_write(&ISR[i]->Destination, save_irq_src_dest[i]);
1004 openpic_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
1005 /* make sure mask gets to controller before we return to user */
1007 openpic_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
1008 } while (openpic_readfield(&ISR[i]->Vector_Priority, vppmask)
1009 != (save_irq_src_vp[i] & vppmask));
1011 for (i=0; i<NumProcessors; i++)
1012 openpic_write(&OpenPIC->Processor[i].Current_Task_Priority,
1013 save_cpu_task_pri[i]);
1015 open_pic.enable = openpic_enable_irq;
1016 open_pic.disable = openpic_disable_irq;
1018 spin_unlock_irqrestore(&openpic_setup_lock, flags);
1023 #endif /* CONFIG_PM */
1025 static struct sysdev_class openpic_sysclass = {
1026 set_kset_name("openpic"),
1029 static struct sys_device device_openpic = {
1031 .cls = &openpic_sysclass,
1034 static struct sysdev_driver driver_openpic = {
1036 .suspend = &openpic_suspend,
1037 .resume = &openpic_resume,
1038 #endif /* CONFIG_PM */
1041 static int __init init_openpic_sysfs(void)
1047 printk(KERN_DEBUG "Registering openpic with sysfs...\n");
1048 rc = sysdev_class_register(&openpic_sysclass);
1050 printk(KERN_ERR "Failed registering openpic sys class\n");
1053 rc = sysdev_register(&device_openpic);
1055 printk(KERN_ERR "Failed registering openpic sys device\n");
1058 rc = sysdev_driver_register(&openpic_sysclass, &driver_openpic);
1060 printk(KERN_ERR "Failed registering openpic sys driver\n");
1066 subsys_initcall(init_openpic_sysfs);