2 * arch/ppc/kernel/open_pic.c -- OpenPIC Interrupt Handling
4 * Copyright (C) 1997 Geert Uytterhoeven
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
11 #include <linux/config.h>
12 #include <linux/types.h>
13 #include <linux/kernel.h>
14 #include <linux/sched.h>
15 #include <linux/init.h>
16 #include <linux/irq.h>
17 #include <linux/interrupt.h>
18 #include <linux/sysdev.h>
19 #include <asm/ptrace.h>
20 #include <asm/signal.h>
24 #include <asm/sections.h>
25 #include <asm/open_pic.h>
26 #include <asm/i8259.h>
27 #include <asm/hardirq.h>
29 #include "open_pic_defs.h"
31 #if defined(CONFIG_PRPMC800) || defined(CONFIG_85xx)
32 #define OPENPIC_BIG_ENDIAN
36 static volatile struct OpenPIC *OpenPIC = NULL;
39 * We define OpenPIC_InitSenses table thusly:
40 * bit 0x1: sense, 0 for edge and 1 for level.
41 * bit 0x2: polarity, 0 for negative, 1 for positive.
43 u_int OpenPIC_NumInitSenses __initdata = 0;
44 u_char *OpenPIC_InitSenses __initdata = NULL;
45 extern int use_of_interrupt_tree;
47 static u_int NumProcessors;
48 static u_int NumSources;
49 static int open_pic_irq_offset;
50 static volatile OpenPIC_Source *ISR[NR_IRQS];
51 static int openpic_cascade_irq = -1;
52 static int (*openpic_cascade_fn)(struct pt_regs *);
54 /* Global Operations */
55 static void openpic_disable_8259_pass_through(void);
56 static void openpic_set_priority(u_int pri);
57 static void openpic_set_spurious(u_int vector);
60 /* Interprocessor Interrupts */
61 static void openpic_initipi(u_int ipi, u_int pri, u_int vector);
62 static irqreturn_t openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *);
65 /* Timer Interrupts */
66 static void openpic_inittimer(u_int timer, u_int pri, u_int vector);
67 static void openpic_maptimer(u_int timer, u_int cpumask);
69 /* Interrupt Sources */
70 static void openpic_enable_irq(u_int irq);
71 static void openpic_disable_irq(u_int irq);
72 static void openpic_initirq(u_int irq, u_int pri, u_int vector, int polarity,
74 static void openpic_mapirq(u_int irq, u_int cpumask, u_int keepmask);
77 * These functions are not used but the code is kept here
78 * for completeness and future reference.
81 static void openpic_enable_8259_pass_through(void);
82 static u_int openpic_get_priority(void);
83 static u_int openpic_get_spurious(void);
84 static void openpic_set_sense(u_int irq, int sense);
88 * Description of the openpic for the higher-level irq code
90 static void openpic_end_irq(unsigned int irq_nr);
91 static void openpic_ack_irq(unsigned int irq_nr);
92 static void openpic_set_affinity(unsigned int irq_nr, unsigned long cpumask);
94 struct hw_interrupt_type open_pic = {
106 static void openpic_end_ipi(unsigned int irq_nr);
107 static void openpic_ack_ipi(unsigned int irq_nr);
108 static void openpic_enable_ipi(unsigned int irq_nr);
109 static void openpic_disable_ipi(unsigned int irq_nr);
111 struct hw_interrupt_type open_pic_ipi = {
121 #endif /* CONFIG_SMP */
124 * Accesses to the current processor's openpic registers
127 #define THIS_CPU Processor[cpu]
128 #define DECL_THIS_CPU int cpu = smp_hw_index[smp_processor_id()]
129 #define CHECK_THIS_CPU check_arg_cpu(cpu)
131 #define THIS_CPU Processor[0]
132 #define DECL_THIS_CPU
133 #define CHECK_THIS_CPU
134 #endif /* CONFIG_SMP */
137 #define check_arg_ipi(ipi) \
138 if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \
139 printk("open_pic.c:%d: invalid ipi %d\n", __LINE__, ipi);
140 #define check_arg_timer(timer) \
141 if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \
142 printk("open_pic.c:%d: invalid timer %d\n", __LINE__, timer);
143 #define check_arg_vec(vec) \
144 if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \
145 printk("open_pic.c:%d: invalid vector %d\n", __LINE__, vec);
146 #define check_arg_pri(pri) \
147 if (pri < 0 || pri >= OPENPIC_NUM_PRI) \
148 printk("open_pic.c:%d: invalid priority %d\n", __LINE__, pri);
150 * Print out a backtrace if it's out of range, since if it's larger than NR_IRQ's
151 * data has probably been corrupted and we're going to panic or deadlock later
154 #define check_arg_irq(irq) \
155 if (irq < open_pic_irq_offset || irq >= NumSources+open_pic_irq_offset \
156 || ISR[irq - open_pic_irq_offset] == 0) { \
157 printk("open_pic.c:%d: invalid irq %d\n", __LINE__, irq); \
159 #define check_arg_cpu(cpu) \
160 if (cpu < 0 || cpu >= NumProcessors){ \
161 printk("open_pic.c:%d: invalid cpu %d\n", __LINE__, cpu); \
164 #define check_arg_ipi(ipi) do {} while (0)
165 #define check_arg_timer(timer) do {} while (0)
166 #define check_arg_vec(vec) do {} while (0)
167 #define check_arg_pri(pri) do {} while (0)
168 #define check_arg_irq(irq) do {} while (0)
169 #define check_arg_cpu(cpu) do {} while (0)
172 u_int openpic_read(volatile u_int *addr)
176 #ifdef OPENPIC_BIG_ENDIAN
184 static inline void openpic_write(volatile u_int *addr, u_int val)
186 #ifdef OPENPIC_BIG_ENDIAN
193 static inline u_int openpic_readfield(volatile u_int *addr, u_int mask)
195 u_int val = openpic_read(addr);
199 inline void openpic_writefield(volatile u_int *addr, u_int mask,
202 u_int val = openpic_read(addr);
203 openpic_write(addr, (val & ~mask) | (field & mask));
206 static inline void openpic_clearfield(volatile u_int *addr, u_int mask)
208 openpic_writefield(addr, mask, 0);
211 static inline void openpic_setfield(volatile u_int *addr, u_int mask)
213 openpic_writefield(addr, mask, mask);
216 static void openpic_safe_writefield(volatile u_int *addr, u_int mask,
219 openpic_setfield(addr, OPENPIC_MASK);
220 while (openpic_read(addr) & OPENPIC_ACTIVITY);
221 openpic_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
225 /* yes this is right ... bug, feature, you decide! -- tgall */
226 u_int openpic_read_IPI(volatile u_int* addr)
229 #if defined(OPENPIC_BIG_ENDIAN) || defined(CONFIG_POWER3)
237 /* because of the power3 be / le above, this is needed */
238 inline void openpic_writefield_IPI(volatile u_int* addr, u_int mask, u_int field)
240 u_int val = openpic_read_IPI(addr);
241 openpic_write(addr, (val & ~mask) | (field & mask));
244 static inline void openpic_clearfield_IPI(volatile u_int *addr, u_int mask)
246 openpic_writefield_IPI(addr, mask, 0);
249 static inline void openpic_setfield_IPI(volatile u_int *addr, u_int mask)
251 openpic_writefield_IPI(addr, mask, mask);
254 static void openpic_safe_writefield_IPI(volatile u_int *addr, u_int mask, u_int field)
256 openpic_setfield_IPI(addr, OPENPIC_MASK);
258 /* wait until it's not in use */
259 /* BenH: Is this code really enough ? I would rather check the result
260 * and eventually retry ...
262 while(openpic_read_IPI(addr) & OPENPIC_ACTIVITY);
264 openpic_writefield_IPI(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
266 #endif /* CONFIG_SMP */
268 #ifdef CONFIG_EPIC_SERIAL_MODE
269 static void __init openpic_eicr_set_clk(u_int clkval)
271 openpic_writefield(&OpenPIC->Global.Global_Configuration1,
272 OPENPIC_EICR_S_CLK_MASK, (clkval << 28));
275 static void __init openpic_enable_sie(void)
277 openpic_setfield(&OpenPIC->Global.Global_Configuration1,
282 #if defined(CONFIG_EPIC_SERIAL_MODE) || defined(CONFIG_PM)
283 static void openpic_reset(void)
285 openpic_setfield(&OpenPIC->Global.Global_Configuration0,
286 OPENPIC_CONFIG_RESET);
287 while (openpic_readfield(&OpenPIC->Global.Global_Configuration0,
288 OPENPIC_CONFIG_RESET))
293 void __init openpic_set_sources(int first_irq, int num_irqs, void *first_ISR)
295 volatile OpenPIC_Source *src = first_ISR;
298 last_irq = first_irq + num_irqs;
299 if (last_irq > NumSources)
300 NumSources = last_irq;
302 src = &((struct OpenPIC *)OpenPIC_Addr)->Source[first_irq];
303 for (i = first_irq; i < last_irq; ++i, ++src)
308 * The `offset' parameter defines where the interrupts handled by the
309 * OpenPIC start in the space of interrupt numbers that the kernel knows
310 * about. In other words, the OpenPIC's IRQ0 is numbered `offset' in the
311 * kernel's interrupt numbering scheme.
312 * We assume there is only one OpenPIC.
314 void __init openpic_init(int offset)
321 printk("No OpenPIC found !\n");
324 OpenPIC = (volatile struct OpenPIC *)OpenPIC_Addr;
326 #ifdef CONFIG_EPIC_SERIAL_MODE
327 /* Have to start from ground zero.
332 if (ppc_md.progress) ppc_md.progress("openpic: enter", 0x122);
334 t = openpic_read(&OpenPIC->Global.Feature_Reporting0);
335 switch (t & OPENPIC_FEATURE_VERSION_MASK) {
349 NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >>
350 OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1;
352 openpic_set_sources(0,
353 ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >>
354 OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1,
356 printk("OpenPIC Version %s (%d CPUs and %d IRQ sources) at %p\n",
357 version, NumProcessors, NumSources, OpenPIC);
358 timerfreq = openpic_read(&OpenPIC->Global.Timer_Frequency);
360 printk("OpenPIC timer frequency is %d.%06d MHz\n",
361 timerfreq / 1000000, timerfreq % 1000000);
363 open_pic_irq_offset = offset;
365 /* Initialize timer interrupts */
366 if ( ppc_md.progress ) ppc_md.progress("openpic: timer",0x3ba);
367 for (i = 0; i < OPENPIC_NUM_TIMERS; i++) {
368 /* Disabled, Priority 0 */
369 openpic_inittimer(i, 0, OPENPIC_VEC_TIMER+i+offset);
371 openpic_maptimer(i, 0);
375 /* Initialize IPI interrupts */
376 if ( ppc_md.progress ) ppc_md.progress("openpic: ipi",0x3bb);
377 for (i = 0; i < OPENPIC_NUM_IPI; i++) {
378 /* Disabled, Priority 10..13 */
379 openpic_initipi(i, 10+i, OPENPIC_VEC_IPI+i+offset);
380 /* IPIs are per-CPU */
381 irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU;
382 irq_desc[OPENPIC_VEC_IPI+i+offset].handler = &open_pic_ipi;
386 /* Initialize external interrupts */
387 if (ppc_md.progress) ppc_md.progress("openpic: external",0x3bc);
389 openpic_set_priority(0xf);
391 /* Init all external sources, including possibly the cascade. */
392 for (i = 0; i < NumSources; i++) {
398 /* the bootloader may have left it enabled (bad !) */
399 openpic_disable_irq(i+offset);
401 sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: \
402 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE);
404 if (sense & IRQ_SENSE_MASK)
405 irq_desc[i+offset].status = IRQ_LEVEL;
407 /* Enabled, Priority 8 */
408 openpic_initirq(i, 8, i+offset, (sense & IRQ_POLARITY_MASK),
409 (sense & IRQ_SENSE_MASK));
411 openpic_mapirq(i, 1<<0, 0);
414 /* Init descriptors */
415 for (i = offset; i < NumSources + offset; i++)
416 irq_desc[i].handler = &open_pic;
418 /* Initialize the spurious interrupt */
419 if (ppc_md.progress) ppc_md.progress("openpic: spurious",0x3bd);
420 openpic_set_spurious(OPENPIC_VEC_SPURIOUS+offset);
421 openpic_disable_8259_pass_through();
422 #ifdef CONFIG_EPIC_SERIAL_MODE
423 openpic_eicr_set_clk(7); /* Slowest value until we know better */
424 openpic_enable_sie();
426 openpic_set_priority(0);
428 if (ppc_md.progress) ppc_md.progress("openpic: exit",0x222);
432 static void openpic_enable_8259_pass_through(void)
434 openpic_clearfield(&OpenPIC->Global.Global_Configuration0,
435 OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
439 static void openpic_disable_8259_pass_through(void)
441 openpic_setfield(&OpenPIC->Global.Global_Configuration0,
442 OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
446 * Find out the current interrupt
448 u_int openpic_irq(void)
454 vec = openpic_readfield(&OpenPIC->THIS_CPU.Interrupt_Acknowledge,
455 OPENPIC_VECTOR_MASK);
459 void openpic_eoi(void)
464 openpic_write(&OpenPIC->THIS_CPU.EOI, 0);
465 /* Handle PCI write posting */
466 (void)openpic_read(&OpenPIC->THIS_CPU.EOI);
470 static u_int openpic_get_priority(void)
475 return openpic_readfield(&OpenPIC->THIS_CPU.Current_Task_Priority,
476 OPENPIC_CURRENT_TASK_PRIORITY_MASK);
480 static void __init openpic_set_priority(u_int pri)
486 openpic_writefield(&OpenPIC->THIS_CPU.Current_Task_Priority,
487 OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri);
491 * Get/set the spurious vector
494 static u_int openpic_get_spurious(void)
496 return openpic_readfield(&OpenPIC->Global.Spurious_Vector,
497 OPENPIC_VECTOR_MASK);
501 static void openpic_set_spurious(u_int vec)
504 openpic_writefield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK,
510 * Convert a cpu mask from logical to physical cpu numbers.
512 static inline u32 physmask(u32 cpumask)
517 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
519 mask |= (cpumask & 1) << smp_hw_index[i];
523 #define physmask(cpumask) (cpumask)
526 void openpic_reset_processor_phys(u_int mask)
528 openpic_write(&OpenPIC->Global.Processor_Initialization, mask);
531 #if defined(CONFIG_SMP) || defined(CONFIG_PM)
532 static spinlock_t openpic_setup_lock = SPIN_LOCK_UNLOCKED;
537 * Initialize an interprocessor interrupt (and disable it)
539 * ipi: OpenPIC interprocessor interrupt number
540 * pri: interrupt source priority
541 * vec: the vector it will produce
543 static void __init openpic_initipi(u_int ipi, u_int pri, u_int vec)
548 openpic_safe_writefield_IPI(&OpenPIC->Global.IPI_Vector_Priority(ipi),
549 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
550 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
554 * Send an IPI to one or more CPUs
556 * Externally called, however, it takes an IPI number (0...OPENPIC_NUM_IPI)
557 * and not a system-wide interrupt number
559 void openpic_cause_IPI(u_int ipi, u_int cpumask)
565 openpic_write(&OpenPIC->THIS_CPU.IPI_Dispatch(ipi),
569 void openpic_request_IPIs(void)
574 * Make sure this matches what is defined in smp.c for
575 * smp_message_{pass|recv}() or what shows up in
576 * /proc/interrupts will be wrong!!! --Troy */
581 /* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */
582 request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset,
583 openpic_ipi_action, SA_INTERRUPT,
584 "IPI0 (call function)", 0);
585 request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+1,
586 openpic_ipi_action, SA_INTERRUPT,
587 "IPI1 (reschedule)", 0);
588 request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+2,
589 openpic_ipi_action, SA_INTERRUPT,
590 "IPI2 (invalidate tlb)", 0);
591 request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+3,
592 openpic_ipi_action, SA_INTERRUPT,
593 "IPI3 (xmon break)", 0);
595 for ( i = 0; i < OPENPIC_NUM_IPI ; i++ )
596 openpic_enable_ipi(OPENPIC_VEC_IPI+open_pic_irq_offset+i);
600 * Do per-cpu setup for SMP systems.
602 * Get IPI's working and start taking interrupts.
606 void __devinit do_openpic_setup_cpu(void)
608 #ifdef CONFIG_IRQ_ALL_CPUS
612 spin_lock(&openpic_setup_lock);
614 #ifdef CONFIG_IRQ_ALL_CPUS
615 msk = 1 << smp_hw_index[smp_processor_id()];
617 /* let the openpic know we want intrs. default affinity
618 * is 0xffffffff until changed via /proc
619 * That's how it's done on x86. If we want it differently, then
620 * we should make sure we also change the default values of irq_affinity
623 for (i = 0; i < NumSources; i++)
624 openpic_mapirq(i, msk, ~0U);
625 #endif /* CONFIG_IRQ_ALL_CPUS */
626 openpic_set_priority(0);
628 spin_unlock(&openpic_setup_lock);
630 #endif /* CONFIG_SMP */
633 * Initialize a timer interrupt (and disable it)
635 * timer: OpenPIC timer number
636 * pri: interrupt source priority
637 * vec: the vector it will produce
639 static void __init openpic_inittimer(u_int timer, u_int pri, u_int vec)
641 check_arg_timer(timer);
644 openpic_safe_writefield(&OpenPIC->Global.Timer[timer].Vector_Priority,
645 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
646 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
650 * Map a timer interrupt to one or more CPUs
652 static void __init openpic_maptimer(u_int timer, u_int cpumask)
654 check_arg_timer(timer);
655 openpic_write(&OpenPIC->Global.Timer[timer].Destination,
660 * Initalize the interrupt source which will generate an NMI.
661 * This raises the interrupt's priority from 8 to 9.
663 * irq: The logical IRQ which generates an NMI.
666 openpic_init_nmi_irq(u_int irq)
669 openpic_safe_writefield(&ISR[irq - open_pic_irq_offset]->Vector_Priority,
670 OPENPIC_PRIORITY_MASK,
671 9 << OPENPIC_PRIORITY_SHIFT);
676 * All functions below take an offset'ed irq argument
681 * Hookup a cascade to the OpenPIC.
684 openpic_hookup_cascade(u_int irq, char *name,
685 int (*cascade_fn)(struct pt_regs *))
687 openpic_cascade_irq = irq;
688 openpic_cascade_fn = cascade_fn;
689 if (request_irq(irq, no_action, SA_INTERRUPT, name, NULL))
690 printk("Unable to get OpenPIC IRQ %d for cascade\n",
691 irq - open_pic_irq_offset);
695 * Enable/disable an external interrupt source
697 * Externally called, irq is an offseted system-wide interrupt number
699 static void openpic_enable_irq(u_int irq)
704 vpp = &ISR[irq - open_pic_irq_offset]->Vector_Priority;
705 openpic_clearfield(vpp, OPENPIC_MASK);
706 /* make sure mask gets to controller before we return to user */
708 mb(); /* sync is probably useless here */
709 } while (openpic_readfield(vpp, OPENPIC_MASK));
712 static void openpic_disable_irq(u_int irq)
718 vpp = &ISR[irq - open_pic_irq_offset]->Vector_Priority;
719 openpic_setfield(vpp, OPENPIC_MASK);
720 /* make sure mask gets to controller before we return to user */
722 mb(); /* sync is probably useless here */
723 vp = openpic_readfield(vpp, OPENPIC_MASK | OPENPIC_ACTIVITY);
724 } while((vp & OPENPIC_ACTIVITY) && !(vp & OPENPIC_MASK));
729 * Enable/disable an IPI interrupt source
731 * Externally called, irq is an offseted system-wide interrupt number
733 void openpic_enable_ipi(u_int irq)
735 irq -= (OPENPIC_VEC_IPI+open_pic_irq_offset);
737 openpic_clearfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK);
741 void openpic_disable_ipi(u_int irq)
743 irq -= (OPENPIC_VEC_IPI+open_pic_irq_offset);
745 openpic_setfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK);
750 * Initialize an interrupt source (and disable it!)
752 * irq: OpenPIC interrupt number
753 * pri: interrupt source priority
754 * vec: the vector it will produce
755 * pol: polarity (1 for positive, 0 for negative)
756 * sense: 1 for level, 0 for edge
759 openpic_initirq(u_int irq, u_int pri, u_int vec, int pol, int sense)
761 openpic_safe_writefield(&ISR[irq]->Vector_Priority,
762 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
763 OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK,
764 (pri << OPENPIC_PRIORITY_SHIFT) | vec |
765 (pol ? OPENPIC_POLARITY_POSITIVE :
766 OPENPIC_POLARITY_NEGATIVE) |
767 (sense ? OPENPIC_SENSE_LEVEL : OPENPIC_SENSE_EDGE));
771 * Map an interrupt source to one or more CPUs
773 static void openpic_mapirq(u_int irq, u_int physmask, u_int keepmask)
778 physmask |= openpic_read(&ISR[irq]->Destination) & keepmask;
779 openpic_write(&ISR[irq]->Destination, physmask);
784 * Set the sense for an interrupt source (and disable it!)
786 * sense: 1 for level, 0 for edge
788 static void openpic_set_sense(u_int irq, int sense)
791 openpic_safe_writefield(&ISR[irq]->Vector_Priority,
793 (sense ? OPENPIC_SENSE_LEVEL : 0));
797 /* No spinlocks, should not be necessary with the OpenPIC
798 * (1 register = 1 interrupt and we have the desc lock).
800 static void openpic_ack_irq(unsigned int irq_nr)
802 #ifdef __SLOW_VERSION__
803 openpic_disable_irq(irq_nr);
806 if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0)
811 static void openpic_end_irq(unsigned int irq_nr)
813 #ifdef __SLOW_VERSION__
814 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
815 && irq_desc[irq_nr].action)
816 openpic_enable_irq(irq_nr);
818 if ((irq_desc[irq_nr].status & IRQ_LEVEL) != 0)
823 static void openpic_set_affinity(unsigned int irq_nr, unsigned long cpumask)
825 openpic_mapirq(irq_nr - open_pic_irq_offset, physmask(cpumask), 0);
829 static void openpic_ack_ipi(unsigned int irq_nr)
834 static void openpic_end_ipi(unsigned int irq_nr)
838 static irqreturn_t openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *regs)
840 smp_message_recv(cpl-OPENPIC_VEC_IPI-open_pic_irq_offset, regs);
844 #endif /* CONFIG_SMP */
847 openpic_get_irq(struct pt_regs *regs)
849 int irq = openpic_irq();
852 * Check for the cascade interrupt and call the cascaded
853 * interrupt controller function (usually i8259_irq) if so.
854 * This should move to irq.c eventually. -- paulus
856 if (irq == openpic_cascade_irq && openpic_cascade_fn != NULL) {
857 int cirq = openpic_cascade_fn(regs);
859 /* Allow for the cascade being shared with other devices */
864 } else if (irq == OPENPIC_VEC_SPURIOUS + open_pic_irq_offset)
871 smp_openpic_message_pass(int target, int msg, unsigned long data, int wait)
873 /* make sure we're sending something that translates to an IPI */
875 printk("SMP %d: smp_message_pass: unknown msg %d\n",
876 smp_processor_id(), msg);
881 openpic_cause_IPI(msg, 0xffffffff);
883 case MSG_ALL_BUT_SELF:
884 openpic_cause_IPI(msg,
885 0xffffffff & ~(1 << smp_processor_id()));
888 openpic_cause_IPI(msg, 1<<target);
892 #endif /* CONFIG_SMP */
897 * We implement the IRQ controller as a sysdev and put it
898 * to sleep at powerdown stage (the callback is named suspend,
899 * but it's old semantics, for the Device Model, it's really
900 * powerdown). The possible problem is that another sysdev that
901 * happens to be suspend after this one will have interrupts off,
902 * that may be an issue... For now, this isn't an issue on pmac
906 static u32 save_ipi_vp[OPENPIC_NUM_IPI];
907 static u32 save_irq_src_vp[OPENPIC_MAX_SOURCES];
908 static u32 save_irq_src_dest[OPENPIC_MAX_SOURCES];
909 static u32 save_cpu_task_pri[OPENPIC_MAX_PROCESSORS];
910 static int openpic_suspend_count;
912 static void openpic_cached_enable_irq(u_int irq)
915 save_irq_src_vp[irq - open_pic_irq_offset] &= ~OPENPIC_MASK;
918 static void openpic_cached_disable_irq(u_int irq)
921 save_irq_src_vp[irq - open_pic_irq_offset] |= OPENPIC_MASK;
924 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
925 * we need something better to deal with that... Maybe switch to S1 for
928 int openpic_suspend(struct sys_device *sysdev, u32 state)
933 spin_lock_irqsave(&openpic_setup_lock, flags);
935 if (openpic_suspend_count++ > 0) {
936 spin_unlock_irqrestore(&openpic_setup_lock, flags);
940 open_pic.enable = openpic_cached_enable_irq;
941 open_pic.disable = openpic_cached_disable_irq;
943 for (i=0; i<NumProcessors; i++) {
944 save_cpu_task_pri[i] = openpic_read(&OpenPIC->Processor[i].Current_Task_Priority);
945 openpic_writefield(&OpenPIC->Processor[i].Current_Task_Priority,
946 OPENPIC_CURRENT_TASK_PRIORITY_MASK, 0xf);
949 for (i=0; i<OPENPIC_NUM_IPI; i++)
950 save_ipi_vp[i] = openpic_read(&OpenPIC->Global.IPI_Vector_Priority(i));
951 for (i=0; i<NumSources; i++) {
954 save_irq_src_vp[i] = openpic_read(&ISR[i]->Vector_Priority) & ~OPENPIC_ACTIVITY;
955 save_irq_src_dest[i] = openpic_read(&ISR[i]->Destination);
958 spin_unlock_irqrestore(&openpic_setup_lock, flags);
963 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
964 * we need something better to deal with that... Maybe switch to S1 for
967 int openpic_resume(struct sys_device *sysdev)
971 u32 vppmask = OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
972 OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK |
975 spin_lock_irqsave(&openpic_setup_lock, flags);
977 if ((--openpic_suspend_count) > 0) {
978 spin_unlock_irqrestore(&openpic_setup_lock, flags);
984 /* OpenPIC sometimes seem to need some time to be fully back up... */
986 openpic_set_spurious(OPENPIC_VEC_SPURIOUS+open_pic_irq_offset);
987 } while(openpic_readfield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK)
988 != (OPENPIC_VEC_SPURIOUS + open_pic_irq_offset));
990 openpic_disable_8259_pass_through();
992 for (i=0; i<OPENPIC_NUM_IPI; i++)
993 openpic_write(&OpenPIC->Global.IPI_Vector_Priority(i),
995 for (i=0; i<NumSources; i++) {
998 openpic_write(&ISR[i]->Destination, save_irq_src_dest[i]);
999 openpic_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
1000 /* make sure mask gets to controller before we return to user */
1002 openpic_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
1003 } while (openpic_readfield(&ISR[i]->Vector_Priority, vppmask)
1004 != (save_irq_src_vp[i] & vppmask));
1006 for (i=0; i<NumProcessors; i++)
1007 openpic_write(&OpenPIC->Processor[i].Current_Task_Priority,
1008 save_cpu_task_pri[i]);
1010 open_pic.enable = openpic_enable_irq;
1011 open_pic.disable = openpic_disable_irq;
1013 spin_unlock_irqrestore(&openpic_setup_lock, flags);
1018 #endif /* CONFIG_PM */
1020 static struct sysdev_class openpic_sysclass = {
1021 set_kset_name("openpic"),
1024 static struct sys_device device_openpic = {
1026 .cls = &openpic_sysclass,
1029 static struct sysdev_driver driver_openpic = {
1031 .suspend = &openpic_suspend,
1032 .resume = &openpic_resume,
1033 #endif /* CONFIG_PM */
1036 static int __init init_openpic_sysfs(void)
1042 printk(KERN_DEBUG "Registering openpic with sysfs...\n");
1043 rc = sysdev_class_register(&openpic_sysclass);
1045 printk(KERN_ERR "Failed registering openpic sys class\n");
1048 rc = sysdev_register(&device_openpic);
1050 printk(KERN_ERR "Failed registering openpic sys device\n");
1053 rc = sysdev_driver_register(&openpic_sysclass, &driver_openpic);
1055 printk(KERN_ERR "Failed registering openpic sys driver\n");
1061 subsys_initcall(init_openpic_sysfs);