3 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
5 * Module name: ppc4xx_pic.c
8 * Interrupt controller driver for PowerPC 4xx-based processors.
12 * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
13 * 32 possible interrupts, a majority of which are not implemented on
14 * all cores. There are six configurable, external interrupt pins and
15 * there are eight internal interrupts for the on-chip serial port
16 * (SPU), DMA controller, and JTAG controller.
18 * The PowerPC 405/440 cores' Universal Interrupt Controller (UIC) has
19 * 32 possible interrupts as well. Depending on the core and SoC
20 * implementation, a portion of the interrrupts are used for on-chip
21 * peripherals and a portion of the interrupts are available to be
22 * configured for external devices generating interrupts.
24 * The PowerNP and 440GP (and most likely future implementations) have
29 #include <linux/init.h>
30 #include <linux/sched.h>
31 #include <linux/signal.h>
32 #include <linux/stddef.h>
34 #include <asm/processor.h>
35 #include <asm/system.h>
37 #include <asm/ppc4xx_pic.h>
39 /* Global Variables */
40 struct hw_interrupt_type *ppc4xx_pic;
42 * We define 4xxIRQ_InitSenses table thusly:
43 * bit 0x1: sense, 1 for edge and 0 for level.
44 * bit 0x2: polarity, 0 for negative, 1 for positive.
46 unsigned int ibm4xxPIC_NumInitSenses __initdata = 0;
47 unsigned char *ibm4xxPIC_InitSenses __initdata = NULL;
49 /* Six of one, half dozen of the other....#ifdefs, separate files,
52 * There are basically two types of interrupt controllers, the 403 AIC
53 * and the "others" with UIC. I just kept them both here separated
54 * with #ifdefs, but it seems to change depending upon how supporting
55 * files (like ppc4xx.h) change. -- Dan.
60 /* Function Prototypes */
62 static void ppc403_aic_enable(unsigned int irq);
63 static void ppc403_aic_disable(unsigned int irq);
64 static void ppc403_aic_disable_and_ack(unsigned int irq);
66 static struct hw_interrupt_type ppc403_aic = {
72 ppc403_aic_disable_and_ack,
77 ppc403_pic_get_irq(struct pt_regs *regs)
83 * Only report the status of those interrupts that are actually
87 bits = mfdcr(DCRN_EXISR) & mfdcr(DCRN_EXIER);
90 * Walk through the interrupts from highest priority to lowest, and
91 * report the first pending interrupt found.
92 * We want PPC, not C bit numbering, so just subtract the ffs()
97 if (irq == NR_AIC_IRQS)
104 ppc403_aic_enable(unsigned int irq)
111 ppc_cached_irq_mask[word] |= (1 << (31 - bit));
112 mtdcr(DCRN_EXIER, ppc_cached_irq_mask[word]);
116 ppc403_aic_disable(unsigned int irq)
123 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
124 mtdcr(DCRN_EXIER, ppc_cached_irq_mask[word]);
128 ppc403_aic_disable_and_ack(unsigned int irq)
135 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
136 mtdcr(DCRN_EXIER, ppc_cached_irq_mask[word]);
137 mtdcr(DCRN_EXISR, (1 << (31 - bit)));
150 ppc4xx_uic_enable(unsigned int irq)
153 irq_desc_t *desc = irq_desc + irq;
159 printk("ppc4xx_uic_enable - irq %d word %d bit 0x%x\n", irq, word, bit);
161 ppc_cached_irq_mask[word] |= 1 << (31 - bit);
164 mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]);
165 if ((mfdcr(DCRN_UIC_TR(UIC0)) & (1 << (31 - bit))) == 0)
166 desc->status |= IRQ_LEVEL;
168 desc->status = desc->status & ~IRQ_LEVEL;
171 mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]);
172 if ((mfdcr(DCRN_UIC_TR(UIC1)) & (1 << (31 - bit))) == 0)
173 desc->status |= IRQ_LEVEL;
175 desc->status = desc->status & ~IRQ_LEVEL;
178 mtdcr(DCRN_UIC_ER(UIC2), ppc_cached_irq_mask[word]);
179 if ((mfdcr(DCRN_UIC_TR(UIC2)) & (1 << (31 - bit))) == 0)
180 desc->status |= IRQ_LEVEL;
182 desc->status = desc->status & ~IRQ_LEVEL;
189 ppc4xx_uic_disable(unsigned int irq)
196 printk("ppc4xx_uic_disable - irq %d word %d bit 0x%x\n", irq, word,
199 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
202 mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]);
205 mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]);
208 mtdcr(DCRN_UIC_ER(UIC2), ppc_cached_irq_mask[word]);
214 ppc4xx_uic_disable_and_ack(unsigned int irq)
222 printk("ppc4xx_uic_disable_and_ack - irq %d word %d bit 0x%x\n", irq,
225 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
228 mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]);
229 mtdcr(DCRN_UIC_SR(UIC0), (1 << (31 - bit)));
231 mtdcr(DCRN_UIC_SR(UICB), UICB_UIC0NC);
235 mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]);
236 mtdcr(DCRN_UIC_SR(UIC1), (1 << (31 - bit)));
238 mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC);
242 mtdcr(DCRN_UIC_ER(UIC2), ppc_cached_irq_mask[word]);
243 mtdcr(DCRN_UIC_SR(UIC2), (1 << (31 - bit)));
245 mtdcr(DCRN_UIC_SR(UICB), UICB_UIC2NC);
253 ppc4xx_uic_end(unsigned int irq)
256 unsigned int tr_bits;
262 printk("ppc4xx_uic_end - irq %d word %d bit 0x%x\n", irq, word, bit);
267 tr_bits = mfdcr(DCRN_UIC_TR(UIC0));
270 tr_bits = mfdcr(DCRN_UIC_TR(UIC1));
273 tr_bits = mfdcr(DCRN_UIC_TR(UIC2));
277 if ((tr_bits & (1 << (31 - bit))) == 0) {
281 mtdcr(DCRN_UIC_SR(UIC0), 1 << (31 - bit));
283 mtdcr(DCRN_UIC_SR(UICB), UICB_UIC0NC);
287 mtdcr(DCRN_UIC_SR(UIC1), 1 << (31 - bit));
289 mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC);
293 mtdcr(DCRN_UIC_SR(UIC2), 1 << (31 - bit));
295 mtdcr(DCRN_UIC_SR(UICB), UICB_UIC2NC);
301 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
302 ppc_cached_irq_mask[word] |= 1 << (31 - bit);
305 mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]);
308 mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]);
311 mtdcr(DCRN_UIC_ER(UIC2), ppc_cached_irq_mask[word]);
317 static struct hw_interrupt_type ppc4xx_uic = {
327 ppc4xx_uic_disable_and_ack,
333 ppc4xx_pic_get_irq(struct pt_regs *regs)
339 * Only report the status of those interrupts that are actually
344 bits = mfdcr(DCRN_UIC_MSR(UICB));
346 bits = mfdcr(DCRN_UIC_MSR(UIC0));
349 if (bits & UICB_UIC0NC) {
350 bits = mfdcr(DCRN_UIC_MSR(UIC0));
351 irq = 32 - ffs(bits);
352 } else if (bits & UICB_UIC1NC) {
353 bits = mfdcr(DCRN_UIC_MSR(UIC1));
354 irq = 64 - ffs(bits);
355 } else if (bits & UICB_UIC2NC) {
356 bits = mfdcr(DCRN_UIC_MSR(UIC2));
357 irq = 96 - ffs(bits);
362 if (bits & UIC_CASCADE_MASK) {
363 bits = mfdcr(DCRN_UIC_MSR(UIC1));
364 cas_irq = 32 - ffs(bits);
367 irq = 32 - ffs(bits);
373 * Walk through the interrupts from highest priority to lowest, and
374 * report the first pending interrupt found.
375 * We want PPC, not C bit numbering, so just subtract the ffs()
378 irq = 32 - ffs(bits);
380 if (irq == (NR_UIC_IRQS * NR_UICS))
384 printk("ppc4xx_pic_get_irq - irq %d bit 0x%x\n", irq, bits);
392 ppc4xx_extpic_init(void)
395 * 1 = default/pos/rising , 0= neg/falling internal
396 * 1 = neg/falling , 0= pos/rising external
398 * 0 = default level internal
399 * 0 = level, 1 = edge external
402 unsigned int sense, irq;
404 unsigned long ppc_cached_sense_mask[NR_MASK_WORDS];
405 unsigned long ppc_cached_pol_mask[NR_MASK_WORDS];
406 ppc_cached_sense_mask[0] = 0;
407 ppc_cached_sense_mask[1] = 0;
408 ppc_cached_sense_mask[2] = 0;
409 ppc_cached_pol_mask[0] = 0;
410 ppc_cached_pol_mask[1] = 0;
411 ppc_cached_pol_mask[2] = 0;
413 for (irq = 0; irq < NR_IRQS; irq++) {
420 ibm4xxPIC_NumInitSenses) ? ibm4xxPIC_InitSenses[irq] : 3;
421 #ifdef PPC4xx_PIC_DEBUG
422 printk("PPC4xx_picext %d word:%x bit:%x sense:%x", irq, word,
425 ppc_cached_sense_mask[word] |=
426 (sense & IRQ_SENSE_MASK) << (31 - bit);
427 ppc_cached_pol_mask[word] |=
428 ((sense & IRQ_POLARITY_MASK) >> 1) << (31 - bit);
431 #ifdef PPC4xx_PIC_DEBUG
432 printk("Pol %x ", mfdcr(DCRN_UIC_PR(UIC0)));
433 printk("Level %x\n", mfdcr(DCRN_UIC_TR(UIC0)));
435 /* polarity setting */
436 mtdcr(DCRN_UIC_PR(UIC0), ppc_cached_pol_mask[word]);
439 mtdcr(DCRN_UIC_TR(UIC0), ppc_cached_sense_mask[word]);
443 #ifdef PPC4xx_PIC_DEBUG
444 printk("Pol %x ", mfdcr(DCRN_UIC_PR(UIC1)));
445 printk("Level %x\n", mfdcr(DCRN_UIC_TR(UIC1)));
447 /* polarity setting */
448 mtdcr(DCRN_UIC_PR(UIC1), ppc_cached_pol_mask[word]);
451 mtdcr(DCRN_UIC_TR(UIC1), ppc_cached_sense_mask[word]);
455 #ifdef PPC4xx_PIC_DEBUG
456 printk("Pol %x ", mfdcr(DCRN_UIC_PR(UIC2)));
457 printk("Level %x\n", mfdcr(DCRN_UIC_TR(UIC2)));
459 /* polarity setting */
460 mtdcr(DCRN_UIC_PR(UIC2), ppc_cached_pol_mask[word]);
463 mtdcr(DCRN_UIC_TR(UIC2), ppc_cached_sense_mask[word]);
471 ppc4xx_pic_init(void)
474 * Disable all external interrupts until they are
475 * explicity requested.
477 ppc_cached_irq_mask[0] = 0;
478 ppc_cached_irq_mask[1] = 0;
479 ppc_cached_irq_mask[2] = 0;
481 #if defined CONFIG_403
482 mtdcr(DCRN_EXIER, ppc_cached_irq_mask[0]);
484 ppc4xx_pic = &ppc403_aic;
485 ppc_md.get_irq = ppc403_pic_get_irq;
488 mtdcr(DCRN_UIC_ER(UICB), UICB_UIC0NC | UICB_UIC1NC | UICB_UIC2NC);
489 mtdcr(DCRN_UIC_CR(UICB), 0);
491 mtdcr(DCRN_UIC_ER(UIC2), ppc_cached_irq_mask[2]);
492 mtdcr(DCRN_UIC_CR(UIC2), 0);
497 /* enable cascading interrupt */
498 ppc_cached_irq_mask[0] |= 1 << (31 - UIC0_UIC1NC);
500 mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[1]);
501 mtdcr(DCRN_UIC_CR(UIC1), 0);
503 mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]);
504 mtdcr(DCRN_UIC_CR(UIC0), 0);
506 if (ibm4xxPIC_InitSenses != NULL)
507 ppc4xx_extpic_init();
509 /* Clear any pending interrupts */
511 mtdcr(DCRN_UIC_SR(UICB), 0xffffffff);
512 mtdcr(DCRN_UIC_SR(UIC2), 0xffffffff);
515 mtdcr(DCRN_UIC_SR(UIC1), 0xffffffff);
517 mtdcr(DCRN_UIC_SR(UIC0), 0xffffffff);
519 ppc4xx_pic = &ppc4xx_uic;
520 ppc_md.get_irq = ppc4xx_pic_get_irq;