3 * Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
5 * Copyright 2000-2001 MontaVista Software Inc.
6 * Completed implementation.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * Frank Rowand <frank_rowand@mvista.com>
9 * Debbie Chu <debbie_chu@mvista.com>
10 * Further modifications by Armin Kuster
12 * Module name: ppc4xx_setup.c
16 #include <linux/config.h>
17 #include <linux/init.h>
18 #include <linux/smp.h>
19 #include <linux/threads.h>
20 #include <linux/spinlock.h>
21 #include <linux/irq.h>
22 #include <linux/reboot.h>
23 #include <linux/param.h>
24 #include <linux/string.h>
25 #include <linux/initrd.h>
26 #include <linux/pci.h>
27 #include <linux/rtc.h>
28 #include <linux/console.h>
29 #include <linux/ide.h>
30 #include <linux/serial_reg.h>
31 #include <linux/seq_file.h>
33 #include <asm/system.h>
34 #include <asm/processor.h>
35 #include <asm/machdep.h>
38 #include <asm/ibm4xx.h>
41 #include <asm/ppc4xx_pic.h>
42 #include <asm/pci-bridge.h>
43 #include <asm/bootinfo.h>
45 #include <syslib/gen550.h>
47 /* Function Prototypes */
48 extern void abort(void);
49 extern void ppc4xx_find_bridges(void);
51 extern void ppc4xx_wdt_heartbeat(void);
52 extern int wdt_enable;
53 extern unsigned long wdt_period;
55 /* Global Variables */
59 ppc4xx_setup_arch(void)
61 #if !defined(CONFIG_BDI_SWITCH)
63 * The Abatron BDI JTAG debugger does not tolerate others
64 * mucking with the debug registers.
66 mtspr(SPRN_DBCR0, (DBCR0_IDM));
67 mtspr(SPRN_DBSR, 0xffffffff);
70 /* Setup PCI host bridges */
72 ppc4xx_find_bridges();
77 * This routine pretty-prints the platform's internal CPU clock
78 * frequencies into the buffer for usage in /proc/cpuinfo.
82 ppc4xx_show_percpuinfo(struct seq_file *m, int i)
84 seq_printf(m, "clock\t\t: %ldMHz\n", (long)__res.bi_intfreq / 1000000);
90 * This routine pretty-prints the platform's internal bus clock
91 * frequencies into the buffer for usage in /proc/cpuinfo.
94 ppc4xx_show_cpuinfo(struct seq_file *m)
98 seq_printf(m, "machine\t\t: %s\n", PPC4xx_MACHINE_NAME);
99 seq_printf(m, "plb bus clock\t: %ldMHz\n",
100 (long) bip->bi_busfreq / 1000000);
102 seq_printf(m, "pci bus clock\t: %dMHz\n",
103 bip->bi_pci_busfreq / 1000000);
110 * Return the virtual address representing the top of physical RAM.
112 static unsigned long __init
113 ppc4xx_find_end_of_memory(void)
115 return ((unsigned long) __res.bi_memsize);
121 io_block_mapping(PPC4xx_ONB_IO_VADDR,
122 PPC4xx_ONB_IO_PADDR, PPC4xx_ONB_IO_SIZE, _PAGE_IO);
124 io_block_mapping(PPC4xx_PCI_IO_VADDR,
125 PPC4xx_PCI_IO_PADDR, PPC4xx_PCI_IO_SIZE, _PAGE_IO);
126 io_block_mapping(PPC4xx_PCI_CFG_VADDR,
127 PPC4xx_PCI_CFG_PADDR, PPC4xx_PCI_CFG_SIZE, _PAGE_IO);
128 io_block_mapping(PPC4xx_PCI_LCFG_VADDR,
129 PPC4xx_PCI_LCFG_PADDR, PPC4xx_PCI_LCFG_SIZE, _PAGE_IO);
134 ppc4xx_init_IRQ(void)
140 for (i = 0; i < NR_IRQS; i++)
141 irq_desc[i].handler = ppc4xx_pic;
145 ppc4xx_restart(char *cmd)
152 ppc4xx_power_off(void)
154 printk("System Halted\n");
162 printk("System Halted\n");
168 * This routine retrieves the internal processor frequency from the board
169 * information structure, sets up the kernel timer decrementer based on
170 * that value, enables the 4xx programmable interval timer (PIT) and sets
171 * it up for auto-reload.
174 ppc4xx_calibrate_decr(void)
179 #if defined(CONFIG_WALNUT) || defined(CONFIG_ASH) || defined(CONFIG_SYCAMORE)
180 /* Walnut boot rom sets DCR CHCR1 (aka CPC0_CR1) bit CETE to 1 */
181 mtdcr(DCRN_CHCR1, mfdcr(DCRN_CHCR1) & ~CHR1_CETE);
183 freq = bip->bi_tbfreq;
184 tb_ticks_per_jiffy = freq / HZ;
185 tb_to_us = mulhwu_scale_factor(freq, 1000000);
187 /* Set the time base to zero.
188 ** At 200 Mhz, time base will rollover in ~2925 years.
194 /* Clear any pending timer interrupts */
196 mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_PIS | TSR_FIS);
197 mtspr(SPRN_TCR, TCR_PIE | TCR_ARE);
199 /* Set the PIT reload value and just let it run. */
200 mtspr(SPRN_PIT, tb_ticks_per_jiffy);
205 * should be generic for every IDE PCI chipset
207 #if defined(CONFIG_PCI) && defined(CONFIG_IDE)
209 ppc4xx_ide_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
210 unsigned long ctrl_port, int *irq)
214 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; ++i)
215 hw->io_ports[i] = data_port + i - IDE_DATA_OFFSET;
217 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
219 #endif /* defined(CONFIG_PCI) && defined(CONFIG_IDE) */
225 * r3 - Optional pointer to a board information structure.
226 * r4 - Optional pointer to the physical starting address of the init RAM
228 * r5 - Optional pointer to the physical ending address of the init RAM
230 * r6 - Optional pointer to the physical starting address of any kernel
231 * command-line parameters.
232 * r7 - Optional pointer to the physical ending address of any kernel
233 * command-line parameters.
236 ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5,
237 unsigned long r6, unsigned long r7)
239 parse_bootinfo(find_bootinfo());
242 * If we were passed in a board information, copy it into the
243 * residual data area.
246 __res = *(bd_t *)(r3 + KERNELBASE);
248 #if defined(CONFIG_BLK_DEV_INITRD)
250 * If the init RAM disk has been configured in, and there's a valid
251 * starting address for it, set it up.
254 initrd_start = r4 + KERNELBASE;
255 initrd_end = r5 + KERNELBASE;
257 #endif /* CONFIG_BLK_DEV_INITRD */
259 /* Copy the kernel command line arguments to a safe place. */
262 *(char *) (r7 + KERNELBASE) = 0;
263 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
265 #if defined(CONFIG_PPC405_WDT)
266 /* Look for wdt= option on command line */
267 if (strstr(cmd_line, "wdt=")) {
270 for (q = cmd_line; (p = strstr(q, "wdt=")) != 0;) {
272 if (p > cmd_line && p[-1] != ' ')
274 wdt_period = simple_strtoul(q, &q, 0);
278 wdt_enable = valid_wdt;
282 /* Initialize machine-dependent vectors */
284 ppc_md.setup_arch = ppc4xx_setup_arch;
285 ppc_md.show_percpuinfo = ppc4xx_show_percpuinfo;
286 ppc_md.show_cpuinfo = ppc4xx_show_cpuinfo;
287 ppc_md.init_IRQ = ppc4xx_init_IRQ;
289 ppc_md.restart = ppc4xx_restart;
290 ppc_md.power_off = ppc4xx_power_off;
291 ppc_md.halt = ppc4xx_halt;
293 ppc_md.calibrate_decr = ppc4xx_calibrate_decr;
295 #ifdef CONFIG_PPC405_WDT
296 ppc_md.heartbeat = ppc4xx_wdt_heartbeat;
298 ppc_md.heartbeat_count = 0;
300 ppc_md.find_end_of_memory = ppc4xx_find_end_of_memory;
301 ppc_md.setup_io_mappings = ppc4xx_map_io;
303 #ifdef CONFIG_SERIAL_TEXT_DEBUG
304 ppc_md.progress = gen550_progress;
307 #if defined(CONFIG_PCI) && defined(CONFIG_IDE)
308 ppc_ide_md.ide_init_hwif = ppc4xx_ide_init_hwif_ports;
309 #endif /* defined(CONFIG_PCI) && defined(CONFIG_IDE) */