2 * arch/ppc/kernel/ppc4xx_sgdma.c
4 * IBM PPC4xx DMA engine scatter/gather library
6 * Copyright 2002-2003 MontaVista Software Inc.
8 * Cleaned up and converted to new DCR access
9 * Matt Porter <mporter@kernel.crashing.org>
11 * Original code by Armin Kuster <akuster@mvista.com>
12 * and Pete Popov <ppopov@mvista.com>
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/config.h>
25 #include <linux/kernel.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
31 #include <asm/system.h>
33 #include <asm/ppc4xx_dma.h>
36 ppc4xx_set_sg_addr(int dmanr, phys_addr_t sg_addr)
38 if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
39 printk("ppc4xx_set_sg_addr: bad channel: %d\n", dmanr);
43 #ifdef PPC4xx_DMA_64BIT
44 mtdcr(DCRN_ASGH0 + (dmanr * 0x8), (u32)(sg_addr >> 32));
46 mtdcr(DCRN_ASG0 + (dmanr * 0x8), (u32)sg_addr);
50 * Add a new sgl descriptor to the end of a scatter/gather list
51 * which was created by alloc_dma_handle().
53 * For a memory to memory transfer, both dma addresses must be
54 * valid. For a peripheral to memory transfer, one of the addresses
55 * must be set to NULL, depending on the direction of the transfer:
56 * memory to peripheral: set dst_addr to NULL,
57 * peripheral to memory: set src_addr to NULL.
60 ppc4xx_add_dma_sgl(sgl_handle_t handle, phys_addr_t src_addr, phys_addr_t dst_addr,
63 sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
64 ppc_dma_ch_t *p_dma_ch;
67 printk("ppc4xx_add_dma_sgl: null handle\n");
68 return DMA_STATUS_BAD_HANDLE;
71 if (psgl->dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
72 printk("ppc4xx_add_dma_sgl: bad channel: %d\n", psgl->dmanr);
73 return DMA_STATUS_BAD_CHANNEL;
76 p_dma_ch = &dma_channels[psgl->dmanr];
81 unsigned int aligned =
82 (unsigned) src_addr | (unsigned) dst_addr | count;
83 switch (p_dma_ch->pwidth) {
99 printk("ppc4xx_add_dma_sgl: invalid bus width: 0x%x\n",
101 return DMA_STATUS_GENERAL_ERROR;
105 ("Alignment warning: ppc4xx_add_dma_sgl src 0x%x dst 0x%x count 0x%x bus width var %d\n",
106 src_addr, dst_addr, count, p_dma_ch->pwidth);
111 if ((unsigned) (psgl->ptail + 1) >= ((unsigned) psgl + SGL_LIST_SIZE)) {
112 printk("sgl handle out of memory \n");
113 return DMA_STATUS_OUT_OF_MEMORY;
117 psgl->phead = (ppc_sgl_t *)
118 ((unsigned) psgl + sizeof (sgl_list_info_t));
119 psgl->phead_dma = psgl->dma_addr + sizeof(sgl_list_info_t);
120 psgl->ptail = psgl->phead;
121 psgl->ptail_dma = psgl->phead_dma;
123 psgl->ptail->next = psgl->ptail_dma + sizeof(ppc_sgl_t);
125 psgl->ptail_dma += sizeof(ppc_sgl_t);
128 psgl->ptail->control = psgl->control;
129 psgl->ptail->src_addr = src_addr;
130 psgl->ptail->dst_addr = dst_addr;
131 psgl->ptail->control_count = (count >> p_dma_ch->shift) |
133 psgl->ptail->next = (uint32_t) NULL;
135 return DMA_STATUS_GOOD;
139 * Enable (start) the DMA described by the sgl handle.
142 ppc4xx_enable_dma_sgl(sgl_handle_t handle)
144 sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
145 ppc_dma_ch_t *p_dma_ch;
149 printk("ppc4xx_enable_dma_sgl: null handle\n");
151 } else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) {
152 printk("ppc4xx_enable_dma_sgl: bad channel in handle %d\n",
155 } else if (!psgl->phead) {
156 printk("ppc4xx_enable_dma_sgl: sg list empty\n");
160 p_dma_ch = &dma_channels[psgl->dmanr];
161 psgl->ptail->control_count &= ~SG_LINK; /* make this the last dscrptr */
162 sg_command = mfdcr(DCRN_ASGC);
164 ppc4xx_set_sg_addr(psgl->dmanr, psgl->phead_dma);
166 sg_command |= SSG_ENABLE(psgl->dmanr);
168 mtdcr(DCRN_ASGC, sg_command); /* start transfer */
172 * Halt an active scatter/gather DMA operation.
175 ppc4xx_disable_dma_sgl(sgl_handle_t handle)
177 sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
181 printk("ppc4xx_enable_dma_sgl: null handle\n");
183 } else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) {
184 printk("ppc4xx_enable_dma_sgl: bad channel in handle %d\n",
189 sg_command = mfdcr(DCRN_ASGC);
190 sg_command &= ~SSG_ENABLE(psgl->dmanr);
191 mtdcr(DCRN_ASGC, sg_command); /* stop transfer */
195 * Returns number of bytes left to be transferred from the entire sgl list.
196 * *src_addr and *dst_addr get set to the source/destination address of
197 * the sgl descriptor where the DMA stopped.
199 * An sgl transfer must NOT be active when this function is called.
202 ppc4xx_get_dma_sgl_residue(sgl_handle_t handle, phys_addr_t * src_addr,
203 phys_addr_t * dst_addr)
205 sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
206 ppc_dma_ch_t *p_dma_ch;
207 ppc_sgl_t *pnext, *sgl_addr;
211 printk("ppc4xx_get_dma_sgl_residue: null handle\n");
212 return DMA_STATUS_BAD_HANDLE;
213 } else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) {
214 printk("ppc4xx_get_dma_sgl_residue: bad channel in handle %d\n",
216 return DMA_STATUS_BAD_CHANNEL;
219 sgl_addr = (ppc_sgl_t *) __va(mfdcr(DCRN_ASG0 + (psgl->dmanr * 0x8)));
220 count_left = mfdcr(DCRN_DMACT0 + (psgl->dmanr * 0x8));
223 printk("ppc4xx_get_dma_sgl_residue: sgl addr register is null\n");
229 ((unsigned) pnext < ((unsigned) psgl + SGL_LIST_SIZE) &&
235 if (pnext == sgl_addr) { /* found the sgl descriptor */
237 *src_addr = pnext->src_addr;
238 *dst_addr = pnext->dst_addr;
241 * Now search the remaining descriptors and add their count.
242 * We already have the remaining count from this descriptor in
247 while ((pnext != psgl->ptail) &&
248 ((unsigned) pnext < ((unsigned) psgl + SGL_LIST_SIZE))
250 count_left += pnext->control_count & SG_COUNT_MASK;
253 if (pnext != psgl->ptail) { /* should never happen */
255 ("ppc4xx_get_dma_sgl_residue error (1) psgl->ptail 0x%x handle 0x%x\n",
256 (unsigned int) psgl->ptail, (unsigned int) handle);
261 p_dma_ch = &dma_channels[psgl->dmanr];
262 return (count_left << p_dma_ch->shift); /* count in bytes */
265 /* this shouldn't happen */
267 ("get_dma_sgl_residue, unable to match current address 0x%x, handle 0x%x\n",
268 (unsigned int) sgl_addr, (unsigned int) handle);
273 *src_addr = (phys_addr_t) NULL;
274 *dst_addr = (phys_addr_t) NULL;
279 * Returns the address(es) of the buffer(s) contained in the head element of
280 * the scatter/gather list. The element is removed from the scatter/gather
281 * list and the next element becomes the head.
283 * This function should only be called when the DMA is not active.
286 ppc4xx_delete_dma_sgl_element(sgl_handle_t handle, phys_addr_t * src_dma_addr,
287 phys_addr_t * dst_dma_addr)
289 sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
292 printk("ppc4xx_delete_sgl_element: null handle\n");
293 return DMA_STATUS_BAD_HANDLE;
294 } else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) {
295 printk("ppc4xx_delete_sgl_element: bad channel in handle %d\n",
297 return DMA_STATUS_BAD_CHANNEL;
301 printk("ppc4xx_delete_sgl_element: sgl list empty\n");
302 *src_dma_addr = (phys_addr_t) NULL;
303 *dst_dma_addr = (phys_addr_t) NULL;
304 return DMA_STATUS_SGL_LIST_EMPTY;
307 *src_dma_addr = (phys_addr_t) psgl->phead->src_addr;
308 *dst_dma_addr = (phys_addr_t) psgl->phead->dst_addr;
310 if (psgl->phead == psgl->ptail) {
311 /* last descriptor on the list */
316 psgl->phead_dma += sizeof(ppc_sgl_t);
319 return DMA_STATUS_GOOD;
324 * Create a scatter/gather list handle. This is simply a structure which
325 * describes a scatter/gather list.
327 * A handle is returned in "handle" which the driver should save in order to
328 * be able to access this list later. A chunk of memory will be allocated
329 * to be used by the API for internal management purposes, including managing
330 * the sg list and allocating memory for the sgl descriptors. One page should
331 * be more than enough for that purpose. Perhaps it's a bit wasteful to use
332 * a whole page for a single sg list, but most likely there will be only one
333 * sg list per channel.
336 * Each sgl descriptor has a copy of the DMA control word which the DMA engine
337 * loads in the control register. The control word has a "global" interrupt
338 * enable bit for that channel. Interrupts are further qualified by a few bits
339 * in the sgl descriptor count register. In order to setup an sgl, we have to
340 * know ahead of time whether or not interrupts will be enabled at the completion
341 * of the transfers. Thus, enable_dma_interrupt()/disable_dma_interrupt() MUST
342 * be called before calling alloc_dma_handle(). If the interrupt mode will never
343 * change after powerup, then enable_dma_interrupt()/disable_dma_interrupt()
344 * do not have to be called -- interrupts will be enabled or disabled based
345 * on how the channel was configured after powerup by the hw_init_dma_channel()
346 * function. Each sgl descriptor will be setup to interrupt if an error occurs;
347 * however, only the last descriptor will be setup to interrupt. Thus, an
348 * interrupt will occur (if interrupts are enabled) only after the complete
349 * sgl transfer is done.
352 ppc4xx_alloc_dma_handle(sgl_handle_t * phandle, unsigned int mode, unsigned int dmanr)
354 sgl_list_info_t *psgl;
356 ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
360 if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
361 printk("ppc4xx_alloc_dma_handle: invalid channel 0x%x\n", dmanr);
362 return DMA_STATUS_BAD_CHANNEL;
366 printk("ppc4xx_alloc_dma_handle: null handle pointer\n");
367 return DMA_STATUS_NULL_POINTER;
370 /* Get a page of memory, which is zeroed out by consistent_alloc() */
371 ret = dma_alloc_coherent(NULL, DMA_PPC4xx_SIZE, &dma_addr, GFP_KERNEL);
373 memset(ret, 0, DMA_PPC4xx_SIZE);
374 psgl = (sgl_list_info_t *) ret;
378 *phandle = (sgl_handle_t) NULL;
379 return DMA_STATUS_OUT_OF_MEMORY;
382 psgl->dma_addr = dma_addr;
386 * Modify and save the control word. These words will be
387 * written to each sgl descriptor. The DMA engine then
388 * loads this control word into the control register
389 * every time it reads a new descriptor.
391 psgl->control = p_dma_ch->control;
392 /* Clear all mode bits */
393 psgl->control &= ~(DMA_TM_MASK | DMA_TD);
394 /* Save control word and mode */
395 psgl->control |= (mode | DMA_CE_ENABLE);
397 /* In MM mode, we must set ETD/TCE */
398 if (mode == DMA_MODE_MM)
399 psgl->control |= DMA_ETD_OUTPUT | DMA_TCE_ENABLE;
401 if (p_dma_ch->int_enable) {
402 /* Enable channel interrupt */
403 psgl->control |= DMA_CIE_ENABLE;
405 psgl->control &= ~DMA_CIE_ENABLE;
408 sg_command = mfdcr(DCRN_ASGC);
409 sg_command |= SSG_MASK_ENABLE(dmanr);
411 /* Enable SGL control access */
412 mtdcr(DCRN_ASGC, sg_command);
413 psgl->sgl_control = SG_ERI_ENABLE | SG_LINK;
415 if (p_dma_ch->int_enable) {
416 if (p_dma_ch->tce_enable)
417 psgl->sgl_control |= SG_TCI_ENABLE;
419 psgl->sgl_control |= SG_ETI_ENABLE;
422 *phandle = (sgl_handle_t) psgl;
423 return DMA_STATUS_GOOD;
427 * Destroy a scatter/gather list handle that was created by alloc_dma_handle().
428 * The list must be empty (contain no elements).
431 ppc4xx_free_dma_handle(sgl_handle_t handle)
433 sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
436 printk("ppc4xx_free_dma_handle: got NULL\n");
438 } else if (psgl->phead) {
439 printk("ppc4xx_free_dma_handle: list not empty\n");
441 } else if (!psgl->dma_addr) { /* should never happen */
442 printk("ppc4xx_free_dma_handle: no dma address\n");
446 dma_free_coherent(NULL, DMA_PPC4xx_SIZE, (void *) psgl, 0);
449 EXPORT_SYMBOL(ppc4xx_alloc_dma_handle);
450 EXPORT_SYMBOL(ppc4xx_free_dma_handle);
451 EXPORT_SYMBOL(ppc4xx_add_dma_sgl);
452 EXPORT_SYMBOL(ppc4xx_delete_dma_sgl_element);
453 EXPORT_SYMBOL(ppc4xx_enable_dma_sgl);
454 EXPORT_SYMBOL(ppc4xx_disable_dma_sgl);
455 EXPORT_SYMBOL(ppc4xx_get_dma_sgl_residue);