arch/ppc/syslib/ppc85xx_setup.c

   1 /*
   2  * arch/ppc/syslib/ppc85xx_setup.c
   3  *
   4  * MPC85XX common board code
   5  *
   6  * Maintainer: Kumar Gala <kumar.gala@freescale.com>
   7  *
   8  * Copyright 2004 Freescale Semiconductor Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/types.h>
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/pci.h>
  21 #include <linux/serial.h>
  22 #include <linux/tty.h>  /* for linux/serial_core.h */
  23 #include <linux/serial_core.h>
  24
  25 #include <asm/prom.h>
  26 #include <asm/time.h>
  27 #include <asm/mpc85xx.h>
  28 #include <asm/immap_85xx.h>
  29 #include <asm/mmu.h>
  30 #include <asm/ocp.h>
  31 #include <asm/kgdb.h>
  32
  33 #include <syslib/ppc85xx_setup.h>
  34
  35 /* Return the amount of memory */
  36 unsigned long __init
  37 mpc85xx_find_end_of_memory(void)
  38 {
  39         bd_t *binfo;
  40
  41         binfo = (bd_t *) __res;
  42
  43         return binfo->bi_memsize;
  44 }
  45
  46 /* The decrementer counts at the system (internal) clock freq divided by 8 */
  47 void __init
  48 mpc85xx_calibrate_decr(void)
  49 {
  50         bd_t *binfo = (bd_t *) __res;
  51         unsigned int freq, divisor;
  52
  53         /* get the core frequency */
  54         freq = binfo->bi_busfreq;
  55
  56         /* The timebase is updated every 8 bus clocks, HID0[SEL_TBCLK] = 0 */
  57         divisor = 8;
  58         tb_ticks_per_jiffy = freq / divisor / HZ;
  59         tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
  60
  61         /* Set the time base to zero */
  62         mtspr(SPRN_TBWL, 0);
  63         mtspr(SPRN_TBWU, 0);
  64
  65         /* Clear any pending timer interrupts */
  66         mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
  67
  68         /* Enable decrementer interrupt */
  69         mtspr(SPRN_TCR, TCR_DIE);
  70 }
  71
  72 #ifdef CONFIG_SERIAL_8250
  73 void __init
  74 mpc85xx_early_serial_map(void)
  75 {
  76         struct uart_port serial_req;
  77         bd_t *binfo = (bd_t *) __res;
  78         phys_addr_t duart_paddr = binfo->bi_immr_base + MPC85xx_UART0_OFFSET;
  79
  80         /* Setup serial port access */
  81         memset(&serial_req, 0, sizeof (serial_req));
  82         serial_req.uartclk = binfo->bi_busfreq;
  83         serial_req.line = 0;
  84         serial_req.irq = MPC85xx_IRQ_DUART;
  85         serial_req.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
  86         serial_req.iotype = SERIAL_IO_MEM;
  87         serial_req.membase = ioremap(duart_paddr, MPC85xx_UART0_SIZE);
  88         serial_req.mapbase = duart_paddr;
  89         serial_req.regshift = 0;
  90
  91 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
  92         gen550_init(0, &serial_req);
  93 #endif
  94
  95         if (early_serial_setup(&serial_req) != 0)
  96                 printk("Early serial init of port 0 failed\n");
  97
  98         /* Assume early_serial_setup() doesn't modify serial_req */
  99         duart_paddr = binfo->bi_immr_base + MPC85xx_UART1_OFFSET;
 100         serial_req.line = 1;
 101         serial_req.mapbase = duart_paddr;
 102         serial_req.membase = ioremap(duart_paddr, MPC85xx_UART1_SIZE);
 103
 104 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 105         gen550_init(1, &serial_req);
 106 #endif
 107
 108         if (early_serial_setup(&serial_req) != 0)
 109                 printk("Early serial init of port 1 failed\n");
 110 }
 111 #endif
 112
 113 void
 114 mpc85xx_restart(char *cmd)
 115 {
 116         local_irq_disable();
 117         abort();
 118 }
 119
 120 void
 121 mpc85xx_power_off(void)
 122 {
 123         local_irq_disable();
 124         for(;;);
 125 }
 126
 127 void
 128 mpc85xx_halt(void)
 129 {
 130         local_irq_disable();
 131         for(;;);
 132 }
 133
 134 #ifdef CONFIG_PCI
 135 static void __init
 136 mpc85xx_setup_pci1(struct pci_controller *hose)
 137 {
 138         volatile struct ccsr_pci *pci;
 139         volatile struct ccsr_guts *guts;
 140         unsigned short temps;
 141         bd_t *binfo = (bd_t *) __res;
 142
 143         pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI1_OFFSET,
 144                     MPC85xx_PCI1_SIZE);
 145
 146         guts = ioremap(binfo->bi_immr_base + MPC85xx_GUTS_OFFSET,
 147                     MPC85xx_GUTS_SIZE);
 148
 149         early_read_config_word(hose, 0, 0, PCI_COMMAND, &temps);
 150         temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 151         early_write_config_word(hose, 0, 0, PCI_COMMAND, temps);
 152
 153 #define PORDEVSR_PCI    (0x00800000)    /* PCI Mode */
 154         if (guts->pordevsr & PORDEVSR_PCI) {
 155                 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
 156         } else {
 157                 /* PCI-X init */
 158                 temps = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
 159                         | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
 160                 early_write_config_word(hose, 0, 0, PCIX_COMMAND, temps);
 161         }
 162
 163         /* Disable all windows (except powar0 since its ignored) */
 164         pci->powar1 = 0;
 165         pci->powar2 = 0;
 166         pci->powar3 = 0;
 167         pci->powar4 = 0;
 168         pci->piwar1 = 0;
 169         pci->piwar2 = 0;
 170         pci->piwar3 = 0;
 171
 172         /* Setup 512M Phys:PCI 1:1 outbound mem window @ 0x80000000 */
 173         pci->potar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
 174         pci->potear1 = 0x00000000;
 175         pci->powbar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
 176         pci->powar1 = 0x8004401c;       /* Enable, Mem R/W, 512M */
 177
 178         /* Setup 16M outboud IO windows @ 0xe2000000 */
 179         pci->potar2 = 0x00000000;
 180         pci->potear2 = 0x00000000;
 181         pci->powbar2 = (MPC85XX_PCI1_IO_BASE >> 12) & 0x000fffff;
 182         pci->powar2 = 0x80088017;       /* Enable, IO R/W, 16M */
 183
 184         /* Setup 2G inbound Memory Window @ 0 */
 185         pci->pitar1 = 0x00000000;
 186         pci->piwbar1 = 0x00000000;
 187         pci->piwar1 = 0xa0f5501e;       /* Enable, Prefetch, Local
 188                                            Mem, Snoop R/W, 2G */
 189 }
 190
 191
 192 extern int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin);
 193 extern int mpc85xx_exclude_device(u_char bus, u_char devfn);
 194
 195 #if CONFIG_85xx_PCI2
 196 static void __init
 197 mpc85xx_setup_pci2(struct pci_controller *hose)
 198 {
 199         volatile struct ccsr_pci *pci;
 200         unsigned short temps;
 201         bd_t *binfo = (bd_t *) __res;
 202
 203         pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI2_OFFSET,
 204                     MPC85xx_PCI2_SIZE);
 205
 206         early_read_config_word(hose, 0, 0, PCI_COMMAND, &temps);
 207         temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 208         early_write_config_word(hose, 0, 0, PCI_COMMAND, temps);
 209         early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
 210
 211         /* Disable all windows (except powar0 since its ignored) */
 212         pci->powar1 = 0;
 213         pci->powar2 = 0;
 214         pci->powar3 = 0;
 215         pci->powar4 = 0;
 216         pci->piwar1 = 0;
 217         pci->piwar2 = 0;
 218         pci->piwar3 = 0;
 219
 220         /* Setup 512M Phys:PCI 1:1 outbound mem window @ 0xa0000000 */
 221         pci->potar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
 222         pci->potear1 = 0x00000000;
 223         pci->powbar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
 224         pci->powar1 = 0x8004401c;       /* Enable, Mem R/W, 512M */
 225
 226         /* Setup 16M outboud IO windows @ 0xe3000000 */
 227         pci->potar2 = 0x00000000;
 228         pci->potear2 = 0x00000000;
 229         pci->powbar2 = (MPC85XX_PCI2_IO_BASE >> 12) & 0x000fffff;
 230         pci->powar2 = 0x80088017;       /* Enable, IO R/W, 16M */
 231
 232         /* Setup 2G inbound Memory Window @ 0 */
 233         pci->pitar1 = 0x00000000;
 234         pci->piwbar1 = 0x00000000;
 235         pci->piwar1 = 0xa0f5501e;       /* Enable, Prefetch, Local
 236                                            Mem, Snoop R/W, 2G */
 237 }
 238 #endif /* CONFIG_85xx_PCI2 */
 239
 240 void __init
 241 mpc85xx_setup_hose(void)
 242 {
 243         struct pci_controller *hose_a;
 244 #ifdef CONFIG_85xx_PCI2
 245         struct pci_controller *hose_b;
 246 #endif
 247         bd_t *binfo = (bd_t *) __res;
 248
 249         hose_a = pcibios_alloc_controller();
 250
 251         if (!hose_a)
 252                 return;
 253
 254         ppc_md.pci_swizzle = common_swizzle;
 255         ppc_md.pci_map_irq = mpc85xx_map_irq;
 256
 257         hose_a->first_busno = 0;
 258         hose_a->bus_offset = 0;
 259         hose_a->last_busno = 0xff;
 260
 261         setup_indirect_pci(hose_a, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
 262                            binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
 263         hose_a->set_cfg_type = 1;
 264
 265         mpc85xx_setup_pci1(hose_a);
 266
 267         hose_a->pci_mem_offset = MPC85XX_PCI1_MEM_OFFSET;
 268         hose_a->mem_space.start = MPC85XX_PCI1_LOWER_MEM;
 269         hose_a->mem_space.end = MPC85XX_PCI1_UPPER_MEM;
 270
 271         hose_a->io_space.start = MPC85XX_PCI1_LOWER_IO;
 272         hose_a->io_space.end = MPC85XX_PCI1_UPPER_IO;
 273         hose_a->io_base_phys = MPC85XX_PCI1_IO_BASE;
 274 #if CONFIG_85xx_PCI2
 275         isa_io_base =
 276                 (unsigned long) ioremap(MPC85XX_PCI1_IO_BASE,
 277                                         MPC85XX_PCI1_IO_SIZE +
 278                                         MPC85XX_PCI2_IO_SIZE);
 279 #else
 280         isa_io_base =
 281                 (unsigned long) ioremap(MPC85XX_PCI1_IO_BASE,
 282                                         MPC85XX_PCI1_IO_SIZE);
 283 #endif
 284         hose_a->io_base_virt = (void *) isa_io_base;
 285
 286         /* setup resources */
 287         pci_init_resource(&hose_a->mem_resources[0],
 288                         MPC85XX_PCI1_LOWER_MEM,
 289                         MPC85XX_PCI1_UPPER_MEM,
 290                         IORESOURCE_MEM, "PCI1 host bridge");
 291
 292         pci_init_resource(&hose_a->io_resource,
 293                         MPC85XX_PCI1_LOWER_IO,
 294                         MPC85XX_PCI1_UPPER_IO,
 295                         IORESOURCE_IO, "PCI1 host bridge");
 296
 297         ppc_md.pci_exclude_device = mpc85xx_exclude_device;
 298
 299         hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
 300
 301 #if CONFIG_85xx_PCI2
 302         hose_b = pcibios_alloc_controller();
 303
 304         if (!hose_b)
 305                 return;
 306
 307         hose_b->bus_offset = hose_a->last_busno + 1;
 308         hose_b->first_busno = hose_a->last_busno + 1;
 309         hose_b->last_busno = 0xff;
 310
 311         setup_indirect_pci(hose_b, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
 312                            binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
 313         hose_b->set_cfg_type = 1;
 314
 315         mpc85xx_setup_pci2(hose_b);
 316
 317         hose_b->pci_mem_offset = MPC85XX_PCI2_MEM_OFFSET;
 318         hose_b->mem_space.start = MPC85XX_PCI2_LOWER_MEM;
 319         hose_b->mem_space.end = MPC85XX_PCI2_UPPER_MEM;
 320
 321         hose_b->io_space.start = MPC85XX_PCI2_LOWER_IO;
 322         hose_b->io_space.end = MPC85XX_PCI2_UPPER_IO;
 323         hose_b->io_base_phys = MPC85XX_PCI2_IO_BASE;
 324         hose_b->io_base_virt = (void *) isa_io_base + MPC85XX_PCI1_IO_SIZE;
 325
 326         /* setup resources */
 327         pci_init_resource(&hose_b->mem_resources[0],
 328                         MPC85XX_PCI2_LOWER_MEM,
 329                         MPC85XX_PCI2_UPPER_MEM,
 330                         IORESOURCE_MEM, "PCI2 host bridge");
 331
 332         pci_init_resource(&hose_b->io_resource,
 333                         MPC85XX_PCI2_LOWER_IO,
 334                         MPC85XX_PCI2_UPPER_IO,
 335                         IORESOURCE_IO, "PCI2 host bridge");
 336
 337         hose_b->last_busno = pciauto_bus_scan(hose_b, hose_b->first_busno);
 338 #endif
 339         return;
 340 }
 341 #endif /* CONFIG_PCI */
 342
 343