3 * Most 8xx boards use the QSpan PCI bridge. The config address register
4 * is located 0x500 from the base of the bridge control/status registers.
5 * The data register is located at 0x504.
6 * This is a two step operation. First, the address register is written,
7 * then the data register is read/written as required.
8 * I don't know what to do about interrupts (yet).
10 * The RPX Classic implementation shares a chip select for normal
11 * PCI access and QSpan control register addresses. The selection is
12 * further selected by a bit setting in a board control register.
13 * Although it should happen, we disable interrupts during this operation
14 * to make sure some driver doesn't accidentally access the PCI while
15 * we have switched the chip select.
18 #include <linux/config.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/delay.h>
22 #include <linux/string.h>
23 #include <linux/init.h>
26 #include <asm/mpc8xx.h>
27 #include <asm/system.h>
28 #include <asm/machdep.h>
29 #include <asm/pci-bridge.h>
34 * When reading the configuration space, if something does not respond
35 * the bus times out and we get a machine check interrupt. So, the
36 * good ol' exception tables come to mind to trap it and return some
39 * On an error we just return a -1, since that is what the caller wants
40 * returned if nothing is present. I copied this from __get_user_asm,
41 * with the only difference of returning -1 instead of EFAULT.
42 * There is an associated hack in the machine check trap code.
44 * The QSPAN is also a big endian device, that is it makes the PCI
45 * look big endian to us. This presents a problem for the Linux PCI
46 * functions, which assume little endian. For example, we see the
47 * first 32-bit word like this:
48 * ------------------------
49 * | Device ID | Vendor ID |
50 * ------------------------
51 * If we read/write as a double word, that's OK. But in our world,
52 * when read as a word, device ID is at location 0, not location 2 as
53 * the little endian PCI would believe. We have to switch bits in
54 * the PCI addresses given to us to get the data to/from the correct
57 * The QSPAN only supports 4 bits of "slot" in the dev_fn instead of 5.
58 * It always forces the MS bit to zero. Therefore, dev_fn values
59 * greater than 128 are returned as "no device found" errors.
61 * The QSPAN can only perform long word (32-bit) configuration cycles.
62 * The "offset" must have the two LS bits set to zero. Read operations
63 * require we read the entire word and then sort out what should be
64 * returned. Write operations other than long word require that we
65 * read the long word, update the proper word or byte, then write the
66 * entire long word back.
68 * PCI Bridge hack. We assume (correctly) that bus 0 is the primary
69 * PCI bus from the QSPAN. If we are called with a bus number other
70 * than zero, we create a Type 1 configuration access that a downstream
71 * PCI bridge will interpret.
74 #define __get_qspan_pci_config(x, addr, op) \
75 __asm__ __volatile__( \
76 "1: "op" %0,0(%1)\n" \
79 ".section .fixup,\"ax\"\n" \
82 ".section __ex_table,\"a\"\n" \
86 : "=r"(x) : "r"(addr) : " %0")
88 #define QS_CONFIG_ADDR ((volatile uint *)(PCI_CSR_ADDR + 0x500))
89 #define QS_CONFIG_DATA ((volatile uint *)(PCI_CSR_ADDR + 0x504))
91 #define mk_config_addr(bus, dev, offset) \
92 (((bus)<<16) | ((dev)<<8) | (offset & 0xfc))
94 #define mk_config_type1(bus, dev, offset) \
95 mk_config_addr(bus, dev, offset) | 1;
97 int qspan_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn,
98 unsigned char offset, unsigned char *val)
102 #ifdef CONFIG_RPXCLASSIC
106 if ((bus > 7) || (dev_fn > 127)) {
108 return PCIBIOS_DEVICE_NOT_FOUND;
111 #ifdef CONFIG_RPXCLASSIC
114 *((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
119 *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
121 *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
122 __get_qspan_pci_config(temp, QS_CONFIG_DATA, "lwz");
124 #ifdef CONFIG_RPXCLASSIC
125 *((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
127 restore_flags(flags);
131 cp = ((u_char *)&temp) + (offset & 0x03);
133 return PCIBIOS_SUCCESSFUL;
136 int qspan_pcibios_read_config_word(unsigned char bus, unsigned char dev_fn,
137 unsigned char offset, unsigned short *val)
141 #ifdef CONFIG_RPXCLASSIC
145 if ((bus > 7) || (dev_fn > 127)) {
147 return PCIBIOS_DEVICE_NOT_FOUND;
150 #ifdef CONFIG_RPXCLASSIC
153 *((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
158 *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
160 *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
161 __get_qspan_pci_config(temp, QS_CONFIG_DATA, "lwz");
164 #ifdef CONFIG_RPXCLASSIC
165 *((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
167 restore_flags(flags);
170 sp = ((ushort *)&temp) + ((offset >> 1) & 1);
172 return PCIBIOS_SUCCESSFUL;
175 int qspan_pcibios_read_config_dword(unsigned char bus, unsigned char dev_fn,
176 unsigned char offset, unsigned int *val)
178 #ifdef CONFIG_RPXCLASSIC
182 if ((bus > 7) || (dev_fn > 127)) {
184 return PCIBIOS_DEVICE_NOT_FOUND;
187 #ifdef CONFIG_RPXCLASSIC
190 *((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
195 *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
197 *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
198 __get_qspan_pci_config(*val, QS_CONFIG_DATA, "lwz");
200 #ifdef CONFIG_RPXCLASSIC
201 *((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
203 restore_flags(flags);
206 return PCIBIOS_SUCCESSFUL;
209 int qspan_pcibios_write_config_byte(unsigned char bus, unsigned char dev_fn,
210 unsigned char offset, unsigned char val)
214 #ifdef CONFIG_RPXCLASSIC
218 if ((bus > 7) || (dev_fn > 127))
219 return PCIBIOS_DEVICE_NOT_FOUND;
221 qspan_pcibios_read_config_dword(bus, dev_fn, offset, &temp);
224 cp = ((u_char *)&temp) + (offset & 0x03);
227 #ifdef CONFIG_RPXCLASSIC
230 *((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
235 *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
237 *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
238 *QS_CONFIG_DATA = temp;
240 #ifdef CONFIG_RPXCLASSIC
241 *((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
243 restore_flags(flags);
246 return PCIBIOS_SUCCESSFUL;
249 int qspan_pcibios_write_config_word(unsigned char bus, unsigned char dev_fn,
250 unsigned char offset, unsigned short val)
254 #ifdef CONFIG_RPXCLASSIC
258 if ((bus > 7) || (dev_fn > 127))
259 return PCIBIOS_DEVICE_NOT_FOUND;
261 qspan_pcibios_read_config_dword(bus, dev_fn, offset, &temp);
264 sp = ((ushort *)&temp) + ((offset >> 1) & 1);
267 #ifdef CONFIG_RPXCLASSIC
270 *((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
275 *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
277 *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
278 *QS_CONFIG_DATA = temp;
280 #ifdef CONFIG_RPXCLASSIC
281 *((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
283 restore_flags(flags);
286 return PCIBIOS_SUCCESSFUL;
289 int qspan_pcibios_write_config_dword(unsigned char bus, unsigned char dev_fn,
290 unsigned char offset, unsigned int val)
292 #ifdef CONFIG_RPXCLASSIC
296 if ((bus > 7) || (dev_fn > 127))
297 return PCIBIOS_DEVICE_NOT_FOUND;
299 #ifdef CONFIG_RPXCLASSIC
302 *((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL;
307 *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
309 *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
310 *(unsigned int *)QS_CONFIG_DATA = val;
312 #ifdef CONFIG_RPXCLASSIC
313 *((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL;
315 restore_flags(flags);
318 return PCIBIOS_SUCCESSFUL;
321 int qspan_pcibios_find_device(unsigned short vendor, unsigned short dev_id,
322 unsigned short index, unsigned char *bus_ptr,
323 unsigned char *dev_fn_ptr)
326 unsigned int x, vendev;
328 if (vendor == 0xffff)
329 return PCIBIOS_BAD_VENDOR_ID;
330 vendev = (dev_id << 16) + vendor;
332 for (devfn = 0; devfn < 32; devfn++) {
333 qspan_pcibios_read_config_dword(0, devfn<<3, PCI_VENDOR_ID, &x);
337 *dev_fn_ptr = devfn<<3;
338 return PCIBIOS_SUCCESSFUL;
343 return PCIBIOS_DEVICE_NOT_FOUND;
346 int qspan_pcibios_find_class(unsigned int class_code, unsigned short index,
347 unsigned char *bus_ptr, unsigned char *dev_fn_ptr)
352 for (devnr = 0; devnr < 32; devnr++) {
353 qspan_pcibios_read_config_dword(0, devnr<<3, PCI_CLASS_REVISION, &x);
354 if ((x>>8) == class_code) {
357 *dev_fn_ptr = devnr<<3;
358 return PCIBIOS_SUCCESSFUL;
363 return PCIBIOS_DEVICE_NOT_FOUND;
367 m8xx_pcibios_fixup(void))
369 /* Lots to do here, all board and configuration specific. */
373 m8xx_setup_pci_ptrs(void))
375 set_config_access_method(qspan);
377 ppc_md.pcibios_fixup = m8xx_pcibios_fixup;