2 * arch/ppc/syslib/todc_time.c
4 * Time of Day Clock support for the M48T35, M48T37, M48T59, and MC146818
5 * Real Time Clocks/Timekeepers.
7 * Author: Mark A. Greer
10 * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
15 #include <linux/errno.h>
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/time.h>
19 #include <linux/timex.h>
20 #include <linux/bcd.h>
22 #include <asm/machdep.h>
28 * Depending on the hardware on your board and your board design, the
29 * RTC/NVRAM may be accessed either directly (like normal memory) or via
30 * address/data registers. If your board uses the direct method, set
31 * 'nvram_data' to the base address of your nvram and leave 'nvram_as0' and
32 * 'nvram_as1' NULL. If your board uses address/data regs to access nvram,
33 * set 'nvram_as0' to the address of the lower byte, set 'nvram_as1' to the
34 * address of the upper byte (leave NULL if using mc146818), and set
35 * 'nvram_data' to the address of the 8-bit data register.
37 * In order to break the assumption that the RTC and NVRAM are accessed by
38 * the same mechanism, you need to explicitly set 'ppc_md.rtc_read_val' and
39 * 'ppc_md.rtc_write_val', otherwise the values of 'ppc_md.rtc_read_val'
40 * and 'ppc_md.rtc_write_val' will be used.
42 * Note: Even though the documentation for the various RTC chips say that it
43 * take up to a second before it starts updating once the 'R' bit is
44 * cleared, they always seem to update even though we bang on it many
45 * times a second. This is true, except for the Dallas Semi 1746/1747
46 * (possibly others). Those chips seem to have a real problem whenever
47 * we set the 'R' bit before reading them, they basically stop counting.
51 extern spinlock_t rtc_lock;
54 * 'todc_info' should be initialized in your *_setup.c file to
55 * point to a fully initialized 'todc_info_t' structure.
56 * This structure holds all the register offsets for your particular
58 * TODC_ALLOC()/TODC_INIT() will allocate and initialize this table for you.
61 #ifdef RTC_FREQ_SELECT
62 #undef RTC_FREQ_SELECT
63 #define RTC_FREQ_SELECT control_b /* Register A */
68 #define RTC_CONTROL control_a /* Register B */
73 #define RTC_INTR_FLAGS watchdog /* Register C */
78 #define RTC_VALID interrupts /* Register D */
81 /* Access routines when RTC accessed directly (like normal memory) */
83 todc_direct_read_val(int addr)
85 return readb(todc_info->nvram_data + addr);
89 todc_direct_write_val(int addr, unsigned char val)
91 writeb(val, todc_info->nvram_data + addr);
95 /* Access routines for accessing m48txx type chips via addr/data regs */
97 todc_m48txx_read_val(int addr)
99 outb(addr, todc_info->nvram_as0);
100 outb(addr>>todc_info->as0_bits, todc_info->nvram_as1);
101 return inb(todc_info->nvram_data);
105 todc_m48txx_write_val(int addr, unsigned char val)
107 outb(addr, todc_info->nvram_as0);
108 outb(addr>>todc_info->as0_bits, todc_info->nvram_as1);
109 outb(val, todc_info->nvram_data);
113 /* Access routines for accessing mc146818 type chips via addr/data regs */
115 todc_mc146818_read_val(int addr)
117 outb_p(addr, todc_info->nvram_as0);
118 return inb_p(todc_info->nvram_data);
122 todc_mc146818_write_val(int addr, unsigned char val)
124 outb_p(addr, todc_info->nvram_as0);
125 outb_p(val, todc_info->nvram_data);
130 * Routines to make RTC chips with NVRAM buried behind an addr/data pair
131 * have the NVRAM and clock regs appear at the same level.
132 * The NVRAM will appear to start at addr 0 and the clock regs will appear
133 * to start immediately after the NVRAM (actually, start at offset
134 * todc_info->nvram_size).
137 todc_read_val(int addr)
141 if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
142 if (addr < todc_info->nvram_size) { /* NVRAM */
143 ppc_md.rtc_write_val(todc_info->nvram_addr_reg, addr);
144 val = ppc_md.rtc_read_val(todc_info->nvram_data_reg);
146 else { /* Clock Reg */
147 addr -= todc_info->nvram_size;
148 val = ppc_md.rtc_read_val(addr);
152 val = ppc_md.rtc_read_val(addr);
159 todc_write_val(int addr, u_char val)
161 if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
162 if (addr < todc_info->nvram_size) { /* NVRAM */
163 ppc_md.rtc_write_val(todc_info->nvram_addr_reg, addr);
164 ppc_md.rtc_write_val(todc_info->nvram_data_reg, val);
166 else { /* Clock Reg */
167 addr -= todc_info->nvram_size;
168 ppc_md.rtc_write_val(addr, val);
172 ppc_md.rtc_write_val(addr, val);
179 * There is some ugly stuff in that there are assumptions for the mc146818.
182 * - todc_info->control_a has the offset as mc146818 Register B reg
183 * - todc_info->control_b has the offset as mc146818 Register A reg
184 * - m48txx control reg's write enable or 'W' bit is same as
185 * mc146818 Register B 'SET' bit (i.e., 0x80)
187 * These assumptions were made to make the code simpler.
194 if (!ppc_md.rtc_read_val)
195 ppc_md.rtc_read_val = ppc_md.nvram_read_val;
196 if (!ppc_md.rtc_write_val)
197 ppc_md.rtc_write_val = ppc_md.nvram_write_val;
199 cntl_b = todc_read_val(todc_info->control_b);
201 if (todc_info->rtc_type == TODC_TYPE_MC146818) {
202 if ((cntl_b & 0x70) != 0x20) {
203 printk(KERN_INFO "TODC %s %s\n",
204 "real-time-clock was stopped.",
210 todc_write_val(todc_info->control_b, cntl_b);
211 } else if (todc_info->rtc_type == TODC_TYPE_DS17285) {
214 mode = todc_read_val(TODC_TYPE_DS17285_CNTL_A);
215 /* Make sure countdown clear is not set */
217 /* Enable oscillator, extended register set */
219 todc_write_val(TODC_TYPE_DS17285_CNTL_A, mode);
221 } else if (todc_info->rtc_type == TODC_TYPE_DS1501) {
224 todc_info->enable_read = TODC_DS1501_CNTL_B_TE;
225 todc_info->enable_write = TODC_DS1501_CNTL_B_TE;
227 month = todc_read_val(todc_info->month);
229 if ((month & 0x80) == 0x80) {
230 printk(KERN_INFO "TODC %s %s\n",
231 "real-time-clock was stopped.",
234 todc_write_val(todc_info->month, month);
237 cntl_b &= ~TODC_DS1501_CNTL_B_TE;
238 todc_write_val(todc_info->control_b, cntl_b);
239 } else { /* must be a m48txx type */
242 todc_info->enable_read = TODC_MK48TXX_CNTL_A_R;
243 todc_info->enable_write = TODC_MK48TXX_CNTL_A_W;
245 cntl_a = todc_read_val(todc_info->control_a);
247 /* Check & clear STOP bit in control B register */
248 if (cntl_b & TODC_MK48TXX_DAY_CB) {
249 printk(KERN_INFO "TODC %s %s\n",
250 "real-time-clock was stopped.",
253 cntl_a |= todc_info->enable_write;
254 cntl_b &= ~TODC_MK48TXX_DAY_CB;/* Start Oscil */
256 todc_write_val(todc_info->control_a, cntl_a);
257 todc_write_val(todc_info->control_b, cntl_b);
260 /* Make sure READ & WRITE bits are cleared. */
261 cntl_a &= ~(todc_info->enable_write |
262 todc_info->enable_read);
263 todc_write_val(todc_info->control_a, cntl_a);
270 * There is some ugly stuff in that there are assumptions that for a mc146818,
271 * the todc_info->control_a has the offset of the mc146818 Register B reg and
272 * that the register'ss 'SET' bit is the same as the m48txx's write enable
273 * bit in the control register of the m48txx (i.e., 0x80).
275 * It was done to make the code look simpler.
278 todc_get_rtc_time(void)
280 uint year, mon, day, hour, min, sec;
282 u_char save_control, uip;
284 spin_lock(&rtc_lock);
285 save_control = todc_read_val(todc_info->control_a);
287 if (todc_info->rtc_type != TODC_TYPE_MC146818) {
290 switch (todc_info->rtc_type) {
291 case TODC_TYPE_DS1557:
292 case TODC_TYPE_DS1743:
293 case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */
294 case TODC_TYPE_DS1747:
295 case TODC_TYPE_DS17285:
298 todc_write_val(todc_info->control_a,
299 (save_control | todc_info->enable_read));
306 for (i=0; i<limit; i++) {
307 if (todc_info->rtc_type == TODC_TYPE_MC146818) {
308 uip = todc_read_val(todc_info->RTC_FREQ_SELECT);
311 sec = todc_read_val(todc_info->seconds) & 0x7f;
312 min = todc_read_val(todc_info->minutes) & 0x7f;
313 hour = todc_read_val(todc_info->hours) & 0x3f;
314 day = todc_read_val(todc_info->day_of_month) & 0x3f;
315 mon = todc_read_val(todc_info->month) & 0x1f;
316 year = todc_read_val(todc_info->year) & 0xff;
318 if (todc_info->rtc_type == TODC_TYPE_MC146818) {
319 uip |= todc_read_val(todc_info->RTC_FREQ_SELECT);
320 if ((uip & RTC_UIP) == 0) break;
324 if (todc_info->rtc_type != TODC_TYPE_MC146818) {
325 switch (todc_info->rtc_type) {
326 case TODC_TYPE_DS1557:
327 case TODC_TYPE_DS1743:
328 case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */
329 case TODC_TYPE_DS1747:
330 case TODC_TYPE_DS17285:
333 save_control &= ~(todc_info->enable_read);
334 todc_write_val(todc_info->control_a,
338 spin_unlock(&rtc_lock);
340 if ((todc_info->rtc_type != TODC_TYPE_MC146818) ||
341 ((save_control & RTC_DM_BINARY) == 0) ||
357 return mktime(year, mon, day, hour, min, sec);
361 todc_set_rtc_time(unsigned long nowtime)
364 u_char save_control, save_freq_select;
366 spin_lock(&rtc_lock);
369 save_control = todc_read_val(todc_info->control_a);
371 /* Assuming MK48T59_RTC_CA_WRITE & RTC_SET are equal */
372 todc_write_val(todc_info->control_a,
373 (save_control | todc_info->enable_write));
374 save_control &= ~(todc_info->enable_write); /* in case it was set */
376 if (todc_info->rtc_type == TODC_TYPE_MC146818) {
377 save_freq_select = todc_read_val(todc_info->RTC_FREQ_SELECT);
378 todc_write_val(todc_info->RTC_FREQ_SELECT,
379 save_freq_select | RTC_DIV_RESET2);
383 tm.tm_year = (tm.tm_year - 1900) % 100;
385 if ((todc_info->rtc_type != TODC_TYPE_MC146818) ||
386 ((save_control & RTC_DM_BINARY) == 0) ||
389 BIN_TO_BCD(tm.tm_sec);
390 BIN_TO_BCD(tm.tm_min);
391 BIN_TO_BCD(tm.tm_hour);
392 BIN_TO_BCD(tm.tm_mon);
393 BIN_TO_BCD(tm.tm_mday);
394 BIN_TO_BCD(tm.tm_year);
397 todc_write_val(todc_info->seconds, tm.tm_sec);
398 todc_write_val(todc_info->minutes, tm.tm_min);
399 todc_write_val(todc_info->hours, tm.tm_hour);
400 todc_write_val(todc_info->month, tm.tm_mon);
401 todc_write_val(todc_info->day_of_month, tm.tm_mday);
402 todc_write_val(todc_info->year, tm.tm_year);
404 todc_write_val(todc_info->control_a, save_control);
406 if (todc_info->rtc_type == TODC_TYPE_MC146818) {
407 todc_write_val(todc_info->RTC_FREQ_SELECT, save_freq_select);
409 spin_unlock(&rtc_lock);
415 * Manipulates read bit to reliably read seconds at a high rate.
417 static unsigned char __init todc_read_timereg(int addr)
419 unsigned char save_control, val;
421 switch (todc_info->rtc_type) {
422 case TODC_TYPE_DS1557:
423 case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */
424 case TODC_TYPE_DS1747:
425 case TODC_TYPE_DS17285:
426 case TODC_TYPE_MC146818:
429 save_control = todc_read_val(todc_info->control_a);
430 todc_write_val(todc_info->control_a,
431 (save_control | todc_info->enable_read));
433 val = todc_read_val(addr);
435 switch (todc_info->rtc_type) {
436 case TODC_TYPE_DS1557:
437 case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */
438 case TODC_TYPE_DS1747:
439 case TODC_TYPE_DS17285:
440 case TODC_TYPE_MC146818:
443 save_control &= ~(todc_info->enable_read);
444 todc_write_val(todc_info->control_a, save_control);
451 * This was taken from prep_setup.c
452 * Use the NVRAM RTC to time a second to calibrate the decrementer.
455 todc_calibrate_decr(void)
465 * Actually this is bad for precision, we should have a loop in
466 * which we only read the seconds counter. todc_read_val writes
467 * the address bytes on every call and this takes a lot of time.
468 * Perhaps an nvram_wait_change method returning a time
469 * stamp with a loop count as parameter would be the solution.
472 * Need to make sure the tbl doesn't roll over so if tbu increments
473 * during this test, we need to do it again.
477 sec = todc_read_timereg(todc_info->seconds) & 0x7f;
482 for (i = 0 ; i < 10000000 ; i++) {/* may take up to 1 second */
485 if ((todc_read_timereg(todc_info->seconds) & 0x7f) != sec) {
490 sec = todc_read_timereg(todc_info->seconds) & 0x7f;
492 for (i = 0 ; i < 10000000 ; i++) { /* Should take 1 second */
495 if ((todc_read_timereg(todc_info->seconds) & 0x7f) != sec) {
501 } while ((get_tbu() != tbu) && (++loop_count < 2));
503 printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
504 freq/1000000, freq%1000000);
506 tb_ticks_per_jiffy = freq / HZ;
507 tb_to_us = mulhwu_scale_factor(freq, 1000000);