2 * Copyright 2001 Mike Corrigan, IBM Corp
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
12 #include <linux/threads.h>
13 #include <linux/module.h>
14 #include <asm/processor.h>
15 #include <asm/ptrace.h>
17 #include <asm/abs_addr.h>
18 #include <asm/bitops.h>
19 #include <asm/iSeries/ItLpNaca.h>
20 #include <asm/iSeries/ItLpPaca.h>
21 #include <asm/iSeries/ItLpRegSave.h>
23 #include <asm/iSeries/HvReleaseData.h>
24 #include <asm/iSeries/LparMap.h>
25 #include <asm/iSeries/ItVpdAreas.h>
26 #include <asm/iSeries/ItIplParmsReal.h>
27 #include <asm/iSeries/ItExtVpdPanel.h>
28 #include <asm/iSeries/ItLpQueue.h>
29 #include <asm/iSeries/IoHriProcessorVpd.h>
30 #include <asm/iSeries/ItSpCommArea.h>
32 /* The LpQueue is used to pass event data from the hypervisor to
33 * the partition. This is where I/O interrupt events are communicated.
36 /* May be filled in by the hypervisor so cannot end up in the BSS */
37 struct ItLpQueue xItLpQueue __attribute__((__section__(".data")));
40 /* The HvReleaseData is the root of the information shared between
41 * the hypervisor and Linux.
44 struct HvReleaseData hvReleaseData = {
45 0xc8a5d9c4, /* desc = "HvRD" ebcdic */
46 sizeof(struct HvReleaseData),
47 offsetof(struct naca_struct, xItVpdAreas),
48 (struct naca_struct *)(NACA_VIRT_ADDR), /* 64-bit Naca address */
49 0x6000, /* offset of LparMap within loadarea (see head.S) */
51 1, /* tags inactive */
53 0, /* shared processors */
55 6, /* TEMP: This allows non-GA driver */
56 4, /* We are v5r2m0 */
57 3, /* Min supported PLIC = v5r1m0 */
58 3, /* Min usable PLIC = v5r1m0 */
59 { 0xd3, 0x89, 0x95, 0xa4, /* "Linux 2.4 "*/
60 0xa7, 0x40, 0xf2, 0x4b,
61 0xf4, 0x4b, 0xf6, 0xf4 },
65 extern void SystemReset_Iseries(void);
66 extern void MachineCheck_Iseries(void);
67 extern void DataAccess_Iseries(void);
68 extern void InstructionAccess_Iseries(void);
69 extern void HardwareInterrupt_Iseries(void);
70 extern void Alignment_Iseries(void);
71 extern void ProgramCheck_Iseries(void);
72 extern void FPUnavailable_Iseries(void);
73 extern void Decrementer_Iseries(void);
74 extern void Trap_0a_Iseries(void);
75 extern void Trap_0b_Iseries(void);
76 extern void SystemCall_Iseries(void);
77 extern void SingleStep_Iseries(void);
78 extern void Trap_0e_Iseries(void);
79 extern void PerformanceMonitor_Iseries(void);
80 extern void DataAccessSLB_Iseries(void);
81 extern void InstructionAccessSLB_Iseries(void);
83 struct ItLpNaca itLpNaca = {
84 0xd397d581, /* desc = "LpNa" ebcdic */
85 0x0400, /* size of ItLpNaca */
86 0x0300, 19, /* offset to int array, # ents */
87 0, 0, 0, /* Part # of primary, serv, me */
88 0, 0x100, /* # of LP queues, offset */
89 0, 0, 0, /* Piranha stuff */
90 { 0,0,0,0,0 }, /* reserved */
91 0,0,0,0,0,0,0, /* stuff */
92 { 0,0,0,0,0 }, /* reserved */
94 0, /* VRM index of PLIC */
95 0, 0, /* min supported, compat SLIC */
96 0, /* 64-bit addr of load area */
97 0, /* chunks for load area */
98 0, 0, /* PASE mask, seg table */
99 { 0 }, /* 64 reserved bytes */
100 { 0 }, /* 128 reserved bytes */
101 { 0 }, /* Old LP Queue */
102 { 0 }, /* 384 reserved bytes */
104 (u64)SystemReset_Iseries, /* 0x100 System Reset */
105 (u64)MachineCheck_Iseries, /* 0x200 Machine Check */
106 (u64)DataAccess_Iseries, /* 0x300 Data Access */
107 (u64)InstructionAccess_Iseries, /* 0x400 Instruction Access */
108 (u64)HardwareInterrupt_Iseries, /* 0x500 External */
109 (u64)Alignment_Iseries, /* 0x600 Alignment */
110 (u64)ProgramCheck_Iseries, /* 0x700 Program Check */
111 (u64)FPUnavailable_Iseries, /* 0x800 FP Unavailable */
112 (u64)Decrementer_Iseries, /* 0x900 Decrementer */
113 (u64)Trap_0a_Iseries, /* 0xa00 Trap 0A */
114 (u64)Trap_0b_Iseries, /* 0xb00 Trap 0B */
115 (u64)SystemCall_Iseries, /* 0xc00 System Call */
116 (u64)SingleStep_Iseries, /* 0xd00 Single Step */
117 (u64)Trap_0e_Iseries, /* 0xe00 Trap 0E */
118 (u64)PerformanceMonitor_Iseries,/* 0xf00 Performance Monitor */
121 0, /* int 0x1020 CPU ctls */
122 (u64)HardwareInterrupt_Iseries, /* SC Ret Hdlr */
123 (u64)DataAccessSLB_Iseries, /* 0x380 D-SLB */
124 (u64)InstructionAccessSLB_Iseries /* 0x480 I-SLB */
127 EXPORT_SYMBOL(itLpNaca);
129 /* May be filled in by the hypervisor so cannot end up in the BSS */
130 struct ItIplParmsReal xItIplParmsReal __attribute__((__section__(".data")));
132 /* May be filled in by the hypervisor so cannot end up in the BSS */
133 struct ItExtVpdPanel xItExtVpdPanel __attribute__((__section__(".data")));
134 EXPORT_SYMBOL(xItExtVpdPanel);
136 #define maxPhysicalProcessors 32
138 struct IoHriProcessorVpd xIoHriProcessorVpd[maxPhysicalProcessors] = {
140 .xInstCacheOperandSize = 32,
141 .xDataCacheOperandSize = 32,
142 .xProcFreq = 50000000,
143 .xTimeBaseFreq = 50000000,
148 /* Space for Main Store Vpd 27,200 bytes */
149 /* May be filled in by the hypervisor so cannot end up in the BSS */
150 u64 xMsVpd[3400] __attribute__((__section__(".data")));
152 /* Space for Recovery Log Buffer */
153 /* May be filled in by the hypervisor so cannot end up in the BSS */
154 u64 xRecoveryLogBuffer[32] __attribute__((__section__(".data")));
156 struct SpCommArea xSpCommArea = {
163 /* The LparMap data is now located at offset 0x6000 in head.S
164 * It was put there so that the HvReleaseData could address it
165 * with a 32-bit offset as required by the iSeries hypervisor
167 * The Naca has a pointer to the ItVpdAreas. The hypervisor finds
168 * the Naca via the HvReleaseData area. The HvReleaseData has the
169 * offset into the Naca of the pointer to the ItVpdAreas.
171 struct ItVpdAreas itVpdAreas = {
172 0xc9a3e5c1, /* "ItVA" */
173 sizeof( struct ItVpdAreas ),
175 26, /* # VPD array entries */
176 10, /* # DMA array entries */
177 NR_CPUS*2, maxPhysicalProcessors, /* Max logical, physical procs */
178 offsetof(struct ItVpdAreas,xPlicDmaToks),/* offset to DMA toks */
179 offsetof(struct ItVpdAreas,xSlicVpdAdrs),/* offset to VPD addrs */
180 offsetof(struct ItVpdAreas,xPlicDmaLens),/* offset to DMA lens */
181 offsetof(struct ItVpdAreas,xSlicVpdLens),/* offset to VPD lens */
182 0, /* max slot labels */
183 1, /* max LP queues */
184 {0}, {0}, /* reserved */
185 {0}, /* DMA lengths */
186 {0}, /* DMA tokens */
189 sizeof(xItExtVpdPanel), /* 3 Extended VPD */
190 sizeof(struct paca_struct), /* 4 length of Paca */
192 sizeof(struct ItIplParmsReal),/* 6 length of IPL parms */
193 26992, /* 7 length of MS VPD */
195 sizeof(struct ItLpNaca),/* 9 length of LP Naca */
197 256, /* 11 length of Recovery Log Buf */
198 sizeof(struct SpCommArea), /* 12 length of SP Comm Area */
200 sizeof(struct IoHriProcessorVpd),/* 16 length of Proc Vpd */
201 0,0,0,0,0,0, /* 17 - 22 */
202 sizeof(struct ItLpQueue),/* 23 length of Lp Queue */
205 { /* VPD addresses */
207 &xItExtVpdPanel, /* 3 Extended VPD */
208 &paca[0], /* 4 first Paca */
210 &xItIplParmsReal, /* 6 IPL parms */
211 &xMsVpd, /* 7 MS Vpd */
213 &itLpNaca, /* 9 LpNaca */
215 &xRecoveryLogBuffer, /* 11 Recovery Log Buffer */
216 &xSpCommArea, /* 12 SP Comm Area */
218 &xIoHriProcessorVpd, /* 16 Proc Vpd */
219 0,0,0,0,0,0, /* 17 - 22 */
220 &xItLpQueue, /* 23 Lp Queue */
225 struct msChunks msChunks;
227 /* Depending on whether this is called from iSeries or pSeries setup
228 * code, the location of the msChunks struct may or may not have
229 * to be reloc'd, so we force the caller to do that for us by passing
230 * in a pointer to the structure.
233 msChunks_alloc(unsigned long mem, unsigned long num_chunks, unsigned long chunk_size)
235 unsigned long offset = reloc_offset();
236 struct msChunks *_msChunks = PTRRELOC(&msChunks);
238 _msChunks->num_chunks = num_chunks;
239 _msChunks->chunk_size = chunk_size;
240 _msChunks->chunk_shift = __ilog2(chunk_size);
241 _msChunks->chunk_mask = (1UL<<_msChunks->chunk_shift)-1;
243 mem = _ALIGN(mem, sizeof(msChunks_entry));
244 _msChunks->abs = (msChunks_entry *)(mem + offset);
245 mem += num_chunks * sizeof(msChunks_entry);