2 * arch/ppc64/kernel/head.S
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
7 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
8 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
9 * Adapted for Power Macintosh by Paul Mackerras.
10 * Low-level exception handlers and MMU support
11 * rewritten by Paul Mackerras.
12 * Copyright (C) 1996 Paul Mackerras.
14 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
15 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
17 * This file contains the low-level support and setup for the
18 * PowerPC-64 platform, including trap and interrupt dispatch.
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License
22 * as published by the Free Software Foundation; either version
23 * 2 of the License, or (at your option) any later version.
26 #define SECONDARY_PROCESSORS
28 #include <linux/config.h>
29 #include <linux/threads.h>
30 #include <asm/processor.h>
34 #include <asm/systemcfg.h>
35 #include <asm/ppc_asm.h>
36 #include <asm/offsets.h>
38 #include <asm/cputable.h>
39 #include <asm/setup.h>
41 #ifdef CONFIG_PPC_ISERIES
42 #define DO_SOFT_DISABLE
46 * hcall interface to pSeries LPAR
48 #define HVSC .long 0x44000022
49 #define H_SET_ASR 0x30
52 * We layout physical memory as follows:
53 * 0x0000 - 0x00ff : Secondary processor spin code
54 * 0x0100 - 0x2fff : pSeries Interrupt prologs
55 * 0x3000 - 0x3fff : Interrupt support
56 * 0x4000 - 0x4fff : NACA
57 * 0x5000 - 0x5fff : SystemCfg
58 * 0x6000 : iSeries and common interrupt prologs
59 * 0x9000 - 0x9fff : Initial segment table
67 * SPRG0 reserved for hypervisor
68 * SPRG1 temp - used to save gpr
69 * SPRG2 temp - used to save gpr
70 * SPRG3 virt addr of paca
74 * Entering into this code we make the following assumptions:
76 * 1. The MMU is off & open firmware is running in real mode.
77 * 2. The kernel is entered at __start
80 * 1. The MMU is on (as it always is for iSeries)
81 * 2. The kernel is entered at SystemReset_Iseries
87 #ifdef CONFIG_PPC_MULTIPLATFORM
89 /* NOP this out unconditionally */
91 b .__start_initialization_multiplatform
93 #endif /* CONFIG_PPC_MULTIPLATFORM */
95 /* Catch branch to 0 in real mode */
97 #ifdef CONFIG_PPC_ISERIES
99 * At offset 0x20, there is a pointer to iSeries LPAR data.
100 * This is required by the hypervisor
103 .llong hvReleaseData-KERNELBASE
106 * At offset 0x28 and 0x30 are offsets to the msChunks
107 * array (used by the iSeries LPAR debugger to do translation
108 * between physical addresses and absolute addresses) and
109 * to the pidhash table (also used by the debugger)
111 .llong msChunks-KERNELBASE
112 .llong 0 /* pidhash-KERNELBASE SFRXXX */
114 /* Offset 0x38 - Pointer to start of embedded System.map */
115 .globl embedded_sysmap_start
116 embedded_sysmap_start:
118 /* Offset 0x40 - Pointer to end of embedded System.map */
119 .globl embedded_sysmap_end
123 #else /* CONFIG_PPC_ISERIES */
125 /* Secondary processors spin on this value until it goes to 1. */
126 .globl __secondary_hold_spinloop
127 __secondary_hold_spinloop:
130 /* Secondary processors write this value with their cpu # */
131 /* after they enter the spin loop immediately below. */
132 .globl __secondary_hold_acknowledge
133 __secondary_hold_acknowledge:
138 * The following code is used on pSeries to hold secondary processors
139 * in a spin loop after they have been freed from OpenFirmware, but
140 * before the bulk of the kernel has been relocated. This code
141 * is relocated to physical address 0x60 before prom_init is run.
142 * All of it must fit below the first exception vector at 0x100.
144 _GLOBAL(__secondary_hold)
147 mtmsrd r24 /* RI on */
149 /* Grab our linux cpu number */
152 /* Tell the master cpu we're here */
153 /* Relocation is off & we are located at an address less */
154 /* than 0x100, so only need to grab low order offset. */
155 std r24,__secondary_hold_acknowledge@l(0)
158 /* All secondary cpu's wait here until told to start. */
159 100: ld r4,__secondary_hold_spinloop@l(0)
168 b .pseries_secondary_smp_init
175 /* This value is used to mark exception frames on the stack. */
178 .tc ID_72656773_68657265[TC],0x7265677368657265
182 * The following macros define the code that appears as
183 * the prologue to each of the exception handlers. They
184 * are split into two parts to allow a single kernel binary
185 * to be used for pSeries and iSeries.
186 * LOL. One day... - paulus
190 * We make as much of the exception code common between native
191 * exception handlers (including pSeries LPAR) and iSeries LPAR
192 * implementations as possible.
196 * This is the start of the interrupt handlers for pSeries
197 * This code runs with relocation off.
205 #define EX_R3 40 /* SLB miss saves R3, but not SRR0 */
207 #define EX_LR 48 /* SLB miss saves LR, but not DAR */
211 #define EXCEPTION_PROLOG_PSERIES(area, label) \
212 mfspr r13,SPRG3; /* get paca address into r13 */ \
213 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
214 std r10,area+EX_R10(r13); \
215 std r11,area+EX_R11(r13); \
216 std r12,area+EX_R12(r13); \
218 std r9,area+EX_R13(r13); \
220 clrrdi r12,r13,32; /* get high part of &label */ \
222 mfspr r11,SRR0; /* save SRR0 */ \
223 ori r12,r12,(label)@l; /* virt addr of handler */ \
224 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
226 mfspr r12,SRR1; /* and SRR1 */ \
229 b . /* prevent speculative execution */
232 * This is the start of the interrupt handlers for iSeries
233 * This code runs with relocation on.
235 #define EXCEPTION_PROLOG_ISERIES_1(area) \
236 mfspr r13,SPRG3; /* get paca address into r13 */ \
237 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
238 std r10,area+EX_R10(r13); \
239 std r11,area+EX_R11(r13); \
240 std r12,area+EX_R12(r13); \
242 std r9,area+EX_R13(r13); \
245 #define EXCEPTION_PROLOG_ISERIES_2 \
247 ld r11,PACALPPACA+LPPACASRR0(r13); \
248 ld r12,PACALPPACA+LPPACASRR1(r13); \
249 ori r10,r10,MSR_RI; \
253 * The common exception prolog is used for all except a few exceptions
254 * such as a segment miss on a kernel address. We have to be prepared
255 * to take another exception from the point where we first touch the
256 * kernel stack onwards.
258 * On entry r13 points to the paca, r9-r13 are saved in the paca,
259 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
260 * SRR1, and relocation is on.
262 #define EXCEPTION_PROLOG_COMMON(n, area) \
263 andi. r10,r12,MSR_PR; /* See if coming from user */ \
264 mr r10,r1; /* Save r1 */ \
265 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
267 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
268 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
269 bge- cr1,bad_stack; /* abort if it is */ \
270 std r9,_CCR(r1); /* save CR in stackframe */ \
271 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
272 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
273 std r10,0(r1); /* make stack chain pointer */ \
274 std r0,GPR0(r1); /* save r0 in stackframe */ \
275 std r10,GPR1(r1); /* save r1 in stackframe */ \
276 std r2,GPR2(r1); /* save r2 in stackframe */ \
277 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
278 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
279 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
280 ld r10,area+EX_R10(r13); \
283 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
284 ld r10,area+EX_R12(r13); \
285 ld r11,area+EX_R13(r13); \
289 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
290 mflr r9; /* save LR in stackframe */ \
292 mfctr r10; /* save CTR in stackframe */ \
294 mfspr r11,XER; /* save XER in stackframe */ \
297 std r9,_TRAP(r1); /* set trap number */ \
299 ld r11,exception_marker@toc(r2); \
300 std r10,RESULT(r1); /* clear regs->result */ \
301 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
306 #define STD_EXCEPTION_PSERIES(n, label) \
308 .globl label##_Pseries; \
311 mtspr SPRG1,r13; /* save r13 */ \
312 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
314 #define STD_EXCEPTION_ISERIES(n, label, area) \
315 .globl label##_Iseries; \
318 mtspr SPRG1,r13; /* save r13 */ \
319 EXCEPTION_PROLOG_ISERIES_1(area); \
320 EXCEPTION_PROLOG_ISERIES_2; \
323 #define MASKABLE_EXCEPTION_ISERIES(n, label) \
324 .globl label##_Iseries; \
327 mtspr SPRG1,r13; /* save r13 */ \
328 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
329 lbz r10,PACAPROCENABLED(r13); \
331 beq- label##_Iseries_masked; \
332 EXCEPTION_PROLOG_ISERIES_2; \
335 #ifdef DO_SOFT_DISABLE
336 #define DISABLE_INTS \
337 lbz r10,PACAPROCENABLED(r13); \
341 stb r11,PACAPROCENABLED(r13); \
342 ori r10,r10,MSR_EE; \
345 #define ENABLE_INTS \
346 lbz r10,PACAPROCENABLED(r13); \
349 ori r11,r11,MSR_EE; \
352 #else /* hard enable/disable interrupts */
355 #define ENABLE_INTS \
358 rlwimi r11,r12,0,MSR_EE; \
363 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \
365 .globl label##_common; \
367 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
370 addi r3,r1,STACK_FRAME_OVERHEAD; \
374 #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
376 .globl label##_common; \
378 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
380 addi r3,r1,STACK_FRAME_OVERHEAD; \
382 b .ret_from_except_lite
385 * Start of pSeries system interrupt routines
388 .globl __start_interrupts
391 STD_EXCEPTION_PSERIES(0x100, SystemReset)
394 _MachineCheckPseries:
396 mtspr SPRG1,r13 /* save r13 */
397 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, MachineCheck_common)
400 .globl DataAccess_Pseries
409 rlwimi r13,r12,16,0x20
412 beq .do_stab_bolted_Pseries
415 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
416 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, DataAccess_common)
419 .globl DataAccessSLB_Pseries
420 DataAccessSLB_Pseries:
423 mfspr r13,SPRG3 /* get paca address into r13 */
424 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
425 std r10,PACA_EXSLB+EX_R10(r13)
426 std r11,PACA_EXSLB+EX_R11(r13)
427 std r12,PACA_EXSLB+EX_R12(r13)
428 std r3,PACA_EXSLB+EX_R3(r13)
430 std r9,PACA_EXSLB+EX_R13(r13)
432 mfspr r12,SRR1 /* and SRR1 */
434 b .do_slb_miss /* Rel. branch works in real mode */
436 STD_EXCEPTION_PSERIES(0x400, InstructionAccess)
439 .globl InstructionAccessSLB_Pseries
440 InstructionAccessSLB_Pseries:
443 mfspr r13,SPRG3 /* get paca address into r13 */
444 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
445 std r10,PACA_EXSLB+EX_R10(r13)
446 std r11,PACA_EXSLB+EX_R11(r13)
447 std r12,PACA_EXSLB+EX_R12(r13)
448 std r3,PACA_EXSLB+EX_R3(r13)
450 std r9,PACA_EXSLB+EX_R13(r13)
452 mfspr r12,SRR1 /* and SRR1 */
453 mfspr r3,SRR0 /* SRR0 is faulting address */
454 b .do_slb_miss /* Rel. branch works in real mode */
456 STD_EXCEPTION_PSERIES(0x500, HardwareInterrupt)
457 STD_EXCEPTION_PSERIES(0x600, Alignment)
458 STD_EXCEPTION_PSERIES(0x700, ProgramCheck)
459 STD_EXCEPTION_PSERIES(0x800, FPUnavailable)
460 STD_EXCEPTION_PSERIES(0x900, Decrementer)
461 STD_EXCEPTION_PSERIES(0xa00, Trap_0a)
462 STD_EXCEPTION_PSERIES(0xb00, Trap_0b)
465 .globl SystemCall_Pseries
473 oris r12,r12,SystemCall_common@h
474 ori r12,r12,SystemCall_common@l
476 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
480 b . /* prevent speculative execution */
482 STD_EXCEPTION_PSERIES(0xd00, SingleStep)
483 STD_EXCEPTION_PSERIES(0xe00, Trap_0e)
485 /* We need to deal with the Altivec unavailable exception
486 * here which is at 0xf20, thus in the middle of the
487 * prolog code of the PerformanceMonitor one. A little
488 * trickery is thus necessary
491 b PerformanceMonitor_Pseries
493 STD_EXCEPTION_PSERIES(0xf20, AltivecUnavailable)
495 STD_EXCEPTION_PSERIES(0x1300, InstructionBreakpoint)
496 STD_EXCEPTION_PSERIES(0x1700, AltivecAssist)
498 /* moved from 0xf00 */
499 STD_EXCEPTION_PSERIES(0x3000, PerformanceMonitor)
502 _GLOBAL(do_stab_bolted_Pseries)
505 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
508 /* Space for the naca. Architected to be located at real address
509 * NACA_PHYS_ADDR. Various tools rely on this location being fixed.
510 * The first dword of the naca is required by iSeries LPAR to
511 * point to itVpdAreas. On pSeries native, this value is not used.
514 .globl __end_interrupts
518 #ifdef CONFIG_PPC_ISERIES
527 . = SYSTEMCFG_PHYS_ADDR
529 .globl __start_systemcfg
532 . = (SYSTEMCFG_PHYS_ADDR + PAGE_SIZE)
533 .globl __end_systemcfg
536 #ifdef CONFIG_PPC_ISERIES
538 * The iSeries LPAR map is at this fixed address
539 * so that the HvReleaseData structure can address
540 * it with a 32-bit offset.
542 * The VSID values below are dependent on the
543 * VSID generation algorithm. See include/asm/mmu_context.h.
546 .llong 2 /* # ESIDs to be mapped by hypervisor */
547 .llong 1 /* # memory ranges to be mapped by hypervisor */
548 .llong STAB0_PAGE /* Page # of segment table within load area */
549 .llong 0 /* Reserved */
550 .llong 0 /* Reserved */
551 .llong 0 /* Reserved */
552 .llong 0 /* Reserved */
553 .llong 0 /* Reserved */
554 .llong (KERNELBASE>>SID_SHIFT)
555 .llong 0x408f92c94 /* KERNELBASE VSID */
556 /* We have to list the bolted VMALLOC segment here, too, so that it
557 * will be restored on shared processor switch */
558 .llong (VMALLOCBASE>>SID_SHIFT)
559 .llong 0xf09b89af5 /* VMALLOCBASE VSID */
560 .llong 8192 /* # pages to map (32 MB) */
561 .llong 0 /* Offset from start of loadarea to start of map */
562 .llong 0x408f92c940000 /* VPN of first page to map */
566 /*** ISeries-LPAR interrupt handlers ***/
568 STD_EXCEPTION_ISERIES(0x200, MachineCheck, PACA_EXMC)
570 .globl DataAccess_Iseries
578 rlwimi r13,r12,16,0x20
581 beq .do_stab_bolted_Iseries
584 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
585 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
586 EXCEPTION_PROLOG_ISERIES_2
589 .do_stab_bolted_Iseries:
592 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
593 EXCEPTION_PROLOG_ISERIES_2
596 .globl DataAccessSLB_Iseries
597 DataAccessSLB_Iseries:
598 mtspr SPRG1,r13 /* save r13 */
599 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
600 std r3,PACA_EXSLB+EX_R3(r13)
601 ld r12,PACALPPACA+LPPACASRR1(r13)
605 STD_EXCEPTION_ISERIES(0x400, InstructionAccess, PACA_EXGEN)
607 .globl InstructionAccessSLB_Iseries
608 InstructionAccessSLB_Iseries:
609 mtspr SPRG1,r13 /* save r13 */
610 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
611 std r3,PACA_EXSLB+EX_R3(r13)
612 ld r12,PACALPPACA+LPPACASRR1(r13)
613 ld r3,PACALPPACA+LPPACASRR0(r13)
616 MASKABLE_EXCEPTION_ISERIES(0x500, HardwareInterrupt)
617 STD_EXCEPTION_ISERIES(0x600, Alignment, PACA_EXGEN)
618 STD_EXCEPTION_ISERIES(0x700, ProgramCheck, PACA_EXGEN)
619 STD_EXCEPTION_ISERIES(0x800, FPUnavailable, PACA_EXGEN)
620 MASKABLE_EXCEPTION_ISERIES(0x900, Decrementer)
621 STD_EXCEPTION_ISERIES(0xa00, Trap_0a, PACA_EXGEN)
622 STD_EXCEPTION_ISERIES(0xb00, Trap_0b, PACA_EXGEN)
624 .globl SystemCall_Iseries
628 EXCEPTION_PROLOG_ISERIES_2
631 STD_EXCEPTION_ISERIES( 0xd00, SingleStep, PACA_EXGEN)
632 STD_EXCEPTION_ISERIES( 0xe00, Trap_0e, PACA_EXGEN)
633 STD_EXCEPTION_ISERIES( 0xf00, PerformanceMonitor, PACA_EXGEN)
635 .globl SystemReset_Iseries
637 mfspr r13,SPRG3 /* Get paca address */
640 mtmsrd r24 /* RI on */
641 lhz r24,PACAPACAINDEX(r13) /* Get processor # */
642 cmpwi 0,r24,0 /* Are we processor 0? */
643 beq .__start_initialization_iSeries /* Start up the first processor */
645 li r5,RUNLATCH /* Turn off the run light */
652 lbz r23,PACAPROCSTART(r13) /* Test if this processor
655 LOADADDR(r3,current_set)
656 sldi r28,r24,3 /* get current_set[cpu#] */
658 addi r1,r3,THREAD_SIZE
659 subi r1,r1,STACK_FRAME_OVERHEAD
662 beq iseries_secondary_smp_loop /* Loop until told to go */
663 #ifdef SECONDARY_PROCESSORS
664 bne .__secondary_start /* Loop until told to go */
666 iseries_secondary_smp_loop:
667 /* Let the Hypervisor know we are alive */
668 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
670 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
671 #else /* CONFIG_SMP */
672 /* Yield the processor. This is required for non-SMP kernels
673 which are running on multi-threaded machines. */
675 rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */
676 addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */
677 li r4,0 /* "yield timed" */
678 li r5,-1 /* "yield forever" */
679 #endif /* CONFIG_SMP */
680 li r0,-1 /* r0=-1 indicates a Hypervisor call */
681 sc /* Invoke the hypervisor via a system call */
682 mfspr r13,SPRG3 /* Put r13 back ???? */
683 b 1b /* If SMP not configured, secondaries
686 .globl Decrementer_Iseries_masked
687 Decrementer_Iseries_masked:
689 stb r11,PACALPPACA+LPPACADECRINT(r13)
690 lwz r12,PACADEFAULTDECR(r13)
694 .globl HardwareInterrupt_Iseries_masked
695 HardwareInterrupt_Iseries_masked:
696 mtcrf 0x80,r9 /* Restore regs */
697 ld r11,PACALPPACA+LPPACASRR0(r13)
698 ld r12,PACALPPACA+LPPACASRR1(r13)
701 ld r9,PACA_EXGEN+EX_R9(r13)
702 ld r10,PACA_EXGEN+EX_R10(r13)
703 ld r11,PACA_EXGEN+EX_R11(r13)
704 ld r12,PACA_EXGEN+EX_R12(r13)
705 ld r13,PACA_EXGEN+EX_R13(r13)
707 b . /* prevent speculative execution */
711 * Data area reserved for FWNMI option.
714 .globl fwnmi_data_area
718 * Vectors for the FWNMI option. Share common code.
721 .globl SystemReset_FWNMI
724 mtspr SPRG1,r13 /* save r13 */
725 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, SystemReset_common)
726 .globl MachineCheck_FWNMI
729 mtspr SPRG1,r13 /* save r13 */
730 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, MachineCheck_common)
733 * Space for the initial segment table
734 * For LPAR, the hypervisor must fill in at least one entry
735 * before we get control (with relocate on)
741 . = (STAB0_PHYS_ADDR + PAGE_SIZE)
746 /*** Common interrupt handlers ***/
748 STD_EXCEPTION_COMMON(0x100, SystemReset, .SystemResetException)
751 * Machine check is different because we use a different
752 * save area: PACA_EXMC instead of PACA_EXGEN.
755 .globl MachineCheck_common
757 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
760 addi r3,r1,STACK_FRAME_OVERHEAD
761 bl .MachineCheckException
764 STD_EXCEPTION_COMMON_LITE(0x900, Decrementer, .timer_interrupt)
765 STD_EXCEPTION_COMMON(0xa00, Trap_0a, .UnknownException)
766 STD_EXCEPTION_COMMON(0xb00, Trap_0b, .UnknownException)
767 STD_EXCEPTION_COMMON(0xd00, SingleStep, .SingleStepException)
768 STD_EXCEPTION_COMMON(0xe00, Trap_0e, .UnknownException)
769 STD_EXCEPTION_COMMON(0xf00, PerformanceMonitor, .PerformanceMonitorException)
770 STD_EXCEPTION_COMMON(0x1300, InstructionBreakpoint, .InstructionBreakpointException)
771 #ifdef CONFIG_ALTIVEC
772 STD_EXCEPTION_COMMON(0x1700, AltivecAssist, .AltivecAssistException)
774 STD_EXCEPTION_COMMON(0x1700, AltivecAssist, .UnknownException)
778 * Here we have detected that the kernel stack pointer is bad.
779 * R9 contains the saved CR, r13 points to the paca,
780 * r10 contains the (bad) kernel stack pointer,
781 * r11 and r12 contain the saved SRR0 and SRR1.
782 * We switch to using the paca guard page as an emergency stack,
783 * save the registers there, and call kernel_bad_stack(), which panics.
786 ld r1,PACAEMERGSP(r13)
787 subi r1,r1,64+INT_FRAME_SIZE
808 addi r11,r1,INT_FRAME_SIZE
813 1: addi r3,r1,STACK_FRAME_OVERHEAD
818 * Return from an exception with minimal checks.
819 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
820 * If interrupts have been enabled, or anything has been
821 * done that might have changed the scheduling status of
822 * any task or sent any task a signal, you should use
823 * ret_from_except or ret_from_except_lite instead of this.
825 fast_exception_return:
828 andi. r3,r12,MSR_RI /* check if RI is set */
842 clrrdi r10,r10,2 /* clear RI (LE is 0 already) */
850 b . /* prevent speculative execution */
854 1: addi r3,r1,STACK_FRAME_OVERHEAD
855 bl .unrecoverable_exception
859 * Here r13 points to the paca, r9 contains the saved CR,
860 * SRR0 and SRR1 are saved in r11 and r12,
861 * r9 - r13 are saved in paca->exgen.
864 .globl DataAccess_common
867 std r10,PACA_EXGEN+EX_DAR(r13)
869 stw r10,PACA_EXGEN+EX_DSISR(r13)
870 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
871 ld r3,PACA_EXGEN+EX_DAR(r13)
872 lwz r4,PACA_EXGEN+EX_DSISR(r13)
874 b .do_hash_page /* Try to handle as hpte fault */
877 .globl InstructionAccess_common
878 InstructionAccess_common:
879 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
883 b .do_hash_page /* Try to handle as hpte fault */
886 .globl HardwareInterrupt_common
887 .globl HardwareInterrupt_entry
888 HardwareInterrupt_common:
889 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
890 HardwareInterrupt_entry:
892 addi r3,r1,STACK_FRAME_OVERHEAD
894 b .ret_from_except_lite
897 .globl Alignment_common
900 std r10,PACA_EXGEN+EX_DAR(r13)
902 stw r10,PACA_EXGEN+EX_DSISR(r13)
903 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
904 ld r3,PACA_EXGEN+EX_DAR(r13)
905 lwz r4,PACA_EXGEN+EX_DSISR(r13)
909 addi r3,r1,STACK_FRAME_OVERHEAD
911 bl .AlignmentException
915 .globl ProgramCheck_common
917 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
919 addi r3,r1,STACK_FRAME_OVERHEAD
921 bl .ProgramCheckException
925 .globl FPUnavailable_common
926 FPUnavailable_common:
927 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
928 bne .load_up_fpu /* if from user, just load it up */
930 addi r3,r1,STACK_FRAME_OVERHEAD
932 bl .KernelFPUnavailableException
936 .globl AltivecUnavailable_common
937 AltivecUnavailable_common:
938 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
939 #ifdef CONFIG_ALTIVEC
940 bne .load_up_altivec /* if from user, just load it up */
943 addi r3,r1,STACK_FRAME_OVERHEAD
945 bl .AltivecUnavailableException
952 _GLOBAL(do_hash_page)
956 andis. r0,r4,0xa450 /* weird error? */
957 bne- .handle_page_fault /* if not, try to insert a HPTE */
959 andis. r0,r4,0x0020 /* Is it a segment table fault? */
960 bne- .do_ste_alloc /* If so handle it */
961 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
964 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
965 * accessing a userspace segment (even from the kernel). We assume
966 * kernel addresses always have the high bit set.
968 rlwinm r4,r4,32-23,29,29 /* DSISR_STORE -> _PAGE_RW */
969 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
970 orc r0,r12,r0 /* MSR_PR | ~high_bit */
971 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
972 ori r4,r4,1 /* add _PAGE_PRESENT */
975 * On iSeries, we soft-disable interrupts here, then
976 * hard-enable interrupts so that the hash_page code can spin on
977 * the hash_table_lock without problems on a shared processor.
982 * r3 contains the faulting address
983 * r4 contains the required access permissions
984 * r5 contains the trap number
986 * at return r3 = 0 for success
988 bl .hash_page /* build HPTE if possible */
989 cmpdi r3,0 /* see if hash_page succeeded */
991 #ifdef DO_SOFT_DISABLE
993 * If we had interrupts soft-enabled at the point where the
994 * DSI/ISI occurred, and an interrupt came in during hash_page,
996 * We jump to ret_from_except_lite rather than fast_exception_return
997 * because ret_from_except_lite will check for and handle pending
998 * interrupts if necessary.
1000 beq .ret_from_except_lite
1001 /* For a hash failure, we don't bother re-enabling interrupts */
1005 * hash_page couldn't handle it, set soft interrupt enable back
1006 * to what it was before the trap. Note that .local_irq_restore
1007 * handles any interrupts pending at this point.
1010 bl .local_irq_restore
1013 beq fast_exception_return /* Return from exception on success */
1014 ble- 12f /* Failure return from hash_page */
1019 /* Here we have a page fault that hash_page can't handle. */
1020 _GLOBAL(handle_page_fault)
1024 addi r3,r1,STACK_FRAME_OVERHEAD
1027 beq+ .ret_from_except_lite
1030 addi r3,r1,STACK_FRAME_OVERHEAD
1035 /* We have a page fault that hash_page could handle but HV refused
1039 addi r3,r1,STACK_FRAME_OVERHEAD
1044 /* here we have a segment miss */
1045 _GLOBAL(do_ste_alloc)
1046 bl .ste_allocate /* try to insert stab entry */
1048 beq+ fast_exception_return
1049 b .handle_page_fault
1052 * r13 points to the PACA, r9 contains the saved CR,
1053 * r11 and r12 contain the saved SRR0 and SRR1.
1054 * r9 - r13 are saved in paca->exslb.
1055 * We assume we aren't going to take any exceptions during this procedure.
1056 * We assume (DAR >> 60) == 0xc.
1059 _GLOBAL(do_stab_bolted)
1060 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1061 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
1063 /* Hash to the primary group */
1064 ld r10,PACASTABVIRT(r13)
1067 rldimi r10,r11,7,52 /* r10 = first ste of the group */
1069 /* Calculate VSID */
1070 /* This is a kernel address, so protovsid = ESID */
1071 ASM_VSID_SCRAMBLE(r11, r9)
1072 rldic r9,r11,12,16 /* r9 = vsid << 12 */
1074 /* Search the primary group for a free entry */
1075 1: ld r11,0(r10) /* Test valid bit of the current ste */
1082 /* Stick for only searching the primary group for now. */
1083 /* At least for now, we use a very simple random castout scheme */
1084 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
1086 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
1089 /* r10 currently points to an ste one past the group of interest */
1090 /* make it point to the randomly selected entry */
1092 or r10,r10,r11 /* r10 is the entry to invalidate */
1094 isync /* mark the entry invalid */
1096 rldicl r11,r11,56,1 /* clear the valid bit */
1101 clrrdi r11,r11,28 /* Get the esid part of the ste */
1104 2: std r9,8(r10) /* Store the vsid part of the ste */
1107 mfspr r11,DAR /* Get the new esid */
1108 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
1109 ori r11,r11,0x90 /* Turn on valid and kp */
1110 std r11,0(r10) /* Put new entry back into the stab */
1114 /* All done -- return from exception. */
1115 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1116 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1118 andi. r10,r12,MSR_RI
1121 mtcrf 0x80,r9 /* restore CR */
1129 ld r9,PACA_EXSLB+EX_R9(r13)
1130 ld r10,PACA_EXSLB+EX_R10(r13)
1131 ld r11,PACA_EXSLB+EX_R11(r13)
1132 ld r12,PACA_EXSLB+EX_R12(r13)
1133 ld r13,PACA_EXSLB+EX_R13(r13)
1135 b . /* prevent speculative execution */
1138 * r13 points to the PACA, r9 contains the saved CR,
1139 * r11 and r12 contain the saved SRR0 and SRR1.
1140 * r3 has the faulting address
1141 * r9 - r13 are saved in paca->exslb.
1142 * r3 is saved in paca->slb_r3
1143 * We assume we aren't going to take any exceptions during this procedure.
1145 _GLOBAL(do_slb_miss)
1148 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1149 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
1151 bl .slb_allocate /* handle it */
1153 /* All done -- return from exception. */
1155 ld r10,PACA_EXSLB+EX_LR(r13)
1156 ld r3,PACA_EXSLB+EX_R3(r13)
1157 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1158 #ifdef CONFIG_PPC_ISERIES
1159 ld r11,PACALPPACA+LPPACASRR0(r13) /* get SRR0 value */
1160 #endif /* CONFIG_PPC_ISERIES */
1164 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
1170 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
1173 #ifdef CONFIG_PPC_ISERIES
1176 #endif /* CONFIG_PPC_ISERIES */
1177 ld r9,PACA_EXSLB+EX_R9(r13)
1178 ld r10,PACA_EXSLB+EX_R10(r13)
1179 ld r11,PACA_EXSLB+EX_R11(r13)
1180 ld r12,PACA_EXSLB+EX_R12(r13)
1181 ld r13,PACA_EXSLB+EX_R13(r13)
1183 b . /* prevent speculative execution */
1186 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
1189 1: addi r3,r1,STACK_FRAME_OVERHEAD
1190 bl .unrecoverable_exception
1195 * On pSeries, secondary processors spin in the following code.
1196 * At entry, r3 = this processor's number (physical cpu id)
1198 _GLOBAL(pseries_secondary_smp_init)
1201 /* turn on 64-bit mode */
1205 /* Copy some CPU settings from CPU 0 */
1206 bl .__restore_cpu_setup
1208 /* Set up a paca value for this processor. Since we have the
1209 * physical cpu id in r3, we need to search the pacas to find
1210 * which logical id maps to our physical one.
1212 LOADADDR(r13, paca) /* Get base vaddr of paca array */
1213 li r5,0 /* logical cpu id */
1214 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
1215 cmpw r6,r24 /* Compare to our id */
1217 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
1222 99: HMT_LOW /* Couldn't find our CPU id */
1225 2: mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1226 /* From now on, r24 is expected to be logica cpuid */
1229 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
1233 /* Create a temp kernel stack for use before relocation is on. */
1234 ld r1,PACAEMERGSP(r13)
1235 subi r1,r1,STACK_FRAME_OVERHEAD
1239 #ifdef SECONDARY_PROCESSORS
1240 bne .__secondary_start
1243 b 3b /* Loop until told to go */
1244 #ifdef CONFIG_PPC_ISERIES
1245 _STATIC(__start_initialization_iSeries)
1246 /* Clear out the BSS */
1247 LOADADDR(r11,__bss_stop)
1248 LOADADDR(r8,__bss_start)
1249 sub r11,r11,r8 /* bss size */
1250 addi r11,r11,7 /* round up to an even double word */
1251 rldicl. r11,r11,61,3 /* shift right by 3 */
1255 mtctr r11 /* zero this many doublewords */
1259 LOADADDR(r1,init_thread_union)
1260 addi r1,r1,THREAD_SIZE
1262 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1264 LOADADDR(r3,cpu_specs)
1265 LOADADDR(r4,cur_cpu_spec)
1269 LOADADDR(r2,__toc_start)
1273 LOADADDR(r9,systemcfg)
1274 SET_REG_TO_CONST(r4, SYSTEMCFG_VIRT_ADDR)
1275 std r4,0(r9) /* set the systemcfg pointer */
1278 SET_REG_TO_CONST(r4, NACA_VIRT_ADDR)
1279 std r4,0(r9) /* set the naca pointer */
1281 /* Get the pointer to the segment table */
1282 ld r6,PACA(r4) /* Get the base paca pointer */
1283 ld r4,PACASTABVIRT(r6)
1285 bl .iSeries_early_setup
1287 /* relocation is on at this point */
1289 b .start_here_common
1290 #endif /* CONFIG_PPC_ISERIES */
1292 #ifdef CONFIG_PPC_MULTIPLATFORM
1296 andi. r0,r3,MSR_IR|MSR_DR
1303 b . /* prevent speculative execution */
1307 * Here is our main kernel entry point. We support currently 2 kind of entries
1308 * depending on the value of r5.
1310 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1313 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1314 * DT block, r4 is a physical pointer to the kernel itself
1317 _GLOBAL(__start_initialization_multiplatform)
1319 * Are we booted from a PROM Of-type client-interface ?
1322 bne .__boot_from_prom /* yes -> prom */
1324 /* Save parameters */
1328 /* Make sure we are running in 64 bits mode */
1331 /* Setup some critical 970 SPRs before switching MMU off */
1332 bl .__970_cpu_preinit
1337 /* Switch off MMU if not already */
1338 LOADADDR(r4, .__after_prom_start - KERNELBASE)
1341 b .__after_prom_start
1343 _STATIC(__boot_from_prom)
1344 /* Save parameters */
1351 /* Make sure we are running in 64 bits mode */
1354 /* put a relocation offset into r3 */
1357 LOADADDR(r2,__toc_start)
1361 /* Relocate the TOC from a virt addr to a real addr */
1364 /* Restore parameters */
1371 /* Do all of the interaction with OF client interface */
1373 /* We never return */
1377 * At this point, r3 contains the physical address we are running at,
1378 * returned by prom_init()
1380 _STATIC(__after_prom_start)
1383 * We need to run with __start at physical address 0.
1384 * This will leave some code in the first 256B of
1385 * real memory, which are reserved for software use.
1386 * The remainder of the first page is loaded with the fixed
1387 * interrupt vectors. The next two pages are filled with
1388 * unknown exception placeholders.
1390 * Note: This process overwrites the OF exception vectors.
1391 * r26 == relocation offset
1396 SET_REG_TO_CONST(r27,KERNELBASE)
1398 li r3,0 /* target addr */
1400 // XXX FIXME: Use phys returned by OF (r30)
1401 sub r4,r27,r26 /* source addr */
1402 /* current address of _start */
1403 /* i.e. where we are running */
1404 /* the source addr */
1406 LOADADDR(r5,copy_to_here) /* # bytes of memory to copy */
1409 li r6,0x100 /* Start offset, the first 0x100 */
1410 /* bytes were copied earlier. */
1412 bl .copy_and_flush /* copy the first n bytes */
1413 /* this includes the code being */
1414 /* executed here. */
1416 LOADADDR(r0, 4f) /* Jump to the copy of this code */
1417 mtctr r0 /* that we just made/relocated */
1420 4: LOADADDR(r5,klimit)
1422 ld r5,0(r5) /* get the value of klimit */
1424 bl .copy_and_flush /* copy the rest */
1425 b .start_here_multiplatform
1427 #endif /* CONFIG_PPC_MULTIPLATFORM */
1430 * Copy routine used to copy the kernel to start at physical address 0
1431 * and flush and invalidate the caches as needed.
1432 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1433 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1435 * Note: this routine *only* clobbers r0, r6 and lr
1437 _GLOBAL(copy_and_flush)
1440 4: li r0,16 /* Use the least common */
1441 /* denominator cache line */
1442 /* size. This results in */
1443 /* extra cache line flushes */
1444 /* but operation is correct. */
1445 /* Can't get cache line size */
1446 /* from NACA as it is being */
1449 mtctr r0 /* put # words/line in ctr */
1450 3: addi r6,r6,8 /* copy a cache line */
1454 dcbst r6,r3 /* write it to memory */
1456 icbi r6,r3 /* flush the icache line */
1468 * load_up_fpu(unused, unused, tsk)
1469 * Disable FP for the task which had the FPU previously,
1470 * and save its floating-point registers in its thread_struct.
1471 * Enables the FPU for use in the kernel on return.
1472 * On SMP we know the fpu is free, since we give it up every
1473 * switch (ie, no lazy save of the FP registers).
1474 * On entry: r13 == 'current' && last_task_used_math != 'current'
1476 _STATIC(load_up_fpu)
1477 mfmsr r5 /* grab the current MSR */
1479 mtmsrd r5 /* enable use of fpu now */
1482 * For SMP, we don't do lazy FPU switching because it just gets too
1483 * horrendously complex, especially when a task switches from one CPU
1484 * to another. Instead we call giveup_fpu in switch_to.
1488 ld r3,last_task_used_math@got(r2)
1492 /* Save FP state to last_task_used_math's THREAD struct */
1496 stfd fr0,THREAD_FPSCR(r4)
1497 /* Disable FP for last_task_used_math */
1499 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1500 li r6,MSR_FP|MSR_FE0|MSR_FE1
1502 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1504 #endif /* CONFIG_SMP */
1505 /* enable use of FP after return */
1506 ld r4,PACACURRENT(r13)
1507 addi r5,r4,THREAD /* Get THREAD */
1508 ld r4,THREAD_FPEXC_MODE(r5)
1512 lfd fr0,THREAD_FPSCR(r5)
1516 /* Update last_task_used_math to 'current' */
1517 subi r4,r5,THREAD /* Back to 'current' */
1519 #endif /* CONFIG_SMP */
1520 /* restore registers and return */
1521 b fast_exception_return
1524 * disable_kernel_fp()
1527 _GLOBAL(disable_kernel_fp)
1529 rldicl r0,r3,(63-MSR_FP_LG),1
1530 rldicl r3,r0,(MSR_FP_LG+1),0
1531 mtmsrd r3 /* disable use of fpu now */
1537 * Disable FP for the task given as the argument,
1538 * and save the floating-point registers in its thread_struct.
1539 * Enables the FPU for use in the kernel on return.
1544 mtmsrd r5 /* enable use of fpu now */
1547 beqlr- /* if no previous owner, done */
1548 addi r3,r3,THREAD /* want THREAD of task */
1553 stfd fr0,THREAD_FPSCR(r3)
1555 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1556 li r3,MSR_FP|MSR_FE0|MSR_FE1
1557 andc r4,r4,r3 /* disable FP for previous task */
1558 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1562 ld r4,last_task_used_math@got(r2)
1564 #endif /* CONFIG_SMP */
1568 #ifdef CONFIG_ALTIVEC
1571 * load_up_altivec(unused, unused, tsk)
1572 * Disable VMX for the task which had it previously,
1573 * and save its vector registers in its thread_struct.
1574 * Enables the VMX for use in the kernel on return.
1575 * On SMP we know the VMX is free, since we give it up every
1576 * switch (ie, no lazy save of the vector registers).
1577 * On entry: r13 == 'current' && last_task_used_altivec != 'current'
1579 _STATIC(load_up_altivec)
1580 mfmsr r5 /* grab the current MSR */
1581 oris r5,r5,MSR_VEC@h
1582 mtmsrd r5 /* enable use of VMX now */
1586 * For SMP, we don't do lazy VMX switching because it just gets too
1587 * horrendously complex, especially when a task switches from one CPU
1588 * to another. Instead we call giveup_altvec in switch_to.
1589 * VRSAVE isn't dealt with here, that is done in the normal context
1590 * switch code. Note that we could rely on vrsave value to eventually
1591 * avoid saving all of the VREGs here...
1594 ld r3,last_task_used_altivec@got(r2)
1598 /* Save VMX state to last_task_used_altivec's THREAD struct */
1604 /* Disable VMX for last_task_used_altivec */
1606 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1609 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1611 #endif /* CONFIG_SMP */
1612 /* Hack: if we get an altivec unavailable trap with VRSAVE
1613 * set to all zeros, we assume this is a broken application
1614 * that fails to set it properly, and thus we switch it to
1617 mfspr r4,SPRN_VRSAVE
1621 mtspr SPRN_VRSAVE,r4
1623 /* enable use of VMX after return */
1624 ld r4,PACACURRENT(r13)
1625 addi r5,r4,THREAD /* Get THREAD */
1626 oris r12,r12,MSR_VEC@h
1630 stw r4,THREAD_USED_VR(r5)
1635 /* Update last_task_used_math to 'current' */
1636 subi r4,r5,THREAD /* Back to 'current' */
1638 #endif /* CONFIG_SMP */
1639 /* restore registers and return */
1640 b fast_exception_return
1643 * disable_kernel_altivec()
1646 _GLOBAL(disable_kernel_altivec)
1648 rldicl r0,r3,(63-MSR_VEC_LG),1
1649 rldicl r3,r0,(MSR_VEC_LG+1),0
1650 mtmsrd r3 /* disable use of VMX now */
1655 * giveup_altivec(tsk)
1656 * Disable VMX for the task given as the argument,
1657 * and save the vector registers in its thread_struct.
1658 * Enables the VMX for use in the kernel on return.
1660 _GLOBAL(giveup_altivec)
1662 oris r5,r5,MSR_VEC@h
1663 mtmsrd r5 /* enable use of VMX now */
1666 beqlr- /* if no previous owner, done */
1667 addi r3,r3,THREAD /* want THREAD of task */
1675 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1677 andc r4,r4,r3 /* disable FP for previous task */
1678 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1682 ld r4,last_task_used_altivec@got(r2)
1684 #endif /* CONFIG_SMP */
1687 #endif /* CONFIG_ALTIVEC */
1690 #ifdef CONFIG_PPC_PMAC
1692 * On PowerMac, secondary processors starts from the reset vector, which
1693 * is temporarily turned into a call to one of the functions below.
1698 .globl pmac_secondary_start_1
1699 pmac_secondary_start_1:
1701 b .pmac_secondary_start
1703 .globl pmac_secondary_start_2
1704 pmac_secondary_start_2:
1706 b .pmac_secondary_start
1708 .globl pmac_secondary_start_3
1709 pmac_secondary_start_3:
1711 b .pmac_secondary_start
1713 _GLOBAL(pmac_secondary_start)
1714 /* turn on 64-bit mode */
1718 /* Copy some CPU settings from CPU 0 */
1719 bl .__restore_cpu_setup
1721 /* pSeries do that early though I don't think we really need it */
1724 mtmsrd r3 /* RI on */
1726 /* Set up a paca value for this processor. */
1727 LOADADDR(r4, paca) /* Get base vaddr of paca array */
1728 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1729 add r13,r13,r4 /* for this processor. */
1730 mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1732 /* Create a temp kernel stack for use before relocation is on. */
1733 ld r1,PACAEMERGSP(r13)
1734 subi r1,r1,STACK_FRAME_OVERHEAD
1736 b .__secondary_start
1738 #endif /* CONFIG_PPC_PMAC */
1741 * This function is called after the master CPU has released the
1742 * secondary processors. The execution environment is relocation off.
1743 * The paca for this processor has the following fields initialized at
1745 * 1. Processor number
1746 * 2. Segment table pointer (virtual address)
1747 * On entry the following are set:
1748 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
1749 * r24 = cpu# (in Linux terms)
1750 * r13 = paca virtual address
1751 * SPRG3 = paca virtual address
1753 _GLOBAL(__secondary_start)
1755 HMT_MEDIUM /* Set thread priority to MEDIUM */
1759 stb r6,PACAPROCENABLED(r13)
1761 #ifndef CONFIG_PPC_ISERIES
1762 /* Initialize the page table pointer register. */
1764 ld r6,0(r6) /* get the value of _SDR1 */
1765 mtspr SDR1,r6 /* set the htab location */
1767 /* Initialize the first segment table (or SLB) entry */
1768 ld r3,PACASTABVIRT(r13) /* get addr of segment table */
1771 /* Initialize the kernel stack. Just a repeat for iSeries. */
1772 LOADADDR(r3,current_set)
1773 sldi r28,r24,3 /* get current_set[cpu#] */
1775 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1776 std r1,PACAKSAVE(r13)
1778 ld r3,PACASTABREAL(r13) /* get raddr of segment table */
1779 ori r4,r3,1 /* turn on valid bit */
1781 #ifdef CONFIG_PPC_ISERIES
1782 li r0,-1 /* hypervisor call */
1784 sldi r3,r3,63 /* 0x8000000000000000 */
1785 ori r3,r3,4 /* 0x8000000000000004 */
1786 sc /* HvCall_setASR */
1789 li r3,SYSTEMCFG_PHYS_ADDR /* r3 = ptr to systemcfg */
1790 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1791 cmpldi r3,PLATFORM_PSERIES_LPAR
1795 cmpwi r3,0x37 /* SStar */
1797 cmpwi r3,0x36 /* IStar */
1799 cmpwi r3,0x34 /* Pulsar */
1801 97: li r3,H_SET_ASR /* hcall = H_SET_ASR */
1802 HVSC /* Invoking hcall */
1804 98: /* !(rpa hypervisor) || !(star) */
1805 mtasr r4 /* set the stab location */
1811 /* enable MMU and jump to start_secondary */
1812 LOADADDR(r3,.start_secondary_prolog)
1813 SET_REG_TO_CONST(r4, MSR_KERNEL)
1814 #ifdef DO_SOFT_DISABLE
1820 b . /* prevent speculative execution */
1823 * Running with relocation on at this point. All we want to do is
1824 * zero the stack back-chain pointer before going into C code.
1826 _GLOBAL(start_secondary_prolog)
1828 std r3,0(r1) /* Zero the stack frame pointer */
1833 * This subroutine clobbers r11 and r12
1835 _GLOBAL(enable_64b_mode)
1836 mfmsr r11 /* grab the current MSR */
1838 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1841 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1847 #ifdef CONFIG_PPC_MULTIPLATFORM
1849 * This is where the main kernel code starts.
1851 _STATIC(start_here_multiplatform)
1852 /* get a new offset, now that the kernel has moved. */
1856 /* Clear out the BSS. It may have been done in prom_init,
1857 * already but that's irrelevant since prom_init will soon
1858 * be detached from the kernel completely. Besides, we need
1859 * to clear it now for kexec-style entry.
1861 LOADADDR(r11,__bss_stop)
1862 LOADADDR(r8,__bss_start)
1863 sub r11,r11,r8 /* bss size */
1864 addi r11,r11,7 /* round up to an even double word */
1865 rldicl. r11,r11,61,3 /* shift right by 3 */
1869 mtctr r11 /* zero this many doublewords */
1876 mtmsrd r6 /* RI on */
1878 /* setup the systemcfg pointer which is needed by *tab_initialize */
1879 LOADADDR(r6,systemcfg)
1880 sub r6,r6,r26 /* addr of the variable systemcfg */
1881 li r27,SYSTEMCFG_PHYS_ADDR
1882 std r27,0(r6) /* set the value of systemcfg */
1884 /* setup the naca pointer which is needed by *tab_initialize */
1886 sub r6,r6,r26 /* addr of the variable naca */
1887 li r27,NACA_PHYS_ADDR
1888 std r27,0(r6) /* set the value of naca */
1891 /* Start up the second thread on cpu 0 */
1894 cmpwi r3,0x34 /* Pulsar */
1896 cmpwi r3,0x36 /* Icestar */
1898 cmpwi r3,0x37 /* SStar */
1900 b 91f /* HMT not supported */
1902 bl .hmt_start_secondary
1906 /* The following gets the stack and TOC set up with the regs */
1907 /* pointing to the real addr of the kernel stack. This is */
1908 /* all done to support the C function call below which sets */
1909 /* up the htab. This is done because we have relocated the */
1910 /* kernel but are still running in real mode. */
1912 LOADADDR(r3,init_thread_union)
1915 /* set up a stack pointer (physical address) */
1916 addi r1,r3,THREAD_SIZE
1918 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1920 /* set up the TOC (physical address) */
1921 LOADADDR(r2,__toc_start)
1926 LOADADDR(r3,cpu_specs)
1928 LOADADDR(r4,cur_cpu_spec)
1933 /* Save some low level config HIDs of CPU0 to be copied to
1934 * other CPUs later on, or used for suspend/resume
1936 bl .__save_cpu_setup
1939 /* Setup a valid physical PACA pointer in SPRG3 for early_setup
1940 * note that boot_cpuid can always be 0 nowadays since there is
1941 * nowhere it can be initialized differently before we reach this
1944 LOADADDR(r27, boot_cpuid)
1948 LOADADDR(r24, paca) /* Get base vaddr of paca array */
1949 mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */
1950 add r13,r13,r24 /* for this processor. */
1951 sub r13,r13,r26 /* convert to physical addr */
1952 mtspr SPRG3,r13 /* PPPBBB: Temp... -Peter */
1954 /* Do very early kernel initializations, including initial hash table,
1955 * stab and slb setup before we turn on relocation. */
1957 /* Restore parameters passed from prom_init/kexec */
1962 ld r3,PACASTABREAL(r13)
1963 ori r4,r3,1 /* turn on valid bit */
1964 li r3,SYSTEMCFG_PHYS_ADDR /* r3 = ptr to systemcfg */
1965 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1966 cmpldi r3,PLATFORM_PSERIES_LPAR
1970 cmpwi r3,0x37 /* SStar */
1972 cmpwi r3,0x36 /* IStar */
1974 cmpwi r3,0x34 /* Pulsar */
1976 97: li r3,H_SET_ASR /* hcall = H_SET_ASR */
1977 HVSC /* Invoking hcall */
1979 98: /* !(rpa hypervisor) || !(star) */
1980 mtasr r4 /* set the stab location */
1982 /* Set SDR1 (hash table pointer) */
1983 li r3,SYSTEMCFG_PHYS_ADDR /* r3 = ptr to systemcfg */
1984 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1985 /* Test if bit 0 is set (LPAR bit) */
1988 LOADADDR(r6,_SDR1) /* Only if NOT LPAR */
1990 ld r6,0(r6) /* get the value of _SDR1 */
1991 mtspr SDR1,r6 /* set the htab location */
1993 LOADADDR(r3,.start_here_common)
1994 SET_REG_TO_CONST(r4, MSR_KERNEL)
1998 b . /* prevent speculative execution */
1999 #endif /* CONFIG_PPC_MULTIPLATFORM */
2001 /* This is where all platforms converge execution */
2002 _STATIC(start_here_common)
2003 /* relocation is on at this point */
2005 /* The following code sets up the SP and TOC now that we are */
2006 /* running with translation enabled. */
2008 LOADADDR(r3,init_thread_union)
2010 /* set up the stack */
2011 addi r1,r3,THREAD_SIZE
2013 stdu r0,-STACK_FRAME_OVERHEAD(r1)
2015 /* Apply the CPUs-specific fixups (nop out sections not relevant
2019 bl .do_cpu_ftr_fixups
2021 /* setup the systemcfg pointer */
2022 LOADADDR(r9,systemcfg)
2023 SET_REG_TO_CONST(r8, SYSTEMCFG_VIRT_ADDR)
2026 /* setup the naca pointer */
2028 SET_REG_TO_CONST(r8, NACA_VIRT_ADDR)
2029 std r8,0(r9) /* set the value of the naca ptr */
2031 LOADADDR(r26, boot_cpuid)
2034 LOADADDR(r24, paca) /* Get base vaddr of paca array */
2035 mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */
2036 add r13,r13,r24 /* for this processor. */
2039 /* ptr to current */
2040 LOADADDR(r4,init_task)
2041 std r4,PACACURRENT(r13)
2045 std r1,PACAKSAVE(r13)
2049 /* Load up the kernel context */
2051 #ifdef DO_SOFT_DISABLE
2053 stb r5,PACAPROCENABLED(r13) /* Soft Disabled */
2055 ori r5,r5,MSR_EE /* Hard Enabled */
2061 _GLOBAL(__setup_cpu_power3)
2066 LOADADDR(r5, hmt_thread_data)
2069 cmpwi r7,0x34 /* Pulsar */
2071 cmpwi r7,0x36 /* Icestar */
2073 cmpwi r7,0x37 /* SStar */
2083 bl .hmt_start_secondary
2086 __hmt_secondary_hold:
2087 LOADADDR(r5, hmt_thread_data)
2097 93: andi. r6,r6,0x3f
2111 b .pseries_secondary_smp_init
2114 _GLOBAL(hmt_start_secondary)
2115 LOADADDR(r4,__hmt_secondary_hold)
2136 #if defined(CONFIG_SMP) && !defined(CONFIG_PPC_ISERIES)
2137 _GLOBAL(smp_release_cpus)
2138 /* All secondary cpus are spinning on a common
2139 * spinloop, release them all now so they can start
2140 * to spin on their individual paca spinloops.
2141 * For non SMP kernels, the secondary cpus never
2142 * get out of the common spinloop.
2145 LOADADDR(r5,__secondary_hold_spinloop)
2149 #endif /* CONFIG_SMP && !CONFIG_PPC_ISERIES */
2153 * We put a few things here that have to be page-aligned.
2154 * This stuff goes at the beginning of the data segment,
2155 * which is page-aligned.
2161 .globl empty_zero_page
2165 .globl swapper_pg_dir
2173 /* 1 page segment table per cpu (max 48, cpu0 allocated at STAB0_PHYS_ADDR) */
2179 * This space gets a copy of optional info passed to us by the bootstrap
2180 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
2184 .space COMMAND_LINE_SIZE