2 * c 2001 PPC64 Team, IBM Corp
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
9 #include <linux/stddef.h>
10 #include <linux/init.h>
11 #include <linux/sched.h>
12 #include <linux/signal.h>
13 #include <linux/cache.h>
14 #include <linux/irq.h>
15 #include <linux/interrupt.h>
17 #include <asm/ppcdebug.h>
20 unsigned char cached_8259[2] = { 0xff, 0xff };
21 #define cached_A1 (cached_8259[0])
22 #define cached_21 (cached_8259[1])
24 static spinlock_t i8259_lock __cacheline_aligned_in_smp = SPIN_LOCK_UNLOCKED;
26 int i8259_pic_irq_offset;
28 int i8259_irq(int cpu)
32 spin_lock/*_irqsave*/(&i8259_lock/*, flags*/);
34 * Perform an interrupt acknowledge cycle on controller 1
41 * Interrupt is cascaded so perform interrupt
42 * acknowledge on controller 2
45 irq = (inb(0xA0) & 7) + 8;
50 * This may be a spurious interrupt
52 * Read the interrupt status register. If the most
53 * significant bit is not set then there is no valid
58 spin_unlock/*_irqrestore*/(&i8259_lock/*, flags*/);
62 spin_unlock/*_irqrestore*/(&i8259_lock/*, flags*/);
66 static void i8259_mask_and_ack_irq(unsigned int irq_nr)
70 spin_lock_irqsave(&i8259_lock, flags);
71 if ( irq_nr >= i8259_pic_irq_offset )
72 irq_nr -= i8259_pic_irq_offset;
75 cached_A1 |= 1 << (irq_nr-8);
76 inb(0xA1); /* DUMMY */
78 outb(0x20,0xA0); /* Non-specific EOI */
79 outb(0x20,0x20); /* Non-specific EOI to cascade */
81 cached_21 |= 1 << irq_nr;
82 inb(0x21); /* DUMMY */
84 outb(0x20,0x20); /* Non-specific EOI */
86 spin_unlock_irqrestore(&i8259_lock, flags);
89 static void i8259_set_irq_mask(int irq_nr)
95 static void i8259_mask_irq(unsigned int irq_nr)
99 spin_lock_irqsave(&i8259_lock, flags);
100 if ( irq_nr >= i8259_pic_irq_offset )
101 irq_nr -= i8259_pic_irq_offset;
103 cached_21 |= 1 << irq_nr;
105 cached_A1 |= 1 << (irq_nr-8);
106 i8259_set_irq_mask(irq_nr);
107 spin_unlock_irqrestore(&i8259_lock, flags);
110 static void i8259_unmask_irq(unsigned int irq_nr)
114 spin_lock_irqsave(&i8259_lock, flags);
115 if ( irq_nr >= i8259_pic_irq_offset )
116 irq_nr -= i8259_pic_irq_offset;
118 cached_21 &= ~(1 << irq_nr);
120 cached_A1 &= ~(1 << (irq_nr-8));
121 i8259_set_irq_mask(irq_nr);
122 spin_unlock_irqrestore(&i8259_lock, flags);
125 static void i8259_end_irq(unsigned int irq)
127 if (!(get_irq_desc(irq)->status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
128 get_irq_desc(irq)->action)
129 i8259_unmask_irq(irq);
132 struct hw_interrupt_type i8259_pic = {
138 i8259_mask_and_ack_irq,
143 void __init i8259_init(void)
147 spin_lock_irqsave(&i8259_lock, flags);
148 /* init master interrupt controller */
149 outb(0x11, 0x20); /* Start init sequence */
150 outb(0x00, 0x21); /* Vector base */
151 outb(0x04, 0x21); /* edge tiggered, Cascade (slave) on IRQ2 */
152 outb(0x01, 0x21); /* Select 8086 mode */
153 outb(0xFF, 0x21); /* Mask all */
154 /* init slave interrupt controller */
155 outb(0x11, 0xA0); /* Start init sequence */
156 outb(0x08, 0xA1); /* Vector base */
157 outb(0x02, 0xA1); /* edge triggered, Cascade (slave) on IRQ2 */
158 outb(0x01, 0xA1); /* Select 8086 mode */
159 outb(0xFF, 0xA1); /* Mask all */
160 outb(cached_A1, 0xA1);
161 outb(cached_21, 0x21);
162 spin_unlock_irqrestore(&i8259_lock, flags);
163 request_irq( i8259_pic_irq_offset + 2, no_action, SA_INTERRUPT,
164 "82c59 secondary cascade", NULL );