2 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
3 * Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
5 * Module name: iSeries_setup.c
8 * Architecture- / platform-specific boot-time initialization code for
9 * the IBM iSeries LPAR. Adapted from original code by Grant Erickson and
10 * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
21 #include <linux/config.h>
22 #include <linux/init.h>
23 #include <linux/threads.h>
24 #include <linux/smp.h>
25 #include <linux/param.h>
26 #include <linux/string.h>
27 #include <linux/bootmem.h>
28 #include <linux/initrd.h>
29 #include <linux/seq_file.h>
30 #include <linux/kdev_t.h>
31 #include <linux/major.h>
32 #include <linux/root_dev.h>
34 #include <asm/processor.h>
35 #include <asm/machdep.h>
38 #include <asm/pgtable.h>
39 #include <asm/mmu_context.h>
40 #include <asm/cputable.h>
41 #include <asm/sections.h>
44 #include "iSeries_setup.h"
47 #include <asm/sections.h>
48 #include <asm/iSeries/LparData.h>
49 #include <asm/iSeries/HvCallHpt.h>
50 #include <asm/iSeries/HvLpConfig.h>
51 #include <asm/iSeries/HvCallEvent.h>
52 #include <asm/iSeries/HvCallSm.h>
53 #include <asm/iSeries/HvCallXm.h>
54 #include <asm/iSeries/ItLpQueue.h>
55 #include <asm/iSeries/IoHriMainStore.h>
56 #include <asm/iSeries/iSeries_proc.h>
57 #include <asm/iSeries/mf.h>
59 extern void hvlog(char *fmt, ...);
62 #define DBG(fmt...) hvlog(fmt)
67 /* Function Prototypes */
68 extern void ppcdbg_initialize(void);
69 extern void tce_init_iSeries(void);
71 static void build_iSeries_Memory_Map(void);
72 static void setup_iSeries_cache_sizes(void);
73 static void iSeries_bolt_kernel(unsigned long saddr, unsigned long eaddr);
74 extern void iSeries_setup_arch(void);
75 extern void iSeries_pci_final_fixup(void);
77 /* Global Variables */
78 static unsigned long procFreqHz;
79 static unsigned long procFreqMhz;
80 static unsigned long procFreqMhzHundreths;
82 static unsigned long tbFreqHz;
83 static unsigned long tbFreqMhz;
84 static unsigned long tbFreqMhzHundreths;
86 int piranha_simulator;
88 extern int rd_size; /* Defined in drivers/block/rd.c */
89 extern unsigned long klimit;
90 extern unsigned long embedded_sysmap_start;
91 extern unsigned long embedded_sysmap_end;
93 extern unsigned long iSeries_recal_tb;
94 extern unsigned long iSeries_recal_titan;
96 static int mf_initialized;
99 unsigned long absStart;
100 unsigned long absEnd;
101 unsigned long logicalStart;
102 unsigned long logicalEnd;
106 * Process the main store vpd to determine where the holes in memory are
107 * and return the number of physical blocks and fill in the array of
110 unsigned long iSeries_process_Condor_mainstore_vpd(struct MemoryBlock *mb_array,
111 unsigned long max_entries)
113 unsigned long holeFirstChunk, holeSizeChunks;
114 unsigned long numMemoryBlocks = 1;
115 struct IoHriMainStoreSegment4 *msVpd =
116 (struct IoHriMainStoreSegment4 *)xMsVpd;
117 unsigned long holeStart = msVpd->nonInterleavedBlocksStartAdr;
118 unsigned long holeEnd = msVpd->nonInterleavedBlocksEndAdr;
119 unsigned long holeSize = holeEnd - holeStart;
121 printk("Mainstore_VPD: Condor\n");
123 * Determine if absolute memory has any
124 * holes so that we can interpret the
125 * access map we get back from the hypervisor
128 mb_array[0].logicalStart = 0;
129 mb_array[0].logicalEnd = 0x100000000;
130 mb_array[0].absStart = 0;
131 mb_array[0].absEnd = 0x100000000;
135 holeStart = holeStart & 0x000fffffffffffff;
136 holeStart = addr_to_chunk(holeStart);
137 holeFirstChunk = holeStart;
138 holeSize = addr_to_chunk(holeSize);
139 holeSizeChunks = holeSize;
140 printk( "Main store hole: start chunk = %0lx, size = %0lx chunks\n",
141 holeFirstChunk, holeSizeChunks );
142 mb_array[0].logicalEnd = holeFirstChunk;
143 mb_array[0].absEnd = holeFirstChunk;
144 mb_array[1].logicalStart = holeFirstChunk;
145 mb_array[1].logicalEnd = 0x100000000 - holeSizeChunks;
146 mb_array[1].absStart = holeFirstChunk + holeSizeChunks;
147 mb_array[1].absEnd = 0x100000000;
149 return numMemoryBlocks;
152 #define MaxSegmentAreas 32
153 #define MaxSegmentAdrRangeBlocks 128
154 #define MaxAreaRangeBlocks 4
156 unsigned long iSeries_process_Regatta_mainstore_vpd(
157 struct MemoryBlock *mb_array, unsigned long max_entries)
159 struct IoHriMainStoreSegment5 *msVpdP =
160 (struct IoHriMainStoreSegment5 *)xMsVpd;
161 unsigned long numSegmentBlocks = 0;
162 u32 existsBits = msVpdP->msAreaExists;
163 unsigned long area_num;
165 printk("Mainstore_VPD: Regatta\n");
167 for (area_num = 0; area_num < MaxSegmentAreas; ++area_num ) {
168 unsigned long numAreaBlocks;
169 struct IoHriMainStoreArea4 *currentArea;
171 if (existsBits & 0x80000000) {
172 unsigned long block_num;
174 currentArea = &msVpdP->msAreaArray[area_num];
175 numAreaBlocks = currentArea->numAdrRangeBlocks;
176 printk("ms_vpd: processing area %2ld blocks=%ld",
177 area_num, numAreaBlocks);
178 for (block_num = 0; block_num < numAreaBlocks;
180 /* Process an address range block */
181 struct MemoryBlock tempBlock;
185 (unsigned long)currentArea->xAdrRangeBlock[block_num].blockStart;
187 (unsigned long)currentArea->xAdrRangeBlock[block_num].blockEnd;
188 tempBlock.logicalStart = 0;
189 tempBlock.logicalEnd = 0;
190 printk("\n block %ld absStart=%016lx absEnd=%016lx",
191 block_num, tempBlock.absStart,
194 for (i = 0; i < numSegmentBlocks; ++i) {
195 if (mb_array[i].absStart ==
199 if (i == numSegmentBlocks) {
200 if (numSegmentBlocks == max_entries)
201 panic("iSeries_process_mainstore_vpd: too many memory blocks");
202 mb_array[numSegmentBlocks] = tempBlock;
205 printk(" (duplicate)");
211 /* Now sort the blocks found into ascending sequence */
212 if (numSegmentBlocks > 1) {
215 for (m = 0; m < numSegmentBlocks - 1; ++m) {
216 for (n = numSegmentBlocks - 1; m < n; --n) {
217 if (mb_array[n].absStart <
218 mb_array[n-1].absStart) {
219 struct MemoryBlock tempBlock;
221 tempBlock = mb_array[n];
222 mb_array[n] = mb_array[n-1];
223 mb_array[n-1] = tempBlock;
229 * Assign "logical" addresses to each block. These
230 * addresses correspond to the hypervisor "bitmap" space.
231 * Convert all addresses into units of 256K chunks.
234 unsigned long i, nextBitmapAddress;
236 printk("ms_vpd: %ld sorted memory blocks\n", numSegmentBlocks);
237 nextBitmapAddress = 0;
238 for (i = 0; i < numSegmentBlocks; ++i) {
239 unsigned long length = mb_array[i].absEnd -
240 mb_array[i].absStart;
242 mb_array[i].logicalStart = nextBitmapAddress;
243 mb_array[i].logicalEnd = nextBitmapAddress + length;
244 nextBitmapAddress += length;
245 printk(" Bitmap range: %016lx - %016lx\n"
246 " Absolute range: %016lx - %016lx\n",
247 mb_array[i].logicalStart,
248 mb_array[i].logicalEnd,
249 mb_array[i].absStart, mb_array[i].absEnd);
250 mb_array[i].absStart = addr_to_chunk(mb_array[i].absStart &
252 mb_array[i].absEnd = addr_to_chunk(mb_array[i].absEnd &
254 mb_array[i].logicalStart =
255 addr_to_chunk(mb_array[i].logicalStart);
256 mb_array[i].logicalEnd = addr_to_chunk(mb_array[i].logicalEnd);
260 return numSegmentBlocks;
263 unsigned long iSeries_process_mainstore_vpd(struct MemoryBlock *mb_array,
264 unsigned long max_entries)
267 unsigned long mem_blocks = 0;
269 if (cur_cpu_spec->cpu_features & CPU_FTR_SLB)
270 mem_blocks = iSeries_process_Regatta_mainstore_vpd(mb_array,
273 mem_blocks = iSeries_process_Condor_mainstore_vpd(mb_array,
276 printk("Mainstore_VPD: numMemoryBlocks = %ld \n", mem_blocks);
277 for (i = 0; i < mem_blocks; ++i) {
278 printk("Mainstore_VPD: block %3ld logical chunks %016lx - %016lx\n"
279 " abs chunks %016lx - %016lx\n",
280 i, mb_array[i].logicalStart, mb_array[i].logicalEnd,
281 mb_array[i].absStart, mb_array[i].absEnd);
286 static void __init iSeries_parse_cmdline(void)
290 /* copy the command line parameter from the primary VSP */
291 HvCallEvent_dmaToSp(cmd_line, 2 * 64* 1024, 256,
292 HvLpDma_Direction_RemoteToLocal);
297 if (!*p || *p == '\n')
304 /*static*/ void __init iSeries_init_early(void)
306 DBG(" -> iSeries_init_early()\n");
310 #if defined(CONFIG_BLK_DEV_INITRD)
312 * If the init RAM disk has been configured and there is
313 * a non-zero starting address for it, set it up
315 if (naca->xRamDisk) {
316 initrd_start = (unsigned long)__va(naca->xRamDisk);
317 initrd_end = initrd_start + naca->xRamDiskSize * PAGE_SIZE;
318 initrd_below_start_ok = 1; // ramdisk in kernel space
319 ROOT_DEV = Root_RAM0;
320 if (((rd_size * 1024) / PAGE_SIZE) < naca->xRamDiskSize)
321 rd_size = (naca->xRamDiskSize * PAGE_SIZE) / 1024;
323 #endif /* CONFIG_BLK_DEV_INITRD */
325 /* ROOT_DEV = MKDEV(VIODASD_MAJOR, 1); */
328 iSeries_recal_tb = get_tb();
329 iSeries_recal_titan = HvCallXm_loadTod();
332 * Cache sizes must be initialized before hpte_init_iSeries is called
333 * as the later need them for flush_icache_range()
335 setup_iSeries_cache_sizes();
338 * Initialize the hash table management pointers
343 * Initialize the DMA/TCE management
348 * Initialize the table which translate Linux physical addresses to
349 * AS/400 absolute addresses
351 build_iSeries_Memory_Map();
353 /* Initialize machine-dependency vectors */
357 if (itLpNaca.xPirEnvironMode == 0)
358 piranha_simulator = 1;
360 /* Associate Lp Event Queue 0 with processor 0 */
361 HvCallEvent_setLpEventQueueInterruptProc(0, 0);
367 /* If we were passed an initrd, set the ROOT_DEV properly if the values
368 * look sensible. If not, clear initrd reference.
370 #ifdef CONFIG_BLK_DEV_INITRD
371 if (initrd_start >= KERNELBASE && initrd_end >= KERNELBASE &&
372 initrd_end > initrd_start)
373 ROOT_DEV = Root_RAM0;
375 initrd_start = initrd_end = 0;
376 #endif /* CONFIG_BLK_DEV_INITRD */
379 iSeries_parse_cmdline();
381 DBG(" <- iSeries_init_early()\n");
385 * The iSeries may have very large memories ( > 128 GB ) and a partition
386 * may get memory in "chunks" that may be anywhere in the 2**52 real
387 * address space. The chunks are 256K in size. To map this to the
388 * memory model Linux expects, the AS/400 specific code builds a
389 * translation table to translate what Linux thinks are "physical"
390 * addresses to the actual real addresses. This allows us to make
391 * it appear to Linux that we have contiguous memory starting at
392 * physical address zero while in fact this could be far from the truth.
393 * To avoid confusion, I'll let the words physical and/or real address
394 * apply to the Linux addresses while I'll use "absolute address" to
395 * refer to the actual hardware real address.
397 * build_iSeries_Memory_Map gets information from the Hypervisor and
398 * looks at the Main Store VPD to determine the absolute addresses
399 * of the memory that has been assigned to our partition and builds
400 * a table used to translate Linux's physical addresses to these
401 * absolute addresses. Absolute addresses are needed when
402 * communicating with the hypervisor (e.g. to build HPT entries)
405 static void __init build_iSeries_Memory_Map(void)
407 u32 loadAreaFirstChunk, loadAreaLastChunk, loadAreaSize;
409 u32 hptFirstChunk, hptLastChunk, hptSizeChunks, hptSizePages;
411 u32 totalChunks,moreChunks;
412 u32 currChunk, thisChunk, absChunk;
416 struct MemoryBlock mb[32];
417 unsigned long numMemoryBlocks, curBlock;
419 /* Chunk size on iSeries is 256K bytes */
420 totalChunks = (u32)HvLpConfig_getMsChunks();
421 klimit = msChunks_alloc(klimit, totalChunks, 1UL << 18);
424 * Get absolute address of our load area
425 * and map it to physical address 0
426 * This guarantees that the loadarea ends up at physical 0
427 * otherwise, it might not be returned by PLIC as the first
431 loadAreaFirstChunk = (u32)addr_to_chunk(itLpNaca.xLoadAreaAddr);
432 loadAreaSize = itLpNaca.xLoadAreaChunks;
435 * Only add the pages already mapped here.
436 * Otherwise we might add the hpt pages
437 * The rest of the pages of the load area
438 * aren't in the HPT yet and can still
439 * be assigned an arbitrary physical address
441 if ((loadAreaSize * 64) > HvPagesToMap)
442 loadAreaSize = HvPagesToMap / 64;
444 loadAreaLastChunk = loadAreaFirstChunk + loadAreaSize - 1;
447 * TODO Do we need to do something if the HPT is in the 64MB load area?
448 * This would be required if the itLpNaca.xLoadAreaChunks includes
452 printk("Mapping load area - physical addr = 0000000000000000\n"
453 " absolute addr = %016lx\n",
454 chunk_to_addr(loadAreaFirstChunk));
455 printk("Load area size %dK\n", loadAreaSize * 256);
457 for (nextPhysChunk = 0; nextPhysChunk < loadAreaSize; ++nextPhysChunk)
458 msChunks.abs[nextPhysChunk] =
459 loadAreaFirstChunk + nextPhysChunk;
462 * Get absolute address of our HPT and remember it so
463 * we won't map it to any physical address
465 hptFirstChunk = (u32)addr_to_chunk(HvCallHpt_getHptAddress());
466 hptSizePages = (u32)HvCallHpt_getHptPages();
467 hptSizeChunks = hptSizePages >> (msChunks.chunk_shift - PAGE_SHIFT);
468 hptLastChunk = hptFirstChunk + hptSizeChunks - 1;
470 printk("HPT absolute addr = %016lx, size = %dK\n",
471 chunk_to_addr(hptFirstChunk), hptSizeChunks * 256);
473 /* Fill in the htab_data structure */
474 /* Fill in size of hashed page table */
475 num_ptegs = hptSizePages *
476 (PAGE_SIZE / (sizeof(HPTE) * HPTES_PER_GROUP));
477 htab_data.htab_num_ptegs = num_ptegs;
478 htab_data.htab_hash_mask = num_ptegs - 1;
481 * The actual hashed page table is in the hypervisor,
482 * we have no direct access
484 htab_data.htab = NULL;
487 * Determine if absolute memory has any
488 * holes so that we can interpret the
489 * access map we get back from the hypervisor
492 numMemoryBlocks = iSeries_process_mainstore_vpd(mb, 32);
495 * Process the main store access map from the hypervisor
496 * to build up our physical -> absolute translation table
501 moreChunks = totalChunks;
504 map = HvCallSm_get64BitsOfAccessMap(itLpNaca.xLpIndex,
506 thisChunk = currChunk;
508 chunkBit = map >> 63;
512 while (thisChunk >= mb[curBlock].logicalEnd) {
514 if (curBlock >= numMemoryBlocks)
515 panic("out of memory blocks");
517 if (thisChunk < mb[curBlock].logicalStart)
518 panic("memory block error");
520 absChunk = mb[curBlock].absStart +
521 (thisChunk - mb[curBlock].logicalStart);
522 if (((absChunk < hptFirstChunk) ||
523 (absChunk > hptLastChunk)) &&
524 ((absChunk < loadAreaFirstChunk) ||
525 (absChunk > loadAreaLastChunk))) {
526 msChunks.abs[nextPhysChunk] = absChunk;
537 * main store size (in chunks) is
538 * totalChunks - hptSizeChunks
539 * which should be equal to
542 systemcfg->physicalMemorySize = chunk_to_addr(nextPhysChunk);
544 /* Bolt kernel mappings for all of memory */
545 iSeries_bolt_kernel(0, systemcfg->physicalMemorySize);
548 lmb_add(0, systemcfg->physicalMemorySize);
549 lmb_analyze(); /* ?? */
550 lmb_reserve(0, __pa(klimit));
554 * Set up the variables that describe the cache line sizes
557 static void __init setup_iSeries_cache_sizes(void)
560 unsigned int procIx = get_paca()->lppaca.xDynHvPhysicalProcIndex;
562 systemcfg->iCacheL1Size =
563 xIoHriProcessorVpd[procIx].xInstCacheSize * 1024;
564 systemcfg->iCacheL1LineSize =
565 xIoHriProcessorVpd[procIx].xInstCacheOperandSize;
566 systemcfg->dCacheL1Size =
567 xIoHriProcessorVpd[procIx].xDataL1CacheSizeKB * 1024;
568 systemcfg->dCacheL1LineSize =
569 xIoHriProcessorVpd[procIx].xDataCacheOperandSize;
570 naca->iCacheL1LinesPerPage = PAGE_SIZE / systemcfg->iCacheL1LineSize;
571 naca->dCacheL1LinesPerPage = PAGE_SIZE / systemcfg->dCacheL1LineSize;
573 i = systemcfg->iCacheL1LineSize;
575 while ((i = (i / 2)))
577 naca->iCacheL1LogLineSize = n;
579 i = systemcfg->dCacheL1LineSize;
581 while ((i = (i / 2)))
583 naca->dCacheL1LogLineSize = n;
585 printk("D-cache line size = %d\n",
586 (unsigned int)systemcfg->dCacheL1LineSize);
587 printk("I-cache line size = %d\n",
588 (unsigned int)systemcfg->iCacheL1LineSize);
592 * Create a pte. Used during initialization only.
594 static void iSeries_make_pte(unsigned long va, unsigned long pa,
597 HPTE local_hpte, rhpte;
598 unsigned long hash, vpn;
601 vpn = va >> PAGE_SHIFT;
602 hash = hpt_hash(vpn, 0);
604 local_hpte.dw1.dword1 = pa | mode;
605 local_hpte.dw0.dword0 = 0;
606 local_hpte.dw0.dw0.avpn = va >> 23;
607 local_hpte.dw0.dw0.bolted = 1; /* bolted */
608 local_hpte.dw0.dw0.v = 1;
610 slot = HvCallHpt_findValid(&rhpte, vpn);
612 /* Must find space in primary group */
613 panic("hash_page: hpte already exists\n");
615 HvCallHpt_addValidate(slot, 0, (HPTE *)&local_hpte );
619 * Bolt the kernel addr space into the HPT
621 static void __init iSeries_bolt_kernel(unsigned long saddr, unsigned long eaddr)
624 unsigned long mode_rw = _PAGE_ACCESSED | _PAGE_COHERENT | PP_RWXX;
627 for (pa = saddr; pa < eaddr ;pa += PAGE_SIZE) {
628 unsigned long ea = (unsigned long)__va(pa);
629 unsigned long vsid = get_kernel_vsid(ea);
630 unsigned long va = (vsid << 28) | (pa & 0xfffffff);
631 unsigned long vpn = va >> PAGE_SHIFT;
632 unsigned long slot = HvCallHpt_findValid(&hpte, vpn);
634 if (hpte.dw0.dw0.v) {
635 /* HPTE exists, so just bolt it */
636 HvCallHpt_setSwBits(slot, 0x10, 0);
637 /* And make sure the pp bits are correct */
638 HvCallHpt_setPp(slot, PP_RWXX);
640 /* No HPTE exists, so create a new bolted one */
641 iSeries_make_pte(va, phys_to_abs(pa), mode_rw);
645 extern unsigned long ppc_proc_freq;
646 extern unsigned long ppc_tb_freq;
651 void __init iSeries_setup_arch(void)
654 unsigned procIx = get_paca()->lppaca.xDynHvPhysicalProcIndex;
656 /* Add an eye catcher and the systemcfg layout version number */
657 strcpy(systemcfg->eye_catcher, "SYSTEMCFG:PPC64");
658 systemcfg->version.major = SYSTEMCFG_MAJOR;
659 systemcfg->version.minor = SYSTEMCFG_MINOR;
661 /* Setup the Lp Event Queue */
663 /* Allocate a page for the Event Stack
664 * The hypervisor wants the absolute real address, so
665 * we subtract out the KERNELBASE and add in the
666 * absolute real address of the kernel load area
668 eventStack = alloc_bootmem_pages(LpEventStackSize);
669 memset(eventStack, 0, LpEventStackSize);
671 /* Invoke the hypervisor to initialize the event stack */
672 HvCallEvent_setLpEventStack(0, eventStack, LpEventStackSize);
674 /* Initialize fields in our Lp Event Queue */
675 xItLpQueue.xSlicEventStackPtr = (char *)eventStack;
676 xItLpQueue.xSlicCurEventPtr = (char *)eventStack;
677 xItLpQueue.xSlicLastValidEventPtr = (char *)eventStack +
678 (LpEventStackSize - LpEventMaxSize);
679 xItLpQueue.xIndex = 0;
681 /* Compute processor frequency */
682 procFreqHz = ((1UL << 34) * 1000000) /
683 xIoHriProcessorVpd[procIx].xProcFreq;
684 procFreqMhz = procFreqHz / 1000000;
685 procFreqMhzHundreths = (procFreqHz / 10000) - (procFreqMhz * 100);
686 ppc_proc_freq = procFreqHz;
688 /* Compute time base frequency */
689 tbFreqHz = ((1UL << 32) * 1000000) /
690 xIoHriProcessorVpd[procIx].xTimeBaseFreq;
691 tbFreqMhz = tbFreqHz / 1000000;
692 tbFreqMhzHundreths = (tbFreqHz / 10000) - (tbFreqMhz * 100);
693 ppc_tb_freq = tbFreqHz;
695 printk("Max logical processors = %d\n",
696 itVpdAreas.xSlicMaxLogicalProcs);
697 printk("Max physical processors = %d\n",
698 itVpdAreas.xSlicMaxPhysicalProcs);
699 printk("Processor frequency = %lu.%02lu\n", procFreqMhz,
700 procFreqMhzHundreths);
701 printk("Time base frequency = %lu.%02lu\n", tbFreqMhz,
703 systemcfg->processor = xIoHriProcessorVpd[procIx].xPVR;
704 printk("Processor version = %x\n", systemcfg->processor);
707 void iSeries_get_cpuinfo(struct seq_file *m)
709 seq_printf(m, "machine\t\t: 64-bit iSeries Logical Partition\n");
716 int iSeries_get_irq(struct pt_regs *regs)
718 /* -2 means ignore this interrupt */
725 void iSeries_restart(char *cmd)
733 void iSeries_power_off(void)
741 void iSeries_halt(void)
747 unsigned long jdh_time = 0;
749 extern void setup_default_decr(void);
752 * void __init iSeries_calibrate_decr()
755 * This routine retrieves the internal processor frequency from the VPD,
756 * and sets up the kernel timer decrementer based on that value.
759 void __init iSeries_calibrate_decr(void)
761 unsigned long cyclesPerUsec;
762 struct div_result divres;
764 /* Compute decrementer (and TB) frequency in cycles/sec */
765 cyclesPerUsec = ppc_tb_freq / 1000000;
768 * Set the amount to refresh the decrementer by. This
769 * is the number of decrementer ticks it takes for
772 tb_ticks_per_jiffy = ppc_tb_freq / HZ;
775 /* TEST CODE FOR ADJTIME */
776 tb_ticks_per_jiffy += tb_ticks_per_jiffy / 5000;
777 /* END OF TEST CODE */
781 * tb_ticks_per_sec = freq; would give better accuracy
782 * but tb_ticks_per_sec = tb_ticks_per_jiffy*HZ; assures
783 * that jiffies (and xtime) will match the time returned
784 * by do_gettimeofday.
786 tb_ticks_per_sec = tb_ticks_per_jiffy * HZ;
787 tb_ticks_per_usec = cyclesPerUsec;
788 tb_to_us = mulhwu_scale_factor(ppc_tb_freq, 1000000);
789 div128_by_32(1024 * 1024, 0, tb_ticks_per_sec, &divres);
790 tb_to_xs = divres.result_low;
791 setup_default_decr();
794 void __init iSeries_progress(char * st, unsigned short code)
796 printk("Progress: [%04x] - %s\n", (unsigned)code, st);
797 if (!piranha_simulator && mf_initialized) {
799 mf_displayProgress(code);
805 static void __init iSeries_fixup_klimit(void)
808 * Change klimit to take into account any ram disk
809 * that may be included
812 klimit = KERNELBASE + (u64)naca->xRamDisk +
813 (naca->xRamDiskSize * PAGE_SIZE);
816 * No ram disk was included - check and see if there
817 * was an embedded system map. Change klimit to take
818 * into account any embedded system map
820 if (embedded_sysmap_end)
821 klimit = KERNELBASE + ((embedded_sysmap_end + 4095) &
826 int __init iSeries_src_init(void)
828 /* clear the progress line */
829 ppc_md.progress(" ", 0xffff);
833 late_initcall(iSeries_src_init);
835 void __init iSeries_early_setup(void)
837 iSeries_fixup_klimit();
839 ppc_md.setup_arch = iSeries_setup_arch;
840 ppc_md.get_cpuinfo = iSeries_get_cpuinfo;
841 ppc_md.init_IRQ = iSeries_init_IRQ;
842 ppc_md.get_irq = iSeries_get_irq;
843 ppc_md.init_early = iSeries_init_early,
845 ppc_md.pcibios_fixup = iSeries_pci_final_fixup;
847 ppc_md.restart = iSeries_restart;
848 ppc_md.power_off = iSeries_power_off;
849 ppc_md.halt = iSeries_halt;
851 ppc_md.get_boot_time = iSeries_get_boot_time;
852 ppc_md.set_rtc_time = iSeries_set_rtc_time;
853 ppc_md.get_rtc_time = iSeries_get_rtc_time;
854 ppc_md.calibrate_decr = iSeries_calibrate_decr;
855 ppc_md.progress = iSeries_progress;