2 * arch/ppc/kernel/open_pic.c -- OpenPIC Interrupt Handling
4 * Copyright (C) 1997 Geert Uytterhoeven
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
11 #include <linux/config.h>
12 #include <linux/types.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/irq.h>
16 #include <linux/smp.h>
17 #include <linux/interrupt.h>
18 #include <asm/ptrace.h>
19 #include <asm/signal.h>
21 #include <asm/pgtable.h>
25 #include <asm/machdep.h>
28 #include "open_pic_defs.h"
30 #include <asm/ppcdebug.h>
33 static volatile struct OpenPIC *OpenPIC = NULL;
34 u_int OpenPIC_NumInitSenses __initdata = 0;
35 u_char *OpenPIC_InitSenses __initdata = NULL;
38 * Local (static) OpenPIC Operations
42 /* Global Operations */
43 static void openpic_reset(void);
44 static void openpic_enable_8259_pass_through(void);
45 static void openpic_disable_8259_pass_through(void);
46 static u_int openpic_irq(void);
47 static void openpic_eoi(void);
48 static u_int openpic_get_priority(void);
49 static void openpic_set_priority(u_int pri);
50 static u_int openpic_get_spurious(void);
51 static void openpic_set_spurious(u_int vector);
54 /* Interprocessor Interrupts */
55 static void openpic_initipi(u_int ipi, u_int pri, u_int vector);
56 static irqreturn_t openpic_ipi_action(int cpl, void *dev_id,
57 struct pt_regs *regs);
60 /* Timer Interrupts */
61 static void openpic_inittimer(u_int timer, u_int pri, u_int vector);
62 static void openpic_maptimer(u_int timer, u_int cpumask);
64 /* Interrupt Sources */
65 static void openpic_enable_irq(u_int irq);
66 static void openpic_disable_irq(u_int irq);
67 static void openpic_initirq(u_int irq, u_int pri, u_int vector, int polarity,
69 static void openpic_mapirq(u_int irq, u_int cpumask);
71 static void find_ISUs(void);
73 static u_int NumProcessors;
74 static u_int NumSources;
76 static int open_pic_irq_offset;
77 static volatile unsigned char* chrp_int_ack_special;
79 OpenPIC_SourcePtr ISU[OPENPIC_MAX_ISU];
81 static void openpic_end_irq(unsigned int irq_nr);
82 static void openpic_set_affinity(unsigned int irq_nr, cpumask_t cpumask);
84 struct hw_interrupt_type open_pic = {
96 static void openpic_end_ipi(unsigned int irq_nr);
97 static void openpic_enable_ipi(unsigned int irq_nr);
98 static void openpic_disable_ipi(unsigned int irq_nr);
100 struct hw_interrupt_type open_pic_ipi = {
110 #endif /* CONFIG_SMP */
112 unsigned int openpic_vec_ipi;
113 unsigned int openpic_vec_timer;
114 unsigned int openpic_vec_spurious;
117 * Accesses to the current processor's openpic registers
120 #define THIS_CPU Processor[cpu]
121 #define DECL_THIS_CPU int cpu = hard_smp_processor_id()
122 #define CHECK_THIS_CPU check_arg_cpu(cpu)
124 #define THIS_CPU Processor[hard_smp_processor_id()]
125 #define DECL_THIS_CPU
126 #define CHECK_THIS_CPU
127 #endif /* CONFIG_SMP */
130 #define check_arg_ipi(ipi) \
131 if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \
132 printk(KERN_ERR "open_pic.c:%d: invalid ipi %d\n", __LINE__, ipi);
133 #define check_arg_timer(timer) \
134 if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \
135 printk(KERN_ERR "open_pic.c:%d: invalid timer %d\n", __LINE__, timer);
136 #define check_arg_vec(vec) \
137 if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \
138 printk(KERN_ERR "open_pic.c:%d: invalid vector %d\n", __LINE__, vec);
139 #define check_arg_pri(pri) \
140 if (pri < 0 || pri >= OPENPIC_NUM_PRI) \
141 printk(KERN_ERR "open_pic.c:%d: invalid priority %d\n", __LINE__, pri);
143 * Print out a backtrace if it's out of range, since if it's larger than NR_IRQ's
144 * data has probably been corrupted and we're going to panic or deadlock later
147 #define check_arg_irq(irq) \
148 if (irq < open_pic_irq_offset || irq >= (NumSources+open_pic_irq_offset)){ \
149 printk(KERN_ERR "open_pic.c:%d: invalid irq %d\n", __LINE__, irq); \
151 #define check_arg_cpu(cpu) \
152 if (cpu < 0 || cpu >= OPENPIC_MAX_PROCESSORS){ \
153 printk(KERN_ERR "open_pic.c:%d: invalid cpu %d\n", __LINE__, cpu); \
156 #define check_arg_ipi(ipi) do {} while (0)
157 #define check_arg_timer(timer) do {} while (0)
158 #define check_arg_vec(vec) do {} while (0)
159 #define check_arg_pri(pri) do {} while (0)
160 #define check_arg_irq(irq) do {} while (0)
161 #define check_arg_cpu(cpu) do {} while (0)
164 #define GET_ISU(source) ISU[(source) >> 4][(source) & 0xf]
166 void __init pSeries_init_openpic(void)
168 struct device_node *np;
171 unsigned char* chrp_int_ack_special = NULL;
172 unsigned char init_senses[NR_IRQS - NUM_ISA_INTERRUPTS];
174 #if defined(CONFIG_VT) && defined(CONFIG_ADB_KEYBOARD) && defined(XMON)
175 struct device_node *kbd;
178 if (!(np = of_find_node_by_name(NULL, "pci"))
179 || !(addrp = (unsigned int *)
180 get_property(np, "8259-interrupt-acknowledge", NULL)))
181 printk(KERN_ERR "Cannot find pci to get ack address\n");
183 chrp_int_ack_special = (unsigned char *)
184 __ioremap(addrp[prom_n_addr_cells(np)-1], 1, _PAGE_NO_CACHE);
185 /* hydra still sets OpenPIC_InitSenses to a static set of values */
186 if (OpenPIC_InitSenses == NULL) {
187 prom_get_irq_senses(init_senses, NUM_ISA_INTERRUPTS, NR_IRQS);
188 OpenPIC_InitSenses = init_senses;
189 OpenPIC_NumInitSenses = NR_IRQS - NUM_ISA_INTERRUPTS;
191 openpic_init(1, NUM_ISA_INTERRUPTS, chrp_int_ack_special, nmi_irq);
192 for (i = 0; i < NUM_ISA_INTERRUPTS; i++)
193 irq_desc[i].handler = &i8259_pic;
197 static inline u_int openpic_read(volatile u_int *addr)
205 static inline void openpic_write(volatile u_int *addr, u_int val)
210 static inline u_int openpic_readfield(volatile u_int *addr, u_int mask)
212 u_int val = openpic_read(addr);
216 static inline void openpic_writefield(volatile u_int *addr, u_int mask,
219 u_int val = openpic_read(addr);
220 openpic_write(addr, (val & ~mask) | (field & mask));
223 static inline void openpic_clearfield(volatile u_int *addr, u_int mask)
225 openpic_writefield(addr, mask, 0);
228 static inline void openpic_setfield(volatile u_int *addr, u_int mask)
230 openpic_writefield(addr, mask, mask);
233 static void openpic_safe_writefield(volatile u_int *addr, u_int mask,
236 unsigned int loops = 100000;
238 openpic_setfield(addr, OPENPIC_MASK);
239 while (openpic_read(addr) & OPENPIC_ACTIVITY) {
241 printk(KERN_ERR "openpic_safe_writefield timeout\n");
245 openpic_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
250 static int broken_ipi_registers;
252 static u_int openpic_read_IPI(volatile u_int* addr)
256 if (broken_ipi_registers)
257 /* yes this is right ... bug, feature, you decide! -- tgall */
265 static void openpic_test_broken_IPI(void)
269 openpic_write(&OpenPIC->Global.IPI_Vector_Priority(0), OPENPIC_MASK);
270 t = openpic_read(&OpenPIC->Global.IPI_Vector_Priority(0));
271 if (t == le32_to_cpu(OPENPIC_MASK)) {
272 printk(KERN_INFO "OpenPIC reversed IPI registers detected\n");
273 broken_ipi_registers = 1;
277 /* because of the power3 be / le above, this is needed */
278 static inline void openpic_writefield_IPI(volatile u_int* addr, u_int mask, u_int field)
280 u_int val = openpic_read_IPI(addr);
281 openpic_write(addr, (val & ~mask) | (field & mask));
284 static inline void openpic_clearfield_IPI(volatile u_int *addr, u_int mask)
286 openpic_writefield_IPI(addr, mask, 0);
289 static inline void openpic_setfield_IPI(volatile u_int *addr, u_int mask)
291 openpic_writefield_IPI(addr, mask, mask);
294 static void openpic_safe_writefield_IPI(volatile u_int *addr, u_int mask, u_int field)
296 unsigned int loops = 100000;
298 openpic_setfield_IPI(addr, OPENPIC_MASK);
300 /* wait until it's not in use */
301 /* BenH: Is this code really enough ? I would rather check the result
302 * and eventually retry ...
304 while(openpic_read_IPI(addr) & OPENPIC_ACTIVITY) {
306 printk(KERN_ERR "openpic_safe_writefield timeout\n");
311 openpic_writefield_IPI(addr, mask, field | OPENPIC_MASK);
313 #endif /* CONFIG_SMP */
315 void __init openpic_init(int main_pic, int offset, unsigned char* chrp_ack,
316 int programmer_switch_irq)
323 printk(KERN_INFO "No OpenPIC found !\n");
326 OpenPIC = (volatile struct OpenPIC *)OpenPIC_Addr;
328 ppc64_boot_msg(0x20, "OpenPic Init");
330 t = openpic_read(&OpenPIC->Global.Feature_Reporting0);
331 switch (t & OPENPIC_FEATURE_VERSION_MASK) {
345 NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >>
346 OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1;
347 NumSources = ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >>
348 OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1;
349 printk(KERN_INFO "OpenPIC Version %s (%d CPUs and %d IRQ sources) at %p\n",
350 version, NumProcessors, NumSources, OpenPIC);
351 timerfreq = openpic_read(&OpenPIC->Global.Timer_Frequency);
353 printk(KERN_INFO "OpenPIC timer frequency is %d.%06d MHz\n",
354 timerfreq / 1000000, timerfreq % 1000000);
359 open_pic_irq_offset = offset;
360 chrp_int_ack_special = (volatile unsigned char*)chrp_ack;
364 /* Initialize timer interrupts */
365 ppc64_boot_msg(0x21, "OpenPic Timer");
366 for (i = 0; i < OPENPIC_NUM_TIMERS; i++) {
367 /* Disabled, Priority 0 */
368 openpic_inittimer(i, 0, openpic_vec_timer+i);
370 openpic_maptimer(i, 0);
374 /* Initialize IPI interrupts */
375 ppc64_boot_msg(0x22, "OpenPic IPI");
376 openpic_test_broken_IPI();
377 for (i = 0; i < OPENPIC_NUM_IPI; i++) {
378 /* Disabled, Priority 10..13 */
379 openpic_initipi(i, 10+i, openpic_vec_ipi+i);
380 /* IPIs are per-CPU */
381 irq_desc[openpic_vec_ipi+i].status |= IRQ_PER_CPU;
382 irq_desc[openpic_vec_ipi+i].handler = &open_pic_ipi;
386 /* Initialize external interrupts */
387 ppc64_boot_msg(0x23, "OpenPic Ext");
389 openpic_set_priority(0xf);
391 /* SIOint (8259 cascade) is special */
393 openpic_initirq(0, 8, offset, 1, 1);
394 openpic_mapirq(0, 1 << get_hard_smp_processor_id(boot_cpuid));
397 /* Init all external sources */
398 for (i = 0; i < NumSources; i++) {
401 /* skip cascade if any */
402 if (offset && i == 0)
404 /* the bootloader may have left it enabled (bad !) */
405 openpic_disable_irq(i+offset);
407 pri = (i == programmer_switch_irq)? 9: 8;
408 sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: 1;
410 irq_desc[i+offset].status = IRQ_LEVEL;
412 /* Enabled, Priority 8 or 9 */
413 openpic_initirq(i, pri, i+offset, !sense, sense);
415 openpic_mapirq(i, 1 << get_hard_smp_processor_id(boot_cpuid));
418 /* Init descriptors */
419 for (i = offset; i < NumSources + offset; i++)
420 irq_desc[i].handler = &open_pic;
422 /* Initialize the spurious interrupt */
423 ppc64_boot_msg(0x24, "OpenPic Spurious");
424 openpic_set_spurious(openpic_vec_spurious);
426 openpic_set_priority(0);
427 openpic_disable_8259_pass_through();
429 ppc64_boot_msg(0x25, "OpenPic Done");
433 * We cant do this in init_IRQ because we need the memory subsystem up for
436 static int __init openpic_setup_i8259(void)
438 if (systemcfg->platform == PLATFORM_POWERMAC)
441 if (naca->interrupt_controller == IC_OPEN_PIC) {
442 /* Initialize the cascade */
443 if (request_irq(NUM_ISA_INTERRUPTS, no_action, SA_INTERRUPT,
444 "82c59 cascade", NULL))
445 printk(KERN_ERR "Unable to get OpenPIC IRQ 0 for cascade\n");
451 arch_initcall(openpic_setup_i8259);
453 void openpic_setup_ISU(int isu_num, unsigned long addr)
455 if (isu_num >= OPENPIC_MAX_ISU)
457 ISU[isu_num] = (OpenPIC_SourcePtr) __ioremap(addr, 0x400, _PAGE_NO_CACHE);
458 if (isu_num >= NumISUs)
459 NumISUs = isu_num + 1;
464 /* For PowerMac, setup ISUs on base openpic */
465 if (systemcfg->platform == PLATFORM_POWERMAC) {
467 for (i=0; i<128; i+=0x10) {
468 ISU[i>>4] = &((struct OpenPIC *)OpenPIC_Addr)->Source[i];
472 /* Use /interrupt-controller/reg and
473 * /interrupt-controller/interrupt-ranges from OF device tree
474 * the ISU array is setup in chrp_pci.c in ibm_add_bridges
479 /* basically each ISU is a bus, and this assumes that
480 * open_pic_isu_count interrupts per bus are possible
481 * ISU == Interrupt Source
483 * On G5, we keep the original NumSources provided by the controller,
484 * it's below 128, so we have room to stuff the IPIs and timers like darwin
485 * does. We put the spurrious vector up at 0xff though.
487 if (systemcfg->platform == PLATFORM_POWERMAC) {
488 openpic_vec_ipi = NumSources;
489 openpic_vec_timer = openpic_vec_ipi + 4;
490 openpic_vec_spurious = 0xff;
492 NumSources = NumISUs * 0x10;
494 openpic_vec_ipi = NumSources + open_pic_irq_offset;
495 openpic_vec_timer = openpic_vec_ipi + OPENPIC_NUM_IPI;
496 openpic_vec_spurious = openpic_vec_timer + OPENPIC_NUM_TIMERS;
500 static inline void openpic_reset(void)
502 openpic_setfield(&OpenPIC->Global.Global_Configuration0,
503 OPENPIC_CONFIG_RESET);
506 static inline void openpic_enable_8259_pass_through(void)
508 openpic_clearfield(&OpenPIC->Global.Global_Configuration0,
509 OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
512 static void openpic_disable_8259_pass_through(void)
514 openpic_setfield(&OpenPIC->Global.Global_Configuration0,
515 OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
519 * Find out the current interrupt
521 static u_int openpic_irq(void)
527 vec = openpic_readfield(&OpenPIC->THIS_CPU.Interrupt_Acknowledge,
528 OPENPIC_VECTOR_MASK);
532 static void openpic_eoi(void)
537 openpic_write(&OpenPIC->THIS_CPU.EOI, 0);
538 /* Handle PCI write posting */
539 (void)openpic_read(&OpenPIC->THIS_CPU.EOI);
543 static inline u_int openpic_get_priority(void)
548 return openpic_readfield(&OpenPIC->THIS_CPU.Current_Task_Priority,
549 OPENPIC_CURRENT_TASK_PRIORITY_MASK);
552 static void openpic_set_priority(u_int pri)
558 openpic_writefield(&OpenPIC->THIS_CPU.Current_Task_Priority,
559 OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri);
563 * Get/set the spurious vector
565 static inline u_int openpic_get_spurious(void)
567 return openpic_readfield(&OpenPIC->Global.Spurious_Vector,
568 OPENPIC_VECTOR_MASK);
571 static void openpic_set_spurious(u_int vec)
574 openpic_writefield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK,
579 * Convert a cpu mask from logical to physical cpu numbers.
581 static inline u32 physmask(u32 cpumask)
586 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
587 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
591 void openpic_init_processor(u_int cpumask)
593 openpic_write(&OpenPIC->Global.Processor_Initialization,
594 physmask(cpumask & cpus_addr(cpu_online_map)[0]));
599 * Initialize an interprocessor interrupt (and disable it)
601 * ipi: OpenPIC interprocessor interrupt number
602 * pri: interrupt source priority
603 * vec: the vector it will produce
605 static void __init openpic_initipi(u_int ipi, u_int pri, u_int vec)
610 openpic_safe_writefield_IPI(&OpenPIC->Global.IPI_Vector_Priority(ipi),
611 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
612 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
616 * Send an IPI to one or more CPUs
618 * Externally called, however, it takes an IPI number (0...OPENPIC_NUM_IPI)
619 * and not a system-wide interrupt number
621 void openpic_cause_IPI(u_int ipi, u_int cpumask)
627 openpic_write(&OpenPIC->THIS_CPU.IPI_Dispatch(ipi),
628 physmask(cpumask & cpus_addr(cpu_online_map)[0]));
631 void openpic_request_IPIs(void)
636 * Make sure this matches what is defined in smp.c for
637 * smp_message_{pass|recv}() or what shows up in
638 * /proc/interrupts will be wrong!!! --Troy */
643 /* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */
644 request_irq(openpic_vec_ipi, openpic_ipi_action, SA_INTERRUPT,
645 "IPI0 (call function)", NULL);
646 request_irq(openpic_vec_ipi+1, openpic_ipi_action, SA_INTERRUPT,
647 "IPI1 (reschedule)", NULL);
648 request_irq(openpic_vec_ipi+2, openpic_ipi_action, SA_INTERRUPT,
649 "IPI2 (unused)", NULL);
650 request_irq(openpic_vec_ipi+3, openpic_ipi_action, SA_INTERRUPT,
651 "IPI3 (debugger break)", NULL);
653 for ( i = 0; i < OPENPIC_NUM_IPI ; i++ )
654 openpic_enable_ipi(openpic_vec_ipi+i);
658 * Do per-cpu setup for SMP systems.
660 * Get IPI's working and start taking interrupts.
663 static spinlock_t openpic_setup_lock __devinitdata = SPIN_LOCK_UNLOCKED;
665 void __devinit do_openpic_setup_cpu(void)
667 #ifdef CONFIG_IRQ_ALL_CPUS
669 u32 msk = 1 << hard_smp_processor_id();
672 spin_lock(&openpic_setup_lock);
674 #ifdef CONFIG_IRQ_ALL_CPUS
675 /* let the openpic know we want intrs. default affinity
676 * is 0xffffffff until changed via /proc
677 * That's how it's done on x86. If we want it differently, then
678 * we should make sure we also change the default values of irq_affinity
681 for (i = 0; i < NumSources ; i++)
682 openpic_mapirq(i, openpic_read(&GET_ISU(i).Destination) | msk);
683 #endif /* CONFIG_IRQ_ALL_CPUS */
684 openpic_set_priority(0);
686 spin_unlock(&openpic_setup_lock);
688 #endif /* CONFIG_SMP */
691 * Initialize a timer interrupt (and disable it)
693 * timer: OpenPIC timer number
694 * pri: interrupt source priority
695 * vec: the vector it will produce
697 static void __init openpic_inittimer(u_int timer, u_int pri, u_int vec)
699 check_arg_timer(timer);
702 openpic_safe_writefield(&OpenPIC->Global.Timer[timer].Vector_Priority,
703 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
704 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
708 * Map a timer interrupt to one or more CPUs
710 static void __init openpic_maptimer(u_int timer, u_int cpumask)
712 check_arg_timer(timer);
713 openpic_write(&OpenPIC->Global.Timer[timer].Destination,
714 physmask(cpumask & cpus_addr(cpu_online_map)[0]));
720 * All functions below take an offset'ed irq argument
726 * Enable/disable an external interrupt source
728 * Externally called, irq is an offseted system-wide interrupt number
730 static void openpic_enable_irq(u_int irq)
732 unsigned int loops = 100000;
735 openpic_clearfield(&GET_ISU(irq - open_pic_irq_offset).Vector_Priority, OPENPIC_MASK);
736 /* make sure mask gets to controller before we return to user */
739 printk(KERN_ERR "openpic_enable_irq timeout\n");
743 mb(); /* sync is probably useless here */
744 } while(openpic_readfield(&GET_ISU(irq - open_pic_irq_offset).Vector_Priority,
748 static void openpic_disable_irq(u_int irq)
751 unsigned int loops = 100000;
755 openpic_setfield(&GET_ISU(irq - open_pic_irq_offset).Vector_Priority, OPENPIC_MASK);
756 /* make sure mask gets to controller before we return to user */
759 printk(KERN_ERR "openpic_disable_irq timeout\n");
763 mb(); /* sync is probably useless here */
764 vp = openpic_readfield(&GET_ISU(irq - open_pic_irq_offset).Vector_Priority,
765 OPENPIC_MASK | OPENPIC_ACTIVITY);
766 } while((vp & OPENPIC_ACTIVITY) && !(vp & OPENPIC_MASK));
771 * Enable/disable an IPI interrupt source
773 * Externally called, irq is an offseted system-wide interrupt number
775 void openpic_enable_ipi(u_int irq)
777 irq -= openpic_vec_ipi;
779 openpic_clearfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK);
782 void openpic_disable_ipi(u_int irq)
784 /* NEVER disable an IPI... that's just plain wrong! */
790 * Initialize an interrupt source (and disable it!)
792 * irq: OpenPIC interrupt number
793 * pri: interrupt source priority
794 * vec: the vector it will produce
795 * pol: polarity (1 for positive, 0 for negative)
796 * sense: 1 for level, 0 for edge
798 static void openpic_initirq(u_int irq, u_int pri, u_int vec, int pol, int sense)
800 openpic_safe_writefield(&GET_ISU(irq).Vector_Priority,
801 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
802 OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK,
803 (pri << OPENPIC_PRIORITY_SHIFT) | vec |
804 (pol ? OPENPIC_POLARITY_POSITIVE :
805 OPENPIC_POLARITY_NEGATIVE) |
806 (sense ? OPENPIC_SENSE_LEVEL : OPENPIC_SENSE_EDGE));
810 * Map an interrupt source to one or more CPUs
812 static void openpic_mapirq(u_int irq, u_int physmask)
814 openpic_write(&GET_ISU(irq).Destination, physmask);
818 * Set the sense for an interrupt source (and disable it!)
820 * sense: 1 for level, 0 for edge
823 static void openpic_set_sense(u_int irq, int sense)
825 openpic_safe_writefield(&GET_ISU(irq).Vector_Priority,
827 (sense ? OPENPIC_SENSE_LEVEL : 0));
830 static int openpic_get_sense(u_int irq)
832 return openpic_readfield(&GET_ISU(irq).Vector_Priority,
833 OPENPIC_SENSE_LEVEL) != 0;
837 static void openpic_end_irq(unsigned int irq_nr)
842 static void openpic_set_affinity(unsigned int irq_nr, cpumask_t cpumask)
846 cpus_and(tmp, cpumask, cpu_online_map);
847 openpic_mapirq(irq_nr - open_pic_irq_offset, physmask(cpus_addr(tmp)[0]));
851 static void openpic_end_ipi(unsigned int irq_nr)
854 * IPIs are marked IRQ_PER_CPU. This has the side effect of
855 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
856 * applying to them. We EOI them late to avoid re-entering.
857 * We mark IPI's with SA_INTERRUPT as they must run with
863 static irqreturn_t openpic_ipi_action(int cpl, void *dev_id,
864 struct pt_regs *regs)
866 smp_message_recv(cpl-openpic_vec_ipi, regs);
870 #endif /* CONFIG_SMP */
872 int openpic_get_irq(struct pt_regs *regs)
874 extern int i8259_irq(int cpu);
876 int irq = openpic_irq();
878 if (open_pic_irq_offset && irq == open_pic_irq_offset) {
880 * This magic address generates a PCI IACK cycle.
882 if ( chrp_int_ack_special )
883 irq = *chrp_int_ack_special;
885 irq = i8259_irq( smp_processor_id() );
888 if (irq == openpic_vec_spurious)