2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
14 #include <linux/config.h>
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/delay.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/capability.h>
21 #include <linux/sched.h>
22 #include <linux/errno.h>
23 #include <linux/bootmem.h>
24 #include <linux/module.h>
27 #include <asm/processor.h>
30 #include <asm/pci-bridge.h>
31 #include <asm/byteorder.h>
33 #include <asm/uaccess.h>
34 #include <asm/ppcdebug.h>
36 #include <asm/iommu.h>
37 #include <asm/machdep.h>
41 unsigned long pci_probe_only = 1;
42 unsigned long pci_assign_all_buses = 0;
44 unsigned int pcibios_assign_all_busses(void)
46 return pci_assign_all_buses;
49 /* pci_io_base -- the base address from which io bars are offsets.
50 * This is the lowest I/O base address (so bar values are always positive),
51 * and it *must* be the start of ISA space if an ISA bus exists because
52 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
53 * page is mapped and isa_io_limit prevents access to it.
55 unsigned long isa_io_base; /* NULL if no ISA bus */
56 unsigned long pci_io_base;
58 void pcibios_name_device(struct pci_dev* dev);
59 void pcibios_final_fixup(void);
60 static void fixup_broken_pcnet32(struct pci_dev* dev);
61 static void fixup_windbond_82c105(struct pci_dev* dev);
62 extern void fixup_k2_sata(struct pci_dev* dev);
64 void iSeries_pcibios_init(void);
66 struct pci_controller *hose_head;
67 struct pci_controller **hose_tail = &hose_head;
69 struct pci_dma_ops pci_dma_ops;
70 EXPORT_SYMBOL(pci_dma_ops);
72 int global_phb_number; /* Global phb counter */
74 /* Cached ISA bridge dev. */
75 struct pci_dev *ppc64_isabridge_dev = NULL;
77 struct pci_fixup pcibios_fixups[] = {
78 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID,
79 fixup_broken_pcnet32 },
80 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
81 fixup_windbond_82c105 },
82 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID,
83 pcibios_name_device },
84 #ifdef CONFIG_PPC_PMAC
85 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SERVERWORKS, 0x0240,
91 static void fixup_broken_pcnet32(struct pci_dev* dev)
93 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
94 dev->vendor = PCI_VENDOR_ID_AMD;
95 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
100 static void fixup_windbond_82c105(struct pci_dev* dev)
102 /* Assume the windbond 82c105 is the IDE controller on a
103 * p610. We should probably be more careful in case
104 * someone tries to plug in a similar adapter.
109 printk("Using INTC for W82c105 IDE controller.\n");
110 pci_read_config_dword(dev, 0x40, ®);
111 /* Enable LEGIRQ to use INTC instead of ISA interrupts */
112 pci_write_config_dword(dev, 0x40, reg | (1<<11));
114 for (i = 0; i < DEVICE_COUNT_RESOURCE; ++i) {
115 /* zap the 2nd function of the winbond chip */
116 if (dev->resource[i].flags & IORESOURCE_IO
117 && dev->bus->number == 0 && dev->devfn == 0x81)
118 dev->resource[i].flags &= ~IORESOURCE_IO;
123 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
124 struct resource *res)
126 unsigned long offset = 0;
127 struct pci_controller *hose = PCI_GET_PHB_PTR(dev);
132 if (res->flags & IORESOURCE_IO)
133 offset = (unsigned long)hose->io_base_virt - pci_io_base;
135 if (res->flags & IORESOURCE_MEM)
136 offset = hose->pci_mem_offset;
138 region->start = res->start - offset;
139 region->end = res->end - offset;
142 #ifdef CONFIG_HOTPLUG
143 EXPORT_SYMBOL(pcibios_resource_to_bus);
147 * We need to avoid collisions with `mirrored' VGA ports
148 * and other strange ISA hardware, so we always want the
149 * addresses to be allocated in the 0x000-0x0ff region
152 * Why? Because some silly external IO cards only decode
153 * the low 10 bits of the IO address. The 0x00-0xff region
154 * is reserved for motherboard devices that decode all 16
155 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
156 * but we want to try to avoid allocating at 0x2900-0x2bff
157 * which might have be mirrored at 0x0100-0x03ff..
159 void pcibios_align_resource(void *data, struct resource *res,
160 unsigned long size, unsigned long align)
162 struct pci_dev *dev = data;
163 struct pci_controller *hose = PCI_GET_PHB_PTR(dev);
164 unsigned long start = res->start;
165 unsigned long alignto;
167 if (res->flags & IORESOURCE_IO) {
168 unsigned long offset = (unsigned long)hose->io_base_virt -
170 /* Make sure we start at our min on all hoses */
171 if (start - offset < PCIBIOS_MIN_IO)
172 start = PCIBIOS_MIN_IO + offset;
175 * Put everything into 0x00-0xff region modulo 0x400
178 start = (start + 0x3ff) & ~0x3ff;
180 } else if (res->flags & IORESOURCE_MEM) {
181 /* Make sure we start at our min on all hoses */
182 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
183 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
185 /* Align to multiple of size of minimum base. */
186 alignto = max(0x1000UL, align);
187 start = ALIGN(start, alignto);
194 * Allocate pci_controller(phb) initialized common variables.
196 struct pci_controller * __init
197 pci_alloc_pci_controller(enum phb_types controller_type)
199 struct pci_controller *hose;
202 #ifdef CONFIG_PPC_ISERIES
203 hose = (struct pci_controller *)kmalloc(sizeof(struct pci_controller), GFP_KERNEL);
205 hose = (struct pci_controller *)alloc_bootmem(sizeof(struct pci_controller));
208 printk(KERN_ERR "PCI: Allocate pci_controller failed.\n");
211 memset(hose, 0, sizeof(struct pci_controller));
213 switch(controller_type) {
214 #ifdef CONFIG_PPC_ISERIES
215 case phb_type_hypervisor:
219 case phb_type_python:
222 case phb_type_speedwagon:
225 case phb_type_winnipeg:
236 if(strlen(model) < 8)
237 strcpy(hose->what,model);
239 memcpy(hose->what,model,7);
240 hose->type = controller_type;
241 hose->global_number = global_phb_number++;
244 hose_tail = &hose->next;
248 static void __init pcibios_claim_one_bus(struct pci_bus *b)
250 struct list_head *ld;
251 struct pci_bus *child_bus;
253 for (ld = b->devices.next; ld != &b->devices; ld = ld->next) {
254 struct pci_dev *dev = pci_dev_b(ld);
257 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
258 struct resource *r = &dev->resource[i];
260 if (r->parent || !r->start || !r->flags)
262 pci_claim_resource(dev, i);
266 list_for_each_entry(child_bus, &b->children, node)
267 pcibios_claim_one_bus(child_bus);
270 #ifndef CONFIG_PPC_ISERIES
271 static void __init pcibios_claim_of_setup(void)
273 struct list_head *lb;
275 for (lb = pci_root_buses.next; lb != &pci_root_buses; lb = lb->next) {
276 struct pci_bus *b = pci_bus_b(lb);
277 pcibios_claim_one_bus(b);
282 static int __init pcibios_init(void)
284 struct pci_controller *hose;
287 #ifdef CONFIG_PPC_ISERIES
288 iSeries_pcibios_init();
291 //ppc64_boot_msg(0x40, "PCI Probe");
292 printk("PCI: Probing PCI hardware\n");
294 /* Scan all of the recorded PCI controllers. */
295 for (hose = hose_head; hose; hose = hose->next) {
296 hose->last_busno = 0xff;
297 bus = pci_scan_bus(hose->first_busno, hose->ops,
300 hose->last_busno = bus->subordinate;
303 #ifndef CONFIG_PPC_ISERIES
305 pcibios_claim_of_setup();
307 /* FIXME: `else' will be removed when
308 pci_assign_unassigned_resources() is able to work
309 correctly with [partially] allocated PCI tree. */
310 pci_assign_unassigned_resources();
313 /* Call machine dependent final fixup */
314 if (ppc_md.pcibios_fixup)
315 ppc_md.pcibios_fixup();
317 /* Cache the location of the ISA bridge (if we have one) */
318 ppc64_isabridge_dev = pci_find_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
319 if (ppc64_isabridge_dev != NULL)
320 printk("ISA bridge at %s\n", pci_name(ppc64_isabridge_dev));
322 printk("PCI: Probing PCI hardware done\n");
323 //ppc64_boot_msg(0x41, "PCI Done");
325 #ifdef CONFIG_PPC_PSERIES
326 pci_addr_cache_build();
332 subsys_initcall(pcibios_init);
334 char __init *pcibios_setup(char *str)
339 int pcibios_enable_device(struct pci_dev *dev, int mask)
344 pci_read_config_word(dev, PCI_COMMAND, &cmd);
347 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
348 struct resource *res = &dev->resource[i];
350 /* Only set up the requested stuff */
351 if (!(mask & (1<<i)))
354 if (res->flags & IORESOURCE_IO)
355 cmd |= PCI_COMMAND_IO;
356 if (res->flags & IORESOURCE_MEM)
357 cmd |= PCI_COMMAND_MEMORY;
361 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
363 /* Enable the appropriate bits in the PCI command register. */
364 pci_write_config_word(dev, PCI_COMMAND, cmd);
370 * Return the domain number for this bus.
372 int pci_domain_nr(struct pci_bus *bus)
374 #ifdef CONFIG_PPC_ISERIES
377 struct pci_controller *hose = PCI_GET_PHB_PTR(bus);
379 return hose->global_number;
383 EXPORT_SYMBOL(pci_domain_nr);
385 /* Set the name of the bus as it appears in /proc/bus/pci */
386 int pci_name_bus(char *name, struct pci_bus *bus)
388 #ifndef CONFIG_PPC_ISERIES
389 struct pci_controller *hose = PCI_GET_PHB_PTR(bus);
392 sprintf(name, "%04x:%02x", pci_domain_nr(bus), bus->number);
395 sprintf(name, "%02x", bus->number);
401 * Platform support for /proc/bus/pci/X/Y mmap()s,
402 * modelled on the sparc64 implementation by Dave Miller.
407 * Adjust vm_pgoff of VMA such that it is the physical page offset
408 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
410 * Basically, the user finds the base address for his device which he wishes
411 * to mmap. They read the 32-bit value from the config space base register,
412 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
413 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
415 * Returns negative error code on failure, zero on success.
417 static __inline__ int
418 __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
419 enum pci_mmap_state mmap_state)
421 struct pci_controller *hose = PCI_GET_PHB_PTR(dev);
422 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
423 unsigned long io_offset = 0;
427 return -EINVAL; /* should never happen */
429 /* If memory, add on the PCI bridge address offset */
430 if (mmap_state == pci_mmap_mem) {
431 offset += hose->pci_mem_offset;
432 res_bit = IORESOURCE_MEM;
434 io_offset = (unsigned long)hose->io_base_virt;
436 res_bit = IORESOURCE_IO;
440 * Check that the offset requested corresponds to one of the
441 * resources of the device.
443 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
444 struct resource *rp = &dev->resource[i];
445 int flags = rp->flags;
447 /* treat ROM as memory (should be already) */
448 if (i == PCI_ROM_RESOURCE)
449 flags |= IORESOURCE_MEM;
451 /* Active and same type? */
452 if ((flags & res_bit) == 0)
455 /* In the range of this resource? */
456 if (offset < (rp->start & PAGE_MASK) || offset > rp->end)
459 /* found it! construct the final physical address */
460 if (mmap_state == pci_mmap_io)
461 offset += hose->io_base_phys - io_offset;
463 vma->vm_pgoff = offset >> PAGE_SHIFT;
471 * Set vm_flags of VMA, as appropriate for this architecture, for a pci device
474 static __inline__ void
475 __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
476 enum pci_mmap_state mmap_state)
478 vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO;
482 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
485 static __inline__ void
486 __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
487 enum pci_mmap_state mmap_state, int write_combine)
489 long prot = pgprot_val(vma->vm_page_prot);
491 /* XXX would be nice to have a way to ask for write-through */
492 prot |= _PAGE_NO_CACHE;
494 prot |= _PAGE_GUARDED;
495 vma->vm_page_prot = __pgprot(prot);
499 * Perform the actual remap of the pages for a PCI device mapping, as
500 * appropriate for this architecture. The region in the process to map
501 * is described by vm_start and vm_end members of VMA, the base physical
502 * address is found in vm_pgoff.
503 * The pci device structure is provided so that architectures may make mapping
504 * decisions on a per-device or per-bus basis.
506 * Returns a negative error code on failure, zero on success.
508 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
509 enum pci_mmap_state mmap_state,
514 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
518 __pci_mmap_set_flags(dev, vma, mmap_state);
519 __pci_mmap_set_pgprot(dev, vma, mmap_state, write_combine);
521 ret = remap_page_range(vma, vma->vm_start, vma->vm_pgoff << PAGE_SHIFT,
522 vma->vm_end - vma->vm_start, vma->vm_page_prot);
527 #ifdef CONFIG_PPC_PSERIES
528 static ssize_t pci_show_devspec(struct device *dev, char *buf)
530 struct pci_dev *pdev;
531 struct device_node *np;
533 pdev = to_pci_dev (dev);
534 np = pci_device_to_OF_node(pdev);
535 if (np == NULL || np->full_name == NULL)
537 return sprintf(buf, "%s", np->full_name);
539 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
540 #endif /* CONFIG_PPC_PSERIES */
542 void pcibios_add_platform_entries(struct pci_dev *pdev)
544 #ifdef CONFIG_PPC_PSERIES
545 device_create_file(&pdev->dev, &dev_attr_devspec);
546 #endif /* CONFIG_PPC_PSERIES */